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19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/dma-mapping.h>
22#include <linux/wait.h>
23#include <linux/mutex.h>
24#include <linux/slab.h>
25#include <linux/mtd/mtd.h>
26#include <linux/module.h>
27
28#include "denali.h"
29
30MODULE_LICENSE("GPL");
31
32
33
34
35
36#define NAND_DEFAULT_TIMINGS -1
37
38static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
39module_param(onfi_timing_mode, int, S_IRUGO);
40MODULE_PARM_DESC(onfi_timing_mode,
41 "Overrides default ONFI setting. -1 indicates use default timings");
42
43#define DENALI_NAND_NAME "denali-nand"
44
45
46
47
48
49#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
50 INTR_STATUS__ECC_TRANSACTION_DONE | \
51 INTR_STATUS__ECC_ERR | \
52 INTR_STATUS__PROGRAM_FAIL | \
53 INTR_STATUS__LOAD_COMP | \
54 INTR_STATUS__PROGRAM_COMP | \
55 INTR_STATUS__TIME_OUT | \
56 INTR_STATUS__ERASE_FAIL | \
57 INTR_STATUS__RST_COMP | \
58 INTR_STATUS__ERASE_COMP)
59
60
61
62
63
64#define CHIP_SELECT_INVALID -1
65
66#define SUPPORT_8BITECC 1
67
68
69
70
71
72#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
73
74
75
76
77
78#define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
79
80
81
82
83
84#define SPARE_ACCESS 0x41
85#define MAIN_ACCESS 0x42
86#define MAIN_SPARE_ACCESS 0x43
87#define PIPELINE_ACCESS 0x2000
88
89#define DENALI_READ 0
90#define DENALI_WRITE 0x100
91
92
93#define COMMAND_CYCLE 0
94#define ADDR_CYCLE 1
95#define STATUS_CYCLE 2
96
97
98
99
100
101#define BANK(x) ((x) << 24)
102
103
104static void clear_interrupts(struct denali_nand_info *denali);
105static uint32_t wait_for_irq(struct denali_nand_info *denali,
106 uint32_t irq_mask);
107static void denali_irq_enable(struct denali_nand_info *denali,
108 uint32_t int_mask);
109static uint32_t read_interrupt_status(struct denali_nand_info *denali);
110
111
112
113
114
115
116
117static void index_addr(struct denali_nand_info *denali,
118 uint32_t address, uint32_t data)
119{
120 iowrite32(address, denali->flash_mem);
121 iowrite32(data, denali->flash_mem + 0x10);
122}
123
124
125static void index_addr_read_data(struct denali_nand_info *denali,
126 uint32_t address, uint32_t *pdata)
127{
128 iowrite32(address, denali->flash_mem);
129 *pdata = ioread32(denali->flash_mem + 0x10);
130}
131
132
133
134
135
136static void reset_buf(struct denali_nand_info *denali)
137{
138 denali->buf.head = denali->buf.tail = 0;
139}
140
141static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
142{
143 denali->buf.buf[denali->buf.tail++] = byte;
144}
145
146
147static void read_status(struct denali_nand_info *denali)
148{
149 uint32_t cmd;
150
151
152 reset_buf(denali);
153
154 cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
155 if (cmd)
156 write_byte_to_buf(denali, NAND_STATUS_WP);
157 else
158 write_byte_to_buf(denali, 0);
159}
160
161
162static void reset_bank(struct denali_nand_info *denali)
163{
164 uint32_t irq_status;
165 uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
166
167 clear_interrupts(denali);
168
169 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
170
171 irq_status = wait_for_irq(denali, irq_mask);
172
173 if (irq_status & INTR_STATUS__TIME_OUT)
174 dev_err(denali->dev, "reset bank failed.\n");
175}
176
177
178static uint16_t denali_nand_reset(struct denali_nand_info *denali)
179{
180 int i;
181
182 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
183 __FILE__, __LINE__, __func__);
184
185 for (i = 0; i < denali->max_banks; i++)
186 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
187 denali->flash_reg + INTR_STATUS(i));
188
189 for (i = 0; i < denali->max_banks; i++) {
190 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
191 while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) &
192 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
193 cpu_relax();
194 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
195 INTR_STATUS__TIME_OUT)
196 dev_dbg(denali->dev,
197 "NAND Reset operation timed out on bank %d\n", i);
198 }
199
200 for (i = 0; i < denali->max_banks; i++)
201 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
202 denali->flash_reg + INTR_STATUS(i));
203
204 return PASS;
205}
206
207
208
209
210
211
212static void nand_onfi_timing_set(struct denali_nand_info *denali,
213 uint16_t mode)
214{
215 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
216 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
217 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
218 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
219 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
220 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
221 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
222 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
223 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
224 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
225 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
226 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
227
228 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
229 uint16_t dv_window = 0;
230 uint16_t en_lo, en_hi;
231 uint16_t acc_clks;
232 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
233
234 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
235 __FILE__, __LINE__, __func__);
236
237 en_lo = CEIL_DIV(Trp[mode], CLK_X);
238 en_hi = CEIL_DIV(Treh[mode], CLK_X);
239#if ONFI_BLOOM_TIME
240 if ((en_hi * CLK_X) < (Treh[mode] + 2))
241 en_hi++;
242#endif
243
244 if ((en_lo + en_hi) * CLK_X < Trc[mode])
245 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
246
247 if ((en_lo + en_hi) < CLK_MULTI)
248 en_lo += CLK_MULTI - en_lo - en_hi;
249
250 while (dv_window < 8) {
251 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
252
253 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
254
255 data_invalid = data_invalid_rhoh < data_invalid_rloh ?
256 data_invalid_rhoh : data_invalid_rloh;
257
258 dv_window = data_invalid - Trea[mode];
259
260 if (dv_window < 8)
261 en_lo++;
262 }
263
264 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
265
266 while (acc_clks * CLK_X - Trea[mode] < 3)
267 acc_clks++;
268
269 if (data_invalid - acc_clks * CLK_X < 2)
270 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
271 __FILE__, __LINE__);
272
273 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
274 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
275 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
276 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
277 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
278 if (cs_cnt == 0)
279 cs_cnt = 1;
280
281 if (Tcea[mode]) {
282 while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode])
283 cs_cnt++;
284 }
285
286#if MODE5_WORKAROUND
287 if (mode == 5)
288 acc_clks = 5;
289#endif
290
291
292 if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 &&
293 ioread32(denali->flash_reg + DEVICE_ID) == 0x88)
294 acc_clks = 6;
295
296 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
297 iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
298 iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
299 iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
300 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
301 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
302 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
303 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
304}
305
306
307static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
308{
309 int i;
310
311
312
313
314
315 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
316 ONFI_TIMING_MODE__VALUE))
317 return FAIL;
318
319 for (i = 5; i > 0; i--) {
320 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
321 (0x01 << i))
322 break;
323 }
324
325 nand_onfi_timing_set(denali, i);
326
327
328
329
330
331
332
333
334 return PASS;
335}
336
337static void get_samsung_nand_para(struct denali_nand_info *denali,
338 uint8_t device_id)
339{
340 if (device_id == 0xd3) {
341
342 iowrite32(5, denali->flash_reg + ACC_CLKS);
343 iowrite32(20, denali->flash_reg + RE_2_WE);
344 iowrite32(12, denali->flash_reg + WE_2_RE);
345 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
346 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
347 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
348 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
349 }
350}
351
352static void get_toshiba_nand_para(struct denali_nand_info *denali)
353{
354 uint32_t tmp;
355
356
357
358
359
360 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
361 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
362 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
363 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
364 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
365 iowrite32(tmp,
366 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
367#if SUPPORT_15BITECC
368 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
369#elif SUPPORT_8BITECC
370 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
371#endif
372 }
373}
374
375static void get_hynix_nand_para(struct denali_nand_info *denali,
376 uint8_t device_id)
377{
378 uint32_t main_size, spare_size;
379
380 switch (device_id) {
381 case 0xD5:
382 case 0xD7:
383 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
384 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
385 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
386 main_size = 4096 *
387 ioread32(denali->flash_reg + DEVICES_CONNECTED);
388 spare_size = 224 *
389 ioread32(denali->flash_reg + DEVICES_CONNECTED);
390 iowrite32(main_size,
391 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
392 iowrite32(spare_size,
393 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
394 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
395#if SUPPORT_15BITECC
396 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
397#elif SUPPORT_8BITECC
398 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
399#endif
400 break;
401 default:
402 dev_warn(denali->dev,
403 "Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
404 "Will use default parameter values instead.\n",
405 device_id);
406 }
407}
408
409
410
411
412
413static void find_valid_banks(struct denali_nand_info *denali)
414{
415 uint32_t id[denali->max_banks];
416 int i;
417
418 denali->total_used_banks = 1;
419 for (i = 0; i < denali->max_banks; i++) {
420 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
421 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
422 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
423
424 dev_dbg(denali->dev,
425 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
426
427 if (i == 0) {
428 if (!(id[i] & 0x0ff))
429 break;
430 } else {
431 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
432 denali->total_used_banks++;
433 else
434 break;
435 }
436 }
437
438 if (denali->platform == INTEL_CE4100) {
439
440
441
442
443
444 if (denali->total_used_banks != 1) {
445 dev_err(denali->dev,
446 "Sorry, Intel CE4100 only supports a single NAND device.\n");
447 BUG();
448 }
449 }
450 dev_dbg(denali->dev,
451 "denali->total_used_banks: %d\n", denali->total_used_banks);
452}
453
454
455
456
457
458static void detect_max_banks(struct denali_nand_info *denali)
459{
460 uint32_t features = ioread32(denali->flash_reg + FEATURES);
461
462 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
463}
464
465static void detect_partition_feature(struct denali_nand_info *denali)
466{
467
468
469
470
471
472
473
474 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
475 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
476 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
477 denali->fwblks =
478 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
479 MIN_MAX_BANK__MIN_VALUE) *
480 denali->blksperchip)
481 +
482 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
483 MIN_BLK_ADDR__VALUE);
484 } else {
485 denali->fwblks = SPECTRA_START_BLOCK;
486 }
487 } else {
488 denali->fwblks = SPECTRA_START_BLOCK;
489 }
490}
491
492static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
493{
494 uint16_t status = PASS;
495 uint32_t id_bytes[8], addr;
496 uint8_t maf_id, device_id;
497 int i;
498
499 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
500 __FILE__, __LINE__, __func__);
501
502
503
504
505
506
507 addr = MODE_11 | BANK(denali->flash_bank);
508 index_addr(denali, addr | 0, 0x90);
509 index_addr(denali, addr | 1, 0);
510 for (i = 0; i < 8; i++)
511 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
512 maf_id = id_bytes[0];
513 device_id = id_bytes[1];
514
515 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
516 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) {
517 if (FAIL == get_onfi_nand_para(denali))
518 return FAIL;
519 } else if (maf_id == 0xEC) {
520 get_samsung_nand_para(denali, device_id);
521 } else if (maf_id == 0x98) {
522 get_toshiba_nand_para(denali);
523 } else if (maf_id == 0xAD) {
524 get_hynix_nand_para(denali, device_id);
525 }
526
527 dev_info(denali->dev,
528 "Dump timing register values:\n"
529 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
530 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
531 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
532 ioread32(denali->flash_reg + ACC_CLKS),
533 ioread32(denali->flash_reg + RE_2_WE),
534 ioread32(denali->flash_reg + RE_2_RE),
535 ioread32(denali->flash_reg + WE_2_RE),
536 ioread32(denali->flash_reg + ADDR_2_DATA),
537 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
538 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
539 ioread32(denali->flash_reg + CS_SETUP_CNT));
540
541 find_valid_banks(denali);
542
543 detect_partition_feature(denali);
544
545
546
547
548
549 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
550 nand_onfi_timing_set(denali, onfi_timing_mode);
551
552 return status;
553}
554
555static void denali_set_intr_modes(struct denali_nand_info *denali,
556 uint16_t INT_ENABLE)
557{
558 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
559 __FILE__, __LINE__, __func__);
560
561 if (INT_ENABLE)
562 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
563 else
564 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
565}
566
567
568
569
570
571static inline bool is_flash_bank_valid(int flash_bank)
572{
573 return flash_bank >= 0 && flash_bank < 4;
574}
575
576static void denali_irq_init(struct denali_nand_info *denali)
577{
578 uint32_t int_mask;
579 int i;
580
581
582 denali_set_intr_modes(denali, false);
583
584 int_mask = DENALI_IRQ_ALL;
585
586
587 for (i = 0; i < denali->max_banks; ++i)
588 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
589
590 denali_irq_enable(denali, int_mask);
591}
592
593static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
594{
595 denali_set_intr_modes(denali, false);
596 free_irq(irqnum, denali);
597}
598
599static void denali_irq_enable(struct denali_nand_info *denali,
600 uint32_t int_mask)
601{
602 int i;
603
604 for (i = 0; i < denali->max_banks; ++i)
605 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
606}
607
608
609
610
611
612static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
613{
614 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
615}
616
617
618static inline void clear_interrupt(struct denali_nand_info *denali,
619 uint32_t irq_mask)
620{
621 uint32_t intr_status_reg;
622
623 intr_status_reg = INTR_STATUS(denali->flash_bank);
624
625 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
626}
627
628static void clear_interrupts(struct denali_nand_info *denali)
629{
630 uint32_t status;
631
632 spin_lock_irq(&denali->irq_lock);
633
634 status = read_interrupt_status(denali);
635 clear_interrupt(denali, status);
636
637 denali->irq_status = 0x0;
638 spin_unlock_irq(&denali->irq_lock);
639}
640
641static uint32_t read_interrupt_status(struct denali_nand_info *denali)
642{
643 uint32_t intr_status_reg;
644
645 intr_status_reg = INTR_STATUS(denali->flash_bank);
646
647 return ioread32(denali->flash_reg + intr_status_reg);
648}
649
650
651
652
653
654static irqreturn_t denali_isr(int irq, void *dev_id)
655{
656 struct denali_nand_info *denali = dev_id;
657 uint32_t irq_status;
658 irqreturn_t result = IRQ_NONE;
659
660 spin_lock(&denali->irq_lock);
661
662
663 if (is_flash_bank_valid(denali->flash_bank)) {
664
665
666
667
668 irq_status = denali_irq_detected(denali);
669 if (irq_status != 0) {
670
671
672 clear_interrupt(denali, irq_status);
673
674
675
676
677 denali->irq_status |= irq_status;
678
679 complete(&denali->complete);
680
681 result = IRQ_HANDLED;
682 }
683 }
684 spin_unlock(&denali->irq_lock);
685 return result;
686}
687#define BANK(x) ((x) << 24)
688
689static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
690{
691 unsigned long comp_res;
692 uint32_t intr_status;
693 unsigned long timeout = msecs_to_jiffies(1000);
694
695 do {
696 comp_res =
697 wait_for_completion_timeout(&denali->complete, timeout);
698 spin_lock_irq(&denali->irq_lock);
699 intr_status = denali->irq_status;
700
701 if (intr_status & irq_mask) {
702 denali->irq_status &= ~irq_mask;
703 spin_unlock_irq(&denali->irq_lock);
704
705 break;
706 }
707
708
709
710
711
712 spin_unlock_irq(&denali->irq_lock);
713 } while (comp_res != 0);
714
715 if (comp_res == 0) {
716
717 pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
718 intr_status, irq_mask);
719
720 intr_status = 0;
721 }
722 return intr_status;
723}
724
725
726
727
728
729static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
730 bool transfer_spare)
731{
732 int ecc_en_flag, transfer_spare_flag;
733
734
735 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
736 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
737
738
739 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
740 iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
741}
742
743
744
745
746
747static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
748 bool ecc_en, bool transfer_spare,
749 int access_type, int op)
750{
751 int status = PASS;
752 uint32_t page_count = 1;
753 uint32_t addr, cmd, irq_status, irq_mask;
754
755 if (op == DENALI_READ)
756 irq_mask = INTR_STATUS__LOAD_COMP;
757 else if (op == DENALI_WRITE)
758 irq_mask = 0;
759 else
760 BUG();
761
762 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
763
764 clear_interrupts(denali);
765
766 addr = BANK(denali->flash_bank) | denali->page;
767
768 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
769 cmd = MODE_01 | addr;
770 iowrite32(cmd, denali->flash_mem);
771 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
772
773 cmd = MODE_10 | addr;
774 index_addr(denali, cmd, access_type);
775
776 cmd = MODE_01 | addr;
777 iowrite32(cmd, denali->flash_mem);
778 } else if (op == DENALI_READ) {
779
780 cmd = MODE_10 | addr;
781 index_addr(denali, cmd, access_type);
782
783
784
785
786
787
788 if (access_type == SPARE_ACCESS) {
789 cmd = MODE_01 | addr;
790 iowrite32(cmd, denali->flash_mem);
791 } else {
792 index_addr(denali, cmd,
793 PIPELINE_ACCESS | op | page_count);
794
795
796
797
798
799
800 irq_status = wait_for_irq(denali, irq_mask);
801
802 if (irq_status == 0) {
803 dev_err(denali->dev,
804 "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n",
805 cmd, denali->page, addr);
806 status = FAIL;
807 } else {
808 cmd = MODE_01 | addr;
809 iowrite32(cmd, denali->flash_mem);
810 }
811 }
812 }
813 return status;
814}
815
816
817static int write_data_to_flash_mem(struct denali_nand_info *denali,
818 const uint8_t *buf, int len)
819{
820 uint32_t *buf32;
821 int i;
822
823
824
825
826
827 BUG_ON((len % 4) != 0);
828
829
830 buf32 = (uint32_t *)buf;
831 for (i = 0; i < len / 4; i++)
832 iowrite32(*buf32++, denali->flash_mem + 0x10);
833 return i * 4;
834}
835
836
837static int read_data_from_flash_mem(struct denali_nand_info *denali,
838 uint8_t *buf, int len)
839{
840 uint32_t *buf32;
841 int i;
842
843
844
845
846
847
848
849 BUG_ON((len % 4) != 0);
850
851
852 buf32 = (uint32_t *)buf;
853 for (i = 0; i < len / 4; i++)
854 *buf32++ = ioread32(denali->flash_mem + 0x10);
855 return i * 4;
856}
857
858
859static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
860{
861 struct denali_nand_info *denali = mtd_to_denali(mtd);
862 uint32_t irq_status;
863 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
864 INTR_STATUS__PROGRAM_FAIL;
865 int status = 0;
866
867 denali->page = page;
868
869 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
870 DENALI_WRITE) == PASS) {
871 write_data_to_flash_mem(denali, buf, mtd->oobsize);
872
873
874 irq_status = wait_for_irq(denali, irq_mask);
875
876 if (irq_status == 0) {
877 dev_err(denali->dev, "OOB write failed\n");
878 status = -EIO;
879 }
880 } else {
881 dev_err(denali->dev, "unable to send pipeline command\n");
882 status = -EIO;
883 }
884 return status;
885}
886
887
888static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
889{
890 struct denali_nand_info *denali = mtd_to_denali(mtd);
891 uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
892 uint32_t irq_status, addr, cmd;
893
894 denali->page = page;
895
896 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
897 DENALI_READ) == PASS) {
898 read_data_from_flash_mem(denali, buf, mtd->oobsize);
899
900
901
902
903
904
905 irq_status = wait_for_irq(denali, irq_mask);
906
907 if (irq_status == 0)
908 dev_err(denali->dev, "page on OOB timeout %d\n",
909 denali->page);
910
911
912
913
914
915
916
917
918 addr = BANK(denali->flash_bank) | denali->page;
919 cmd = MODE_10 | addr;
920 index_addr(denali, cmd, MAIN_ACCESS);
921 }
922}
923
924
925
926
927
928static bool is_erased(uint8_t *buf, int len)
929{
930 int i;
931
932 for (i = 0; i < len; i++)
933 if (buf[i] != 0xFF)
934 return false;
935 return true;
936}
937#define ECC_SECTOR_SIZE 512
938
939#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
940#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
941#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
942#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
943#define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
944#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
945
946static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
947 uint32_t irq_status, unsigned int *max_bitflips)
948{
949 bool check_erased_page = false;
950 unsigned int bitflips = 0;
951
952 if (irq_status & INTR_STATUS__ECC_ERR) {
953
954 uint32_t err_address, err_correction_info, err_byte,
955 err_sector, err_device, err_correction_value;
956 denali_set_intr_modes(denali, false);
957
958 do {
959 err_address = ioread32(denali->flash_reg +
960 ECC_ERROR_ADDRESS);
961 err_sector = ECC_SECTOR(err_address);
962 err_byte = ECC_BYTE(err_address);
963
964 err_correction_info = ioread32(denali->flash_reg +
965 ERR_CORRECTION_INFO);
966 err_correction_value =
967 ECC_CORRECTION_VALUE(err_correction_info);
968 err_device = ECC_ERR_DEVICE(err_correction_info);
969
970 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
971
972
973
974
975
976
977
978
979 if (err_byte < ECC_SECTOR_SIZE) {
980 int offset;
981
982 offset = (err_sector *
983 ECC_SECTOR_SIZE +
984 err_byte) *
985 denali->devnum +
986 err_device;
987
988 buf[offset] ^= err_correction_value;
989 denali->mtd.ecc_stats.corrected++;
990 bitflips++;
991 }
992 } else {
993
994
995
996
997
998 check_erased_page = true;
999 }
1000 } while (!ECC_LAST_ERR(err_correction_info));
1001
1002
1003
1004
1005
1006 while (!(read_interrupt_status(denali) &
1007 INTR_STATUS__ECC_TRANSACTION_DONE))
1008 cpu_relax();
1009 clear_interrupts(denali);
1010 denali_set_intr_modes(denali, true);
1011 }
1012 *max_bitflips = bitflips;
1013 return check_erased_page;
1014}
1015
1016
1017static void denali_enable_dma(struct denali_nand_info *denali, bool en)
1018{
1019 iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
1020 ioread32(denali->flash_reg + DMA_ENABLE);
1021}
1022
1023
1024static void denali_setup_dma(struct denali_nand_info *denali, int op)
1025{
1026 uint32_t mode;
1027 const int page_count = 1;
1028 uint32_t addr = denali->buf.dma_buf;
1029
1030 mode = MODE_10 | BANK(denali->flash_bank);
1031
1032
1033
1034
1035 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1036
1037
1038 index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
1039
1040
1041 index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
1042
1043
1044 index_addr(denali, mode | 0x14000, 0x2400);
1045}
1046
1047
1048
1049
1050
1051static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
1052 const uint8_t *buf, bool raw_xfer)
1053{
1054 struct denali_nand_info *denali = mtd_to_denali(mtd);
1055 dma_addr_t addr = denali->buf.dma_buf;
1056 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1057 uint32_t irq_status;
1058 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1059 INTR_STATUS__PROGRAM_FAIL;
1060
1061
1062
1063
1064
1065
1066 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1067
1068
1069 memcpy(denali->buf.buf, buf, mtd->writesize);
1070
1071 if (raw_xfer) {
1072
1073 memcpy(denali->buf.buf + mtd->writesize,
1074 chip->oob_poi,
1075 mtd->oobsize);
1076 }
1077
1078 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
1079
1080 clear_interrupts(denali);
1081 denali_enable_dma(denali, true);
1082
1083 denali_setup_dma(denali, DENALI_WRITE);
1084
1085
1086 irq_status = wait_for_irq(denali, irq_mask);
1087
1088 if (irq_status == 0) {
1089 dev_err(denali->dev, "timeout on write_page (type = %d)\n",
1090 raw_xfer);
1091 denali->status = NAND_STATUS_FAIL;
1092 }
1093
1094 denali_enable_dma(denali, false);
1095 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
1096
1097 return 0;
1098}
1099
1100
1101
1102
1103
1104
1105
1106
1107static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1108 const uint8_t *buf, int oob_required)
1109{
1110
1111
1112
1113
1114 return write_page(mtd, chip, buf, false);
1115}
1116
1117
1118
1119
1120
1121
1122static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1123 const uint8_t *buf, int oob_required)
1124{
1125
1126
1127
1128
1129 return write_page(mtd, chip, buf, true);
1130}
1131
1132static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1133 int page)
1134{
1135 return write_oob_data(mtd, chip->oob_poi, page);
1136}
1137
1138static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1139 int page)
1140{
1141 read_oob_data(mtd, chip->oob_poi, page);
1142
1143 return 0;
1144}
1145
1146static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1147 uint8_t *buf, int oob_required, int page)
1148{
1149 unsigned int max_bitflips;
1150 struct denali_nand_info *denali = mtd_to_denali(mtd);
1151
1152 dma_addr_t addr = denali->buf.dma_buf;
1153 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1154
1155 uint32_t irq_status;
1156 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1157 INTR_STATUS__ECC_ERR;
1158 bool check_erased_page = false;
1159
1160 if (page != denali->page) {
1161 dev_err(denali->dev,
1162 "IN %s: page %d is not equal to denali->page %d",
1163 __func__, page, denali->page);
1164 BUG();
1165 }
1166
1167 setup_ecc_for_xfer(denali, true, false);
1168
1169 denali_enable_dma(denali, true);
1170 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1171
1172 clear_interrupts(denali);
1173 denali_setup_dma(denali, DENALI_READ);
1174
1175
1176 irq_status = wait_for_irq(denali, irq_mask);
1177
1178 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1179
1180 memcpy(buf, denali->buf.buf, mtd->writesize);
1181
1182 check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
1183 denali_enable_dma(denali, false);
1184
1185 if (check_erased_page) {
1186 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1187
1188
1189 if (check_erased_page) {
1190 if (!is_erased(buf, denali->mtd.writesize))
1191 denali->mtd.ecc_stats.failed++;
1192 if (!is_erased(buf, denali->mtd.oobsize))
1193 denali->mtd.ecc_stats.failed++;
1194 }
1195 }
1196 return max_bitflips;
1197}
1198
1199static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1200 uint8_t *buf, int oob_required, int page)
1201{
1202 struct denali_nand_info *denali = mtd_to_denali(mtd);
1203 dma_addr_t addr = denali->buf.dma_buf;
1204 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1205 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
1206
1207 if (page != denali->page) {
1208 dev_err(denali->dev,
1209 "IN %s: page %d is not equal to denali->page %d",
1210 __func__, page, denali->page);
1211 BUG();
1212 }
1213
1214 setup_ecc_for_xfer(denali, false, true);
1215 denali_enable_dma(denali, true);
1216
1217 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1218
1219 clear_interrupts(denali);
1220 denali_setup_dma(denali, DENALI_READ);
1221
1222
1223 wait_for_irq(denali, irq_mask);
1224
1225 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1226
1227 denali_enable_dma(denali, false);
1228
1229 memcpy(buf, denali->buf.buf, mtd->writesize);
1230 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1231
1232 return 0;
1233}
1234
1235static uint8_t denali_read_byte(struct mtd_info *mtd)
1236{
1237 struct denali_nand_info *denali = mtd_to_denali(mtd);
1238 uint8_t result = 0xff;
1239
1240 if (denali->buf.head < denali->buf.tail)
1241 result = denali->buf.buf[denali->buf.head++];
1242
1243 return result;
1244}
1245
1246static void denali_select_chip(struct mtd_info *mtd, int chip)
1247{
1248 struct denali_nand_info *denali = mtd_to_denali(mtd);
1249
1250 spin_lock_irq(&denali->irq_lock);
1251 denali->flash_bank = chip;
1252 spin_unlock_irq(&denali->irq_lock);
1253}
1254
1255static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1256{
1257 struct denali_nand_info *denali = mtd_to_denali(mtd);
1258 int status = denali->status;
1259
1260 denali->status = 0;
1261
1262 return status;
1263}
1264
1265static int denali_erase(struct mtd_info *mtd, int page)
1266{
1267 struct denali_nand_info *denali = mtd_to_denali(mtd);
1268
1269 uint32_t cmd, irq_status;
1270
1271 clear_interrupts(denali);
1272
1273
1274 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1275 index_addr(denali, cmd, 0x1);
1276
1277
1278 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1279 INTR_STATUS__ERASE_FAIL);
1280
1281 return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS;
1282}
1283
1284static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1285 int page)
1286{
1287 struct denali_nand_info *denali = mtd_to_denali(mtd);
1288 uint32_t addr, id;
1289 int i;
1290
1291 switch (cmd) {
1292 case NAND_CMD_PAGEPROG:
1293 break;
1294 case NAND_CMD_STATUS:
1295 read_status(denali);
1296 break;
1297 case NAND_CMD_READID:
1298 case NAND_CMD_PARAM:
1299 reset_buf(denali);
1300
1301
1302
1303
1304
1305 addr = MODE_11 | BANK(denali->flash_bank);
1306 index_addr(denali, addr | 0, 0x90);
1307 index_addr(denali, addr | 1, 0);
1308 for (i = 0; i < 8; i++) {
1309 index_addr_read_data(denali, addr | 2, &id);
1310 write_byte_to_buf(denali, id);
1311 }
1312 break;
1313 case NAND_CMD_READ0:
1314 case NAND_CMD_SEQIN:
1315 denali->page = page;
1316 break;
1317 case NAND_CMD_RESET:
1318 reset_bank(denali);
1319 break;
1320 case NAND_CMD_READOOB:
1321
1322 break;
1323 default:
1324 pr_err(": unsupported command received 0x%x\n", cmd);
1325 break;
1326 }
1327}
1328
1329
1330
1331static void denali_hw_init(struct denali_nand_info *denali)
1332{
1333
1334
1335
1336
1337
1338
1339 denali->bbtskipbytes = ioread32(denali->flash_reg +
1340 SPARE_AREA_SKIP_BYTES);
1341 detect_max_banks(denali);
1342 denali_nand_reset(denali);
1343 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1344 iowrite32(CHIP_EN_DONT_CARE__FLAG,
1345 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1346
1347 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1348
1349
1350 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1351 iowrite32(1, denali->flash_reg + ECC_ENABLE);
1352 denali_nand_timing_set(denali);
1353 denali_irq_init(denali);
1354}
1355
1356
1357
1358
1359
1360
1361#define ECC_8BITS 14
1362static struct nand_ecclayout nand_8bit_oob = {
1363 .eccbytes = 14,
1364};
1365
1366#define ECC_15BITS 26
1367static struct nand_ecclayout nand_15bit_oob = {
1368 .eccbytes = 26,
1369};
1370
1371static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1372static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1373
1374static struct nand_bbt_descr bbt_main_descr = {
1375 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1376 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1377 .offs = 8,
1378 .len = 4,
1379 .veroffs = 12,
1380 .maxblocks = 4,
1381 .pattern = bbt_pattern,
1382};
1383
1384static struct nand_bbt_descr bbt_mirror_descr = {
1385 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1386 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1387 .offs = 8,
1388 .len = 4,
1389 .veroffs = 12,
1390 .maxblocks = 4,
1391 .pattern = mirror_pattern,
1392};
1393
1394
1395static void denali_drv_init(struct denali_nand_info *denali)
1396{
1397 denali->idx = 0;
1398
1399
1400
1401
1402
1403
1404 init_completion(&denali->complete);
1405
1406
1407
1408
1409
1410 spin_lock_init(&denali->irq_lock);
1411
1412
1413 denali->flash_bank = CHIP_SELECT_INVALID;
1414
1415
1416 denali->irq_status = 0;
1417}
1418
1419int denali_init(struct denali_nand_info *denali)
1420{
1421 int ret;
1422
1423 if (denali->platform == INTEL_CE4100) {
1424
1425
1426
1427
1428 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1429 pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
1430 return -EINVAL;
1431 }
1432 }
1433
1434
1435 denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
1436 GFP_DMA | GFP_KERNEL);
1437 if (!denali->buf.buf)
1438 return -ENOMEM;
1439
1440 denali->mtd.dev.parent = denali->dev;
1441 denali_hw_init(denali);
1442 denali_drv_init(denali);
1443
1444
1445
1446
1447
1448 if (request_irq(denali->irq, denali_isr, IRQF_SHARED,
1449 DENALI_NAND_NAME, denali)) {
1450 pr_err("Spectra: Unable to allocate IRQ\n");
1451 return -ENODEV;
1452 }
1453
1454
1455 denali_set_intr_modes(denali, true);
1456 denali->mtd.name = "denali-nand";
1457 denali->mtd.owner = THIS_MODULE;
1458 denali->mtd.priv = &denali->nand;
1459
1460
1461 denali->nand.select_chip = denali_select_chip;
1462 denali->nand.cmdfunc = denali_cmdfunc;
1463 denali->nand.read_byte = denali_read_byte;
1464 denali->nand.waitfunc = denali_waitfunc;
1465
1466
1467
1468
1469
1470
1471 if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
1472 ret = -ENXIO;
1473 goto failed_req_irq;
1474 }
1475
1476
1477 devm_kfree(denali->dev, denali->buf.buf);
1478 denali->buf.buf = devm_kzalloc(denali->dev,
1479 denali->mtd.writesize + denali->mtd.oobsize,
1480 GFP_KERNEL);
1481 if (!denali->buf.buf) {
1482 ret = -ENOMEM;
1483 goto failed_req_irq;
1484 }
1485
1486
1487 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
1488 if (ret) {
1489 pr_err("Spectra: no usable DMA configuration\n");
1490 goto failed_req_irq;
1491 }
1492
1493 denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
1494 denali->mtd.writesize + denali->mtd.oobsize,
1495 DMA_BIDIRECTIONAL);
1496 if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
1497 dev_err(denali->dev, "Spectra: failed to map DMA buffer\n");
1498 ret = -EIO;
1499 goto failed_req_irq;
1500 }
1501
1502
1503
1504
1505
1506
1507 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1508 denali->nand.chipsize <<= (denali->devnum - 1);
1509 denali->nand.page_shift += (denali->devnum - 1);
1510 denali->nand.pagemask = (denali->nand.chipsize >>
1511 denali->nand.page_shift) - 1;
1512 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1513 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1514 denali->nand.chip_shift += (denali->devnum - 1);
1515 denali->mtd.writesize <<= (denali->devnum - 1);
1516 denali->mtd.oobsize <<= (denali->devnum - 1);
1517 denali->mtd.erasesize <<= (denali->devnum - 1);
1518 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
1519 denali->bbtskipbytes *= denali->devnum;
1520
1521
1522
1523
1524
1525
1526
1527
1528 denali->nand.bbt_td = &bbt_main_descr;
1529 denali->nand.bbt_md = &bbt_mirror_descr;
1530
1531
1532 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
1533 denali->nand.options |= NAND_SKIP_BBTSCAN;
1534 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1535
1536
1537 denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
1538
1539
1540
1541
1542
1543
1544 if (!nand_is_slc(&denali->nand) &&
1545 (denali->mtd.oobsize > (denali->bbtskipbytes +
1546 ECC_15BITS * (denali->mtd.writesize /
1547 ECC_SECTOR_SIZE)))) {
1548
1549 denali->nand.ecc.strength = 15;
1550 denali->nand.ecc.layout = &nand_15bit_oob;
1551 denali->nand.ecc.bytes = ECC_15BITS;
1552 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
1553 } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
1554 ECC_8BITS * (denali->mtd.writesize /
1555 ECC_SECTOR_SIZE))) {
1556 pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
1557 goto failed_req_irq;
1558 } else {
1559 denali->nand.ecc.strength = 8;
1560 denali->nand.ecc.layout = &nand_8bit_oob;
1561 denali->nand.ecc.bytes = ECC_8BITS;
1562 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
1563 }
1564
1565 denali->nand.ecc.bytes *= denali->devnum;
1566 denali->nand.ecc.strength *= denali->devnum;
1567 denali->nand.ecc.layout->eccbytes *=
1568 denali->mtd.writesize / ECC_SECTOR_SIZE;
1569 denali->nand.ecc.layout->oobfree[0].offset =
1570 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
1571 denali->nand.ecc.layout->oobfree[0].length =
1572 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
1573 denali->bbtskipbytes;
1574
1575
1576
1577
1578
1579
1580 denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift;
1581 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1582
1583
1584 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
1585 denali->nand.ecc.read_page = denali_read_page;
1586 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1587 denali->nand.ecc.write_page = denali_write_page;
1588 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1589 denali->nand.ecc.read_oob = denali_read_oob;
1590 denali->nand.ecc.write_oob = denali_write_oob;
1591 denali->nand.erase = denali_erase;
1592
1593 if (nand_scan_tail(&denali->mtd)) {
1594 ret = -ENXIO;
1595 goto failed_req_irq;
1596 }
1597
1598 ret = mtd_device_register(&denali->mtd, NULL, 0);
1599 if (ret) {
1600 dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n",
1601 ret);
1602 goto failed_req_irq;
1603 }
1604 return 0;
1605
1606failed_req_irq:
1607 denali_irq_cleanup(denali->irq, denali);
1608
1609 return ret;
1610}
1611EXPORT_SYMBOL(denali_init);
1612
1613
1614void denali_remove(struct denali_nand_info *denali)
1615{
1616 denali_irq_cleanup(denali->irq, denali);
1617 dma_unmap_single(denali->dev, denali->buf.dma_buf,
1618 denali->mtd.writesize + denali->mtd.oobsize,
1619 DMA_BIDIRECTIONAL);
1620}
1621EXPORT_SYMBOL(denali_remove);
1622