linux/drivers/mtd/nand/hisi504_nand.c
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   1/*
   2 * Hisilicon NAND Flash controller driver
   3 *
   4 * Copyright © 2012-2014 HiSilicon Technologies Co., Ltd.
   5 *              http://www.hisilicon.com
   6 *
   7 * Author: Zhou Wang <wangzhou.bry@gmail.com>
   8 * The initial developer of the original code is Zhiyong Cai
   9 * <caizhiyong@huawei.com>
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or
  14 * (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 */
  21#include <linux/of.h>
  22#include <linux/of_mtd.h>
  23#include <linux/mtd/mtd.h>
  24#include <linux/sizes.h>
  25#include <linux/clk.h>
  26#include <linux/slab.h>
  27#include <linux/module.h>
  28#include <linux/delay.h>
  29#include <linux/interrupt.h>
  30#include <linux/mtd/nand.h>
  31#include <linux/dma-mapping.h>
  32#include <linux/platform_device.h>
  33#include <linux/mtd/partitions.h>
  34
  35#define HINFC504_MAX_CHIP                               (4)
  36#define HINFC504_W_LATCH                                (5)
  37#define HINFC504_R_LATCH                                (7)
  38#define HINFC504_RW_LATCH                               (3)
  39
  40#define HINFC504_NFC_TIMEOUT                            (2 * HZ)
  41#define HINFC504_NFC_PM_TIMEOUT                         (1 * HZ)
  42#define HINFC504_NFC_DMA_TIMEOUT                        (5 * HZ)
  43#define HINFC504_CHIP_DELAY                             (25)
  44
  45#define HINFC504_REG_BASE_ADDRESS_LEN                   (0x100)
  46#define HINFC504_BUFFER_BASE_ADDRESS_LEN                (2048 + 128)
  47
  48#define HINFC504_ADDR_CYCLE_MASK                        0x4
  49
  50#define HINFC504_CON                                    0x00
  51#define HINFC504_CON_OP_MODE_NORMAL                     BIT(0)
  52#define HINFC504_CON_PAGEISZE_SHIFT                     (1)
  53#define HINFC504_CON_PAGESIZE_MASK                      (0x07)
  54#define HINFC504_CON_BUS_WIDTH                          BIT(4)
  55#define HINFC504_CON_READY_BUSY_SEL                     BIT(8)
  56#define HINFC504_CON_ECCTYPE_SHIFT                      (9)
  57#define HINFC504_CON_ECCTYPE_MASK                       (0x07)
  58
  59#define HINFC504_PWIDTH                                 0x04
  60#define SET_HINFC504_PWIDTH(_w_lcnt, _r_lcnt, _rw_hcnt) \
  61        ((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8))
  62
  63#define HINFC504_CMD                                    0x0C
  64#define HINFC504_ADDRL                                  0x10
  65#define HINFC504_ADDRH                                  0x14
  66#define HINFC504_DATA_NUM                               0x18
  67
  68#define HINFC504_OP                                     0x1C
  69#define HINFC504_OP_READ_DATA_EN                        BIT(1)
  70#define HINFC504_OP_WAIT_READY_EN                       BIT(2)
  71#define HINFC504_OP_CMD2_EN                             BIT(3)
  72#define HINFC504_OP_WRITE_DATA_EN                       BIT(4)
  73#define HINFC504_OP_ADDR_EN                             BIT(5)
  74#define HINFC504_OP_CMD1_EN                             BIT(6)
  75#define HINFC504_OP_NF_CS_SHIFT                         (7)
  76#define HINFC504_OP_NF_CS_MASK                          (3)
  77#define HINFC504_OP_ADDR_CYCLE_SHIFT                    (9)
  78#define HINFC504_OP_ADDR_CYCLE_MASK                     (7)
  79
  80#define HINFC504_STATUS                                 0x20
  81#define HINFC504_READY                                  BIT(0)
  82
  83#define HINFC504_INTEN                                  0x24
  84#define HINFC504_INTEN_DMA                              BIT(9)
  85#define HINFC504_INTEN_UE                               BIT(6)
  86#define HINFC504_INTEN_CE                               BIT(5)
  87
  88#define HINFC504_INTS                                   0x28
  89#define HINFC504_INTS_DMA                               BIT(9)
  90#define HINFC504_INTS_UE                                BIT(6)
  91#define HINFC504_INTS_CE                                BIT(5)
  92
  93#define HINFC504_INTCLR                                 0x2C
  94#define HINFC504_INTCLR_DMA                             BIT(9)
  95#define HINFC504_INTCLR_UE                              BIT(6)
  96#define HINFC504_INTCLR_CE                              BIT(5)
  97
  98#define HINFC504_ECC_STATUS                             0x5C
  99#define HINFC504_ECC_16_BIT_SHIFT                       12
 100
 101#define HINFC504_DMA_CTRL                               0x60
 102#define HINFC504_DMA_CTRL_DMA_START                     BIT(0)
 103#define HINFC504_DMA_CTRL_WE                            BIT(1)
 104#define HINFC504_DMA_CTRL_DATA_AREA_EN                  BIT(2)
 105#define HINFC504_DMA_CTRL_OOB_AREA_EN                   BIT(3)
 106#define HINFC504_DMA_CTRL_BURST4_EN                     BIT(4)
 107#define HINFC504_DMA_CTRL_BURST8_EN                     BIT(5)
 108#define HINFC504_DMA_CTRL_BURST16_EN                    BIT(6)
 109#define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT                (7)
 110#define HINFC504_DMA_CTRL_ADDR_NUM_MASK                 (1)
 111#define HINFC504_DMA_CTRL_CS_SHIFT                      (8)
 112#define HINFC504_DMA_CTRL_CS_MASK                       (0x03)
 113
 114#define HINFC504_DMA_ADDR_DATA                          0x64
 115#define HINFC504_DMA_ADDR_OOB                           0x68
 116
 117#define HINFC504_DMA_LEN                                0x6C
 118#define HINFC504_DMA_LEN_OOB_SHIFT                      (16)
 119#define HINFC504_DMA_LEN_OOB_MASK                       (0xFFF)
 120
 121#define HINFC504_DMA_PARA                               0x70
 122#define HINFC504_DMA_PARA_DATA_RW_EN                    BIT(0)
 123#define HINFC504_DMA_PARA_OOB_RW_EN                     BIT(1)
 124#define HINFC504_DMA_PARA_DATA_EDC_EN                   BIT(2)
 125#define HINFC504_DMA_PARA_OOB_EDC_EN                    BIT(3)
 126#define HINFC504_DMA_PARA_DATA_ECC_EN                   BIT(4)
 127#define HINFC504_DMA_PARA_OOB_ECC_EN                    BIT(5)
 128
 129#define HINFC_VERSION                                   0x74
 130#define HINFC504_LOG_READ_ADDR                          0x7C
 131#define HINFC504_LOG_READ_LEN                           0x80
 132
 133#define HINFC504_NANDINFO_LEN                           0x10
 134
 135struct hinfc_host {
 136        struct nand_chip        chip;
 137        struct mtd_info         mtd;
 138        struct device           *dev;
 139        void __iomem            *iobase;
 140        void __iomem            *mmio;
 141        struct completion       cmd_complete;
 142        unsigned int            offset;
 143        unsigned int            command;
 144        int                     chipselect;
 145        unsigned int            addr_cycle;
 146        u32                     addr_value[2];
 147        u32                     cache_addr_value[2];
 148        char                    *buffer;
 149        dma_addr_t              dma_buffer;
 150        dma_addr_t              dma_oob;
 151        int                     version;
 152        unsigned int            irq_status; /* interrupt status */
 153};
 154
 155static inline unsigned int hinfc_read(struct hinfc_host *host, unsigned int reg)
 156{
 157        return readl(host->iobase + reg);
 158}
 159
 160static inline void hinfc_write(struct hinfc_host *host, unsigned int value,
 161                               unsigned int reg)
 162{
 163        writel(value, host->iobase + reg);
 164}
 165
 166static void wait_controller_finished(struct hinfc_host *host)
 167{
 168        unsigned long timeout = jiffies + HINFC504_NFC_TIMEOUT;
 169        int val;
 170
 171        while (time_before(jiffies, timeout)) {
 172                val = hinfc_read(host, HINFC504_STATUS);
 173                if (host->command == NAND_CMD_ERASE2) {
 174                        /* nfc is ready */
 175                        while (!(val & HINFC504_READY)) {
 176                                usleep_range(500, 1000);
 177                                val = hinfc_read(host, HINFC504_STATUS);
 178                        }
 179                        return;
 180                }
 181
 182                if (val & HINFC504_READY)
 183                        return;
 184        }
 185
 186        /* wait cmd timeout */
 187        dev_err(host->dev, "Wait NAND controller exec cmd timeout.\n");
 188}
 189
 190static void hisi_nfc_dma_transfer(struct hinfc_host *host, int todev)
 191{
 192        struct mtd_info *mtd = &host->mtd;
 193        struct nand_chip *chip = mtd->priv;
 194        unsigned long val;
 195        int ret;
 196
 197        hinfc_write(host, host->dma_buffer, HINFC504_DMA_ADDR_DATA);
 198        hinfc_write(host, host->dma_oob, HINFC504_DMA_ADDR_OOB);
 199
 200        if (chip->ecc.mode == NAND_ECC_NONE) {
 201                hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK)
 202                        << HINFC504_DMA_LEN_OOB_SHIFT), HINFC504_DMA_LEN);
 203
 204                hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
 205                        | HINFC504_DMA_PARA_OOB_RW_EN, HINFC504_DMA_PARA);
 206        } else {
 207                if (host->command == NAND_CMD_READOOB)
 208                        hinfc_write(host, HINFC504_DMA_PARA_OOB_RW_EN
 209                        | HINFC504_DMA_PARA_OOB_EDC_EN
 210                        | HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
 211                else
 212                        hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
 213                        | HINFC504_DMA_PARA_OOB_RW_EN
 214                        | HINFC504_DMA_PARA_DATA_EDC_EN
 215                        | HINFC504_DMA_PARA_OOB_EDC_EN
 216                        | HINFC504_DMA_PARA_DATA_ECC_EN
 217                        | HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
 218
 219        }
 220
 221        val = (HINFC504_DMA_CTRL_DMA_START | HINFC504_DMA_CTRL_BURST4_EN
 222                | HINFC504_DMA_CTRL_BURST8_EN | HINFC504_DMA_CTRL_BURST16_EN
 223                | HINFC504_DMA_CTRL_DATA_AREA_EN | HINFC504_DMA_CTRL_OOB_AREA_EN
 224                | ((host->addr_cycle == 4 ? 1 : 0)
 225                        << HINFC504_DMA_CTRL_ADDR_NUM_SHIFT)
 226                | ((host->chipselect & HINFC504_DMA_CTRL_CS_MASK)
 227                        << HINFC504_DMA_CTRL_CS_SHIFT));
 228
 229        if (todev)
 230                val |= HINFC504_DMA_CTRL_WE;
 231
 232        init_completion(&host->cmd_complete);
 233
 234        hinfc_write(host, val, HINFC504_DMA_CTRL);
 235        ret = wait_for_completion_timeout(&host->cmd_complete,
 236                        HINFC504_NFC_DMA_TIMEOUT);
 237
 238        if (!ret) {
 239                dev_err(host->dev, "DMA operation(irq) timeout!\n");
 240                /* sanity check */
 241                val = hinfc_read(host, HINFC504_DMA_CTRL);
 242                if (!(val & HINFC504_DMA_CTRL_DMA_START))
 243                        dev_err(host->dev, "DMA is already done but without irq ACK!\n");
 244                else
 245                        dev_err(host->dev, "DMA is really timeout!\n");
 246        }
 247}
 248
 249static int hisi_nfc_send_cmd_pageprog(struct hinfc_host *host)
 250{
 251        host->addr_value[0] &= 0xffff0000;
 252
 253        hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
 254        hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
 255        hinfc_write(host, NAND_CMD_PAGEPROG << 8 | NAND_CMD_SEQIN,
 256                    HINFC504_CMD);
 257
 258        hisi_nfc_dma_transfer(host, 1);
 259
 260        return 0;
 261}
 262
 263static int hisi_nfc_send_cmd_readstart(struct hinfc_host *host)
 264{
 265        struct mtd_info *mtd = &host->mtd;
 266
 267        if ((host->addr_value[0] == host->cache_addr_value[0]) &&
 268            (host->addr_value[1] == host->cache_addr_value[1]))
 269                return 0;
 270
 271        host->addr_value[0] &= 0xffff0000;
 272
 273        hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
 274        hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
 275        hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
 276                    HINFC504_CMD);
 277
 278        hinfc_write(host, 0, HINFC504_LOG_READ_ADDR);
 279        hinfc_write(host, mtd->writesize + mtd->oobsize,
 280                    HINFC504_LOG_READ_LEN);
 281
 282        hisi_nfc_dma_transfer(host, 0);
 283
 284        host->cache_addr_value[0] = host->addr_value[0];
 285        host->cache_addr_value[1] = host->addr_value[1];
 286
 287        return 0;
 288}
 289
 290static int hisi_nfc_send_cmd_erase(struct hinfc_host *host)
 291{
 292        hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
 293        hinfc_write(host, (NAND_CMD_ERASE2 << 8) | NAND_CMD_ERASE1,
 294                    HINFC504_CMD);
 295
 296        hinfc_write(host, HINFC504_OP_WAIT_READY_EN
 297                | HINFC504_OP_CMD2_EN
 298                | HINFC504_OP_CMD1_EN
 299                | HINFC504_OP_ADDR_EN
 300                | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
 301                        << HINFC504_OP_NF_CS_SHIFT)
 302                | ((host->addr_cycle & HINFC504_OP_ADDR_CYCLE_MASK)
 303                        << HINFC504_OP_ADDR_CYCLE_SHIFT),
 304                HINFC504_OP);
 305
 306        wait_controller_finished(host);
 307
 308        return 0;
 309}
 310
 311static int hisi_nfc_send_cmd_readid(struct hinfc_host *host)
 312{
 313        hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
 314        hinfc_write(host, NAND_CMD_READID, HINFC504_CMD);
 315        hinfc_write(host, 0, HINFC504_ADDRL);
 316
 317        hinfc_write(host, HINFC504_OP_CMD1_EN | HINFC504_OP_ADDR_EN
 318                | HINFC504_OP_READ_DATA_EN
 319                | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
 320                        << HINFC504_OP_NF_CS_SHIFT)
 321                | 1 << HINFC504_OP_ADDR_CYCLE_SHIFT, HINFC504_OP);
 322
 323        wait_controller_finished(host);
 324
 325        return 0;
 326}
 327
 328static int hisi_nfc_send_cmd_status(struct hinfc_host *host)
 329{
 330        hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
 331        hinfc_write(host, NAND_CMD_STATUS, HINFC504_CMD);
 332        hinfc_write(host, HINFC504_OP_CMD1_EN
 333                | HINFC504_OP_READ_DATA_EN
 334                | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
 335                        << HINFC504_OP_NF_CS_SHIFT),
 336                HINFC504_OP);
 337
 338        wait_controller_finished(host);
 339
 340        return 0;
 341}
 342
 343static int hisi_nfc_send_cmd_reset(struct hinfc_host *host, int chipselect)
 344{
 345        hinfc_write(host, NAND_CMD_RESET, HINFC504_CMD);
 346
 347        hinfc_write(host, HINFC504_OP_CMD1_EN
 348                | ((chipselect & HINFC504_OP_NF_CS_MASK)
 349                        << HINFC504_OP_NF_CS_SHIFT)
 350                | HINFC504_OP_WAIT_READY_EN,
 351                HINFC504_OP);
 352
 353        wait_controller_finished(host);
 354
 355        return 0;
 356}
 357
 358static void hisi_nfc_select_chip(struct mtd_info *mtd, int chipselect)
 359{
 360        struct nand_chip *chip = mtd->priv;
 361        struct hinfc_host *host = chip->priv;
 362
 363        if (chipselect < 0)
 364                return;
 365
 366        host->chipselect = chipselect;
 367}
 368
 369static uint8_t hisi_nfc_read_byte(struct mtd_info *mtd)
 370{
 371        struct nand_chip *chip = mtd->priv;
 372        struct hinfc_host *host = chip->priv;
 373
 374        if (host->command == NAND_CMD_STATUS)
 375                return *(uint8_t *)(host->mmio);
 376
 377        host->offset++;
 378
 379        if (host->command == NAND_CMD_READID)
 380                return *(uint8_t *)(host->mmio + host->offset - 1);
 381
 382        return *(uint8_t *)(host->buffer + host->offset - 1);
 383}
 384
 385static u16 hisi_nfc_read_word(struct mtd_info *mtd)
 386{
 387        struct nand_chip *chip = mtd->priv;
 388        struct hinfc_host *host = chip->priv;
 389
 390        host->offset += 2;
 391        return *(u16 *)(host->buffer + host->offset - 2);
 392}
 393
 394static void
 395hisi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 396{
 397        struct nand_chip *chip = mtd->priv;
 398        struct hinfc_host *host = chip->priv;
 399
 400        memcpy(host->buffer + host->offset, buf, len);
 401        host->offset += len;
 402}
 403
 404static void hisi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 405{
 406        struct nand_chip *chip = mtd->priv;
 407        struct hinfc_host *host = chip->priv;
 408
 409        memcpy(buf, host->buffer + host->offset, len);
 410        host->offset += len;
 411}
 412
 413static void set_addr(struct mtd_info *mtd, int column, int page_addr)
 414{
 415        struct nand_chip *chip = mtd->priv;
 416        struct hinfc_host *host = chip->priv;
 417        unsigned int command = host->command;
 418
 419        host->addr_cycle    = 0;
 420        host->addr_value[0] = 0;
 421        host->addr_value[1] = 0;
 422
 423        /* Serially input address */
 424        if (column != -1) {
 425                /* Adjust columns for 16 bit buswidth */
 426                if (chip->options & NAND_BUSWIDTH_16 &&
 427                                !nand_opcode_8bits(command))
 428                        column >>= 1;
 429
 430                host->addr_value[0] = column & 0xffff;
 431                host->addr_cycle    = 2;
 432        }
 433        if (page_addr != -1) {
 434                host->addr_value[0] |= (page_addr & 0xffff)
 435                        << (host->addr_cycle * 8);
 436                host->addr_cycle    += 2;
 437                /* One more address cycle for devices > 128MiB */
 438                if (chip->chipsize > (128 << 20)) {
 439                        host->addr_cycle += 1;
 440                        if (host->command == NAND_CMD_ERASE1)
 441                                host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16;
 442                        else
 443                                host->addr_value[1] |= ((page_addr >> 16) & 0xff);
 444                }
 445        }
 446}
 447
 448static void hisi_nfc_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
 449                int page_addr)
 450{
 451        struct nand_chip *chip = mtd->priv;
 452        struct hinfc_host *host = chip->priv;
 453        int is_cache_invalid = 1;
 454        unsigned int flag = 0;
 455
 456        host->command =  command;
 457
 458        switch (command) {
 459        case NAND_CMD_READ0:
 460        case NAND_CMD_READOOB:
 461                if (command == NAND_CMD_READ0)
 462                        host->offset = column;
 463                else
 464                        host->offset = column + mtd->writesize;
 465
 466                is_cache_invalid = 0;
 467                set_addr(mtd, column, page_addr);
 468                hisi_nfc_send_cmd_readstart(host);
 469                break;
 470
 471        case NAND_CMD_SEQIN:
 472                host->offset = column;
 473                set_addr(mtd, column, page_addr);
 474                break;
 475
 476        case NAND_CMD_ERASE1:
 477                set_addr(mtd, column, page_addr);
 478                break;
 479
 480        case NAND_CMD_PAGEPROG:
 481                hisi_nfc_send_cmd_pageprog(host);
 482                break;
 483
 484        case NAND_CMD_ERASE2:
 485                hisi_nfc_send_cmd_erase(host);
 486                break;
 487
 488        case NAND_CMD_READID:
 489                host->offset = column;
 490                memset(host->mmio, 0, 0x10);
 491                hisi_nfc_send_cmd_readid(host);
 492                break;
 493
 494        case NAND_CMD_STATUS:
 495                flag = hinfc_read(host, HINFC504_CON);
 496                if (chip->ecc.mode == NAND_ECC_HW)
 497                        hinfc_write(host,
 498                                    flag & ~(HINFC504_CON_ECCTYPE_MASK <<
 499                                    HINFC504_CON_ECCTYPE_SHIFT), HINFC504_CON);
 500
 501                host->offset = 0;
 502                memset(host->mmio, 0, 0x10);
 503                hisi_nfc_send_cmd_status(host);
 504                hinfc_write(host, flag, HINFC504_CON);
 505                break;
 506
 507        case NAND_CMD_RESET:
 508                hisi_nfc_send_cmd_reset(host, host->chipselect);
 509                break;
 510
 511        default:
 512                dev_err(host->dev, "Error: unsupported cmd(cmd=%x, col=%x, page=%x)\n",
 513                        command, column, page_addr);
 514        }
 515
 516        if (is_cache_invalid) {
 517                host->cache_addr_value[0] = ~0;
 518                host->cache_addr_value[1] = ~0;
 519        }
 520}
 521
 522static irqreturn_t hinfc_irq_handle(int irq, void *devid)
 523{
 524        struct hinfc_host *host = devid;
 525        unsigned int flag;
 526
 527        flag = hinfc_read(host, HINFC504_INTS);
 528        /* store interrupts state */
 529        host->irq_status |= flag;
 530
 531        if (flag & HINFC504_INTS_DMA) {
 532                hinfc_write(host, HINFC504_INTCLR_DMA, HINFC504_INTCLR);
 533                complete(&host->cmd_complete);
 534        } else if (flag & HINFC504_INTS_CE) {
 535                hinfc_write(host, HINFC504_INTCLR_CE, HINFC504_INTCLR);
 536        } else if (flag & HINFC504_INTS_UE) {
 537                hinfc_write(host, HINFC504_INTCLR_UE, HINFC504_INTCLR);
 538        }
 539
 540        return IRQ_HANDLED;
 541}
 542
 543static int hisi_nand_read_page_hwecc(struct mtd_info *mtd,
 544        struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 545{
 546        struct hinfc_host *host = chip->priv;
 547        int max_bitflips = 0, stat = 0, stat_max = 0, status_ecc;
 548        int stat_1, stat_2;
 549
 550        chip->read_buf(mtd, buf, mtd->writesize);
 551        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 552
 553        /* errors which can not be corrected by ECC */
 554        if (host->irq_status & HINFC504_INTS_UE) {
 555                mtd->ecc_stats.failed++;
 556        } else if (host->irq_status & HINFC504_INTS_CE) {
 557                /* TODO: need add other ECC modes! */
 558                switch (chip->ecc.strength) {
 559                case 16:
 560                        status_ecc = hinfc_read(host, HINFC504_ECC_STATUS) >>
 561                                        HINFC504_ECC_16_BIT_SHIFT & 0x0fff;
 562                        stat_2 = status_ecc & 0x3f;
 563                        stat_1 = status_ecc >> 6 & 0x3f;
 564                        stat = stat_1 + stat_2;
 565                        stat_max = max_t(int, stat_1, stat_2);
 566                }
 567                mtd->ecc_stats.corrected += stat;
 568                max_bitflips = max_t(int, max_bitflips, stat_max);
 569        }
 570        host->irq_status = 0;
 571
 572        return max_bitflips;
 573}
 574
 575static int hisi_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 576                                int page)
 577{
 578        struct hinfc_host *host = chip->priv;
 579
 580        chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 581        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 582
 583        if (host->irq_status & HINFC504_INTS_UE) {
 584                host->irq_status = 0;
 585                return -EBADMSG;
 586        }
 587
 588        host->irq_status = 0;
 589        return 0;
 590}
 591
 592static int hisi_nand_write_page_hwecc(struct mtd_info *mtd,
 593                struct nand_chip *chip, const uint8_t *buf, int oob_required)
 594{
 595        chip->write_buf(mtd, buf, mtd->writesize);
 596        if (oob_required)
 597                chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 598
 599        return 0;
 600}
 601
 602static void hisi_nfc_host_init(struct hinfc_host *host)
 603{
 604        struct nand_chip *chip = &host->chip;
 605        unsigned int flag = 0;
 606
 607        host->version = hinfc_read(host, HINFC_VERSION);
 608        host->addr_cycle                = 0;
 609        host->addr_value[0]             = 0;
 610        host->addr_value[1]             = 0;
 611        host->cache_addr_value[0]       = ~0;
 612        host->cache_addr_value[1]       = ~0;
 613        host->chipselect                = 0;
 614
 615        /* default page size: 2K, ecc_none. need modify */
 616        flag = HINFC504_CON_OP_MODE_NORMAL | HINFC504_CON_READY_BUSY_SEL
 617                | ((0x001 & HINFC504_CON_PAGESIZE_MASK)
 618                        << HINFC504_CON_PAGEISZE_SHIFT)
 619                | ((0x0 & HINFC504_CON_ECCTYPE_MASK)
 620                        << HINFC504_CON_ECCTYPE_SHIFT)
 621                | ((chip->options & NAND_BUSWIDTH_16) ?
 622                        HINFC504_CON_BUS_WIDTH : 0);
 623        hinfc_write(host, flag, HINFC504_CON);
 624
 625        memset(host->mmio, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN);
 626
 627        hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
 628                    HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
 629
 630        /* enable DMA irq */
 631        hinfc_write(host, HINFC504_INTEN_DMA, HINFC504_INTEN);
 632}
 633
 634static struct nand_ecclayout nand_ecc_2K_16bits = {
 635        .oobavail = 6,
 636        .oobfree = { {2, 6} },
 637};
 638
 639static int hisi_nfc_ecc_probe(struct hinfc_host *host)
 640{
 641        unsigned int flag;
 642        int size, strength, ecc_bits;
 643        struct device *dev = host->dev;
 644        struct nand_chip *chip = &host->chip;
 645        struct mtd_info *mtd = &host->mtd;
 646        struct device_node *np = host->dev->of_node;
 647
 648        size = of_get_nand_ecc_step_size(np);
 649        strength = of_get_nand_ecc_strength(np);
 650        if (size != 1024) {
 651                dev_err(dev, "error ecc size: %d\n", size);
 652                return -EINVAL;
 653        }
 654
 655        if ((size == 1024) && ((strength != 8) && (strength != 16) &&
 656                                (strength != 24) && (strength != 40))) {
 657                dev_err(dev, "ecc size and strength do not match\n");
 658                return -EINVAL;
 659        }
 660
 661        chip->ecc.size = size;
 662        chip->ecc.strength = strength;
 663
 664        chip->ecc.read_page = hisi_nand_read_page_hwecc;
 665        chip->ecc.read_oob = hisi_nand_read_oob;
 666        chip->ecc.write_page = hisi_nand_write_page_hwecc;
 667
 668        switch (chip->ecc.strength) {
 669        case 16:
 670                ecc_bits = 6;
 671                if (mtd->writesize == 2048)
 672                        chip->ecc.layout = &nand_ecc_2K_16bits;
 673
 674                /* TODO: add more page size support */
 675                break;
 676
 677        /* TODO: add more ecc strength support */
 678        default:
 679                dev_err(dev, "not support strength: %d\n", chip->ecc.strength);
 680                return -EINVAL;
 681        }
 682
 683        flag = hinfc_read(host, HINFC504_CON);
 684        /* add ecc type configure */
 685        flag |= ((ecc_bits & HINFC504_CON_ECCTYPE_MASK)
 686                                                << HINFC504_CON_ECCTYPE_SHIFT);
 687        hinfc_write(host, flag, HINFC504_CON);
 688
 689        /* enable ecc irq */
 690        flag = hinfc_read(host, HINFC504_INTEN) & 0xfff;
 691        hinfc_write(host, flag | HINFC504_INTEN_UE | HINFC504_INTEN_CE,
 692                    HINFC504_INTEN);
 693
 694        return 0;
 695}
 696
 697static int hisi_nfc_probe(struct platform_device *pdev)
 698{
 699        int ret = 0, irq, buswidth, flag, max_chips = HINFC504_MAX_CHIP;
 700        struct device *dev = &pdev->dev;
 701        struct hinfc_host *host;
 702        struct nand_chip  *chip;
 703        struct mtd_info   *mtd;
 704        struct resource   *res;
 705        struct device_node *np = dev->of_node;
 706        struct mtd_part_parser_data ppdata;
 707
 708        host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
 709        if (!host)
 710                return -ENOMEM;
 711        host->dev = dev;
 712
 713        platform_set_drvdata(pdev, host);
 714        chip = &host->chip;
 715        mtd  = &host->mtd;
 716
 717        irq = platform_get_irq(pdev, 0);
 718        if (irq < 0) {
 719                dev_err(dev, "no IRQ resource defined\n");
 720                ret = -ENXIO;
 721                goto err_res;
 722        }
 723
 724        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 725        host->iobase = devm_ioremap_resource(dev, res);
 726        if (IS_ERR(host->iobase)) {
 727                ret = PTR_ERR(host->iobase);
 728                goto err_res;
 729        }
 730
 731        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 732        host->mmio = devm_ioremap_resource(dev, res);
 733        if (IS_ERR(host->mmio)) {
 734                ret = PTR_ERR(host->mmio);
 735                dev_err(dev, "devm_ioremap_resource[1] fail\n");
 736                goto err_res;
 737        }
 738
 739        mtd->priv               = chip;
 740        mtd->owner              = THIS_MODULE;
 741        mtd->name               = "hisi_nand";
 742        mtd->dev.parent         = &pdev->dev;
 743
 744        chip->priv              = host;
 745        chip->cmdfunc           = hisi_nfc_cmdfunc;
 746        chip->select_chip       = hisi_nfc_select_chip;
 747        chip->read_byte         = hisi_nfc_read_byte;
 748        chip->read_word         = hisi_nfc_read_word;
 749        chip->write_buf         = hisi_nfc_write_buf;
 750        chip->read_buf          = hisi_nfc_read_buf;
 751        chip->chip_delay        = HINFC504_CHIP_DELAY;
 752
 753        chip->ecc.mode = of_get_nand_ecc_mode(np);
 754
 755        buswidth = of_get_nand_bus_width(np);
 756        if (buswidth == 16)
 757                chip->options |= NAND_BUSWIDTH_16;
 758
 759        hisi_nfc_host_init(host);
 760
 761        ret = devm_request_irq(dev, irq, hinfc_irq_handle, 0x0, "nandc", host);
 762        if (ret) {
 763                dev_err(dev, "failed to request IRQ\n");
 764                goto err_res;
 765        }
 766
 767        ret = nand_scan_ident(mtd, max_chips, NULL);
 768        if (ret) {
 769                ret = -ENODEV;
 770                goto err_res;
 771        }
 772
 773        host->buffer = dmam_alloc_coherent(dev, mtd->writesize + mtd->oobsize,
 774                &host->dma_buffer, GFP_KERNEL);
 775        if (!host->buffer) {
 776                ret = -ENOMEM;
 777                goto err_res;
 778        }
 779
 780        host->dma_oob = host->dma_buffer + mtd->writesize;
 781        memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
 782
 783        flag = hinfc_read(host, HINFC504_CON);
 784        flag &= ~(HINFC504_CON_PAGESIZE_MASK << HINFC504_CON_PAGEISZE_SHIFT);
 785        switch (mtd->writesize) {
 786        case 2048:
 787                flag |= (0x001 << HINFC504_CON_PAGEISZE_SHIFT); break;
 788        /*
 789         * TODO: add more pagesize support,
 790         * default pagesize has been set in hisi_nfc_host_init
 791         */
 792        default:
 793                dev_err(dev, "NON-2KB page size nand flash\n");
 794                ret = -EINVAL;
 795                goto err_res;
 796        }
 797        hinfc_write(host, flag, HINFC504_CON);
 798
 799        if (chip->ecc.mode == NAND_ECC_HW)
 800                hisi_nfc_ecc_probe(host);
 801
 802        ret = nand_scan_tail(mtd);
 803        if (ret) {
 804                dev_err(dev, "nand_scan_tail failed: %d\n", ret);
 805                goto err_res;
 806        }
 807
 808        ppdata.of_node = np;
 809        ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
 810        if (ret) {
 811                dev_err(dev, "Err MTD partition=%d\n", ret);
 812                goto err_mtd;
 813        }
 814
 815        return 0;
 816
 817err_mtd:
 818        nand_release(mtd);
 819err_res:
 820        return ret;
 821}
 822
 823static int hisi_nfc_remove(struct platform_device *pdev)
 824{
 825        struct hinfc_host *host = platform_get_drvdata(pdev);
 826        struct mtd_info *mtd = &host->mtd;
 827
 828        nand_release(mtd);
 829
 830        return 0;
 831}
 832
 833#ifdef CONFIG_PM_SLEEP
 834static int hisi_nfc_suspend(struct device *dev)
 835{
 836        struct hinfc_host *host = dev_get_drvdata(dev);
 837        unsigned long timeout = jiffies + HINFC504_NFC_PM_TIMEOUT;
 838
 839        while (time_before(jiffies, timeout)) {
 840                if (((hinfc_read(host, HINFC504_STATUS) & 0x1) == 0x0) &&
 841                    (hinfc_read(host, HINFC504_DMA_CTRL) &
 842                     HINFC504_DMA_CTRL_DMA_START)) {
 843                        cond_resched();
 844                        return 0;
 845                }
 846        }
 847
 848        dev_err(host->dev, "nand controller suspend timeout.\n");
 849
 850        return -EAGAIN;
 851}
 852
 853static int hisi_nfc_resume(struct device *dev)
 854{
 855        int cs;
 856        struct hinfc_host *host = dev_get_drvdata(dev);
 857        struct nand_chip *chip = &host->chip;
 858
 859        for (cs = 0; cs < chip->numchips; cs++)
 860                hisi_nfc_send_cmd_reset(host, cs);
 861        hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
 862                    HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
 863
 864        return 0;
 865}
 866#endif
 867static SIMPLE_DEV_PM_OPS(hisi_nfc_pm_ops, hisi_nfc_suspend, hisi_nfc_resume);
 868
 869static const struct of_device_id nfc_id_table[] = {
 870        { .compatible = "hisilicon,504-nfc" },
 871        {}
 872};
 873MODULE_DEVICE_TABLE(of, nfc_id_table);
 874
 875static struct platform_driver hisi_nfc_driver = {
 876        .driver = {
 877                .name  = "hisi_nand",
 878                .of_match_table = nfc_id_table,
 879                .pm = &hisi_nfc_pm_ops,
 880        },
 881        .probe          = hisi_nfc_probe,
 882        .remove         = hisi_nfc_remove,
 883};
 884
 885module_platform_driver(hisi_nfc_driver);
 886
 887MODULE_LICENSE("GPL");
 888MODULE_AUTHOR("Zhou Wang");
 889MODULE_AUTHOR("Zhiyong Cai");
 890MODULE_DESCRIPTION("Hisilicon Nand Flash Controller Driver");
 891