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35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include "t4_hw.h"
39
40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
48#include <linux/vmalloc.h>
49#include <asm/io.h>
50#include "cxgb4_uld.h"
51
52#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
53
54enum {
55 MAX_NPORTS = 4,
56 SERNUM_LEN = 24,
57 EC_LEN = 16,
58 ID_LEN = 16,
59 PN_LEN = 16,
60};
61
62enum {
63 T4_REGMAP_SIZE = (160 * 1024),
64 T5_REGMAP_SIZE = (332 * 1024),
65};
66
67enum {
68 MEM_EDC0,
69 MEM_EDC1,
70 MEM_MC,
71 MEM_MC0 = MEM_MC,
72 MEM_MC1
73};
74
75enum {
76 MEMWIN0_APERTURE = 2048,
77 MEMWIN0_BASE = 0x1b800,
78 MEMWIN1_APERTURE = 32768,
79 MEMWIN1_BASE = 0x28000,
80 MEMWIN1_BASE_T5 = 0x52000,
81 MEMWIN2_APERTURE = 65536,
82 MEMWIN2_BASE = 0x30000,
83 MEMWIN2_APERTURE_T5 = 131072,
84 MEMWIN2_BASE_T5 = 0x60000,
85};
86
87enum dev_master {
88 MASTER_CANT,
89 MASTER_MAY,
90 MASTER_MUST
91};
92
93enum dev_state {
94 DEV_STATE_UNINIT,
95 DEV_STATE_INIT,
96 DEV_STATE_ERR
97};
98
99enum {
100 PAUSE_RX = 1 << 0,
101 PAUSE_TX = 1 << 1,
102 PAUSE_AUTONEG = 1 << 2
103};
104
105struct port_stats {
106 u64 tx_octets;
107 u64 tx_frames;
108 u64 tx_bcast_frames;
109 u64 tx_mcast_frames;
110 u64 tx_ucast_frames;
111 u64 tx_error_frames;
112
113 u64 tx_frames_64;
114 u64 tx_frames_65_127;
115 u64 tx_frames_128_255;
116 u64 tx_frames_256_511;
117 u64 tx_frames_512_1023;
118 u64 tx_frames_1024_1518;
119 u64 tx_frames_1519_max;
120
121 u64 tx_drop;
122 u64 tx_pause;
123 u64 tx_ppp0;
124 u64 tx_ppp1;
125 u64 tx_ppp2;
126 u64 tx_ppp3;
127 u64 tx_ppp4;
128 u64 tx_ppp5;
129 u64 tx_ppp6;
130 u64 tx_ppp7;
131
132 u64 rx_octets;
133 u64 rx_frames;
134 u64 rx_bcast_frames;
135 u64 rx_mcast_frames;
136 u64 rx_ucast_frames;
137 u64 rx_too_long;
138 u64 rx_jabber;
139 u64 rx_fcs_err;
140 u64 rx_len_err;
141 u64 rx_symbol_err;
142 u64 rx_runt;
143
144 u64 rx_frames_64;
145 u64 rx_frames_65_127;
146 u64 rx_frames_128_255;
147 u64 rx_frames_256_511;
148 u64 rx_frames_512_1023;
149 u64 rx_frames_1024_1518;
150 u64 rx_frames_1519_max;
151
152 u64 rx_pause;
153 u64 rx_ppp0;
154 u64 rx_ppp1;
155 u64 rx_ppp2;
156 u64 rx_ppp3;
157 u64 rx_ppp4;
158 u64 rx_ppp5;
159 u64 rx_ppp6;
160 u64 rx_ppp7;
161
162 u64 rx_ovflow0;
163 u64 rx_ovflow1;
164 u64 rx_ovflow2;
165 u64 rx_ovflow3;
166 u64 rx_trunc0;
167 u64 rx_trunc1;
168 u64 rx_trunc2;
169 u64 rx_trunc3;
170};
171
172struct lb_port_stats {
173 u64 octets;
174 u64 frames;
175 u64 bcast_frames;
176 u64 mcast_frames;
177 u64 ucast_frames;
178 u64 error_frames;
179
180 u64 frames_64;
181 u64 frames_65_127;
182 u64 frames_128_255;
183 u64 frames_256_511;
184 u64 frames_512_1023;
185 u64 frames_1024_1518;
186 u64 frames_1519_max;
187
188 u64 drop;
189
190 u64 ovflow0;
191 u64 ovflow1;
192 u64 ovflow2;
193 u64 ovflow3;
194 u64 trunc0;
195 u64 trunc1;
196 u64 trunc2;
197 u64 trunc3;
198};
199
200struct tp_tcp_stats {
201 u32 tcpOutRsts;
202 u64 tcpInSegs;
203 u64 tcpOutSegs;
204 u64 tcpRetransSegs;
205};
206
207struct tp_err_stats {
208 u32 macInErrs[4];
209 u32 hdrInErrs[4];
210 u32 tcpInErrs[4];
211 u32 tnlCongDrops[4];
212 u32 ofldChanDrops[4];
213 u32 tnlTxDrops[4];
214 u32 ofldVlanDrops[4];
215 u32 tcp6InErrs[4];
216 u32 ofldNoNeigh;
217 u32 ofldCongDefer;
218};
219
220struct sge_params {
221 u32 hps;
222 u32 eq_qpp;
223 u32 iq_qpp;
224};
225
226struct tp_params {
227 unsigned int ntxchan;
228 unsigned int tre;
229 unsigned int la_mask;
230 unsigned short tx_modq_map;
231
232
233 uint32_t dack_re;
234 unsigned short tx_modq[NCHAN];
235
236 u32 vlan_pri_map;
237 u32 ingress_config;
238
239
240
241
242
243
244
245
246
247
248
249
250 int vlan_shift;
251 int vnic_shift;
252 int port_shift;
253 int protocol_shift;
254};
255
256struct vpd_params {
257 unsigned int cclk;
258 u8 ec[EC_LEN + 1];
259 u8 sn[SERNUM_LEN + 1];
260 u8 id[ID_LEN + 1];
261 u8 pn[PN_LEN + 1];
262};
263
264struct pci_params {
265 unsigned char speed;
266 unsigned char width;
267};
268
269#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
270#define CHELSIO_CHIP_FPGA 0x100
271#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
272#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
273
274#define CHELSIO_T4 0x4
275#define CHELSIO_T5 0x5
276
277enum chip_type {
278 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
279 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
280 T4_FIRST_REV = T4_A1,
281 T4_LAST_REV = T4_A2,
282
283 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
284 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
285 T5_FIRST_REV = T5_A0,
286 T5_LAST_REV = T5_A1,
287};
288
289struct devlog_params {
290 u32 memtype;
291 u32 start;
292 u32 size;
293};
294
295struct adapter_params {
296 struct sge_params sge;
297 struct tp_params tp;
298 struct vpd_params vpd;
299 struct pci_params pci;
300 struct devlog_params devlog;
301 enum pcie_memwin drv_memwin;
302
303 unsigned int cim_la_size;
304
305 unsigned int sf_size;
306 unsigned int sf_nsec;
307 unsigned int sf_fw_start;
308
309 unsigned int fw_vers;
310 unsigned int tp_vers;
311 u8 api_vers[7];
312
313 unsigned short mtus[NMTUS];
314 unsigned short a_wnd[NCCTRL_WIN];
315 unsigned short b_wnd[NCCTRL_WIN];
316
317 unsigned char nports;
318 unsigned char portvec;
319 enum chip_type chip;
320 unsigned char offload;
321
322 unsigned char bypass;
323
324 unsigned int ofldq_wr_cred;
325 bool ulptx_memwrite_dsgl;
326
327 unsigned int max_ordird_qp;
328 unsigned int max_ird_adapter;
329};
330
331#include "t4fw_api.h"
332
333#define FW_VERSION(chip) ( \
334 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
335 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
336 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
337 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
338#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
339
340struct fw_info {
341 u8 chip;
342 char *fs_name;
343 char *fw_mod_name;
344 struct fw_hdr fw_hdr;
345};
346
347
348struct trace_params {
349 u32 data[TRACE_LEN / 4];
350 u32 mask[TRACE_LEN / 4];
351 unsigned short snap_len;
352 unsigned short min_len;
353 unsigned char skip_ofst;
354 unsigned char skip_len;
355 unsigned char invert;
356 unsigned char port;
357};
358
359struct link_config {
360 unsigned short supported;
361 unsigned short advertising;
362 unsigned short requested_speed;
363 unsigned short speed;
364 unsigned char requested_fc;
365 unsigned char fc;
366 unsigned char autoneg;
367 unsigned char link_ok;
368};
369
370#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
371
372enum {
373 MAX_ETH_QSETS = 32,
374 MAX_OFLD_QSETS = 16,
375 MAX_CTRL_QUEUES = NCHAN,
376 MAX_RDMA_QUEUES = NCHAN,
377 MAX_RDMA_CIQS = 32,
378 MAX_ISCSI_QUEUES = NCHAN,
379};
380
381enum {
382 MAX_TXQ_ENTRIES = 16384,
383 MAX_CTRL_TXQ_ENTRIES = 1024,
384 MAX_RSPQ_ENTRIES = 16384,
385 MAX_RX_BUFFERS = 16384,
386 MIN_TXQ_ENTRIES = 32,
387 MIN_CTRL_TXQ_ENTRIES = 32,
388 MIN_RSPQ_ENTRIES = 128,
389 MIN_FL_ENTRIES = 16
390};
391
392enum {
393 INGQ_EXTRAS = 2,
394
395 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES
396 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS,
397};
398
399struct adapter;
400struct sge_rspq;
401
402#include "cxgb4_dcb.h"
403
404#ifdef CONFIG_CHELSIO_T4_FCOE
405#include "cxgb4_fcoe.h"
406#endif
407
408struct port_info {
409 struct adapter *adapter;
410 u16 viid;
411 s16 xact_addr_filt;
412 u16 rss_size;
413 s8 mdio_addr;
414 enum fw_port_type port_type;
415 u8 mod_type;
416 u8 port_id;
417 u8 tx_chan;
418 u8 lport;
419 u8 nqsets;
420 u8 first_qset;
421 u8 rss_mode;
422 struct link_config link_cfg;
423 u16 *rss;
424#ifdef CONFIG_CHELSIO_T4_DCB
425 struct port_dcb_info dcb;
426#endif
427#ifdef CONFIG_CHELSIO_T4_FCOE
428 struct cxgb_fcoe fcoe;
429#endif
430};
431
432struct dentry;
433struct work_struct;
434
435enum {
436 FULL_INIT_DONE = (1 << 0),
437 DEV_ENABLED = (1 << 1),
438 USING_MSI = (1 << 2),
439 USING_MSIX = (1 << 3),
440 FW_OK = (1 << 4),
441 RSS_TNLALLLOOKUP = (1 << 5),
442 USING_SOFT_PARAMS = (1 << 6),
443 MASTER_PF = (1 << 7),
444 FW_OFLD_CONN = (1 << 9),
445};
446
447struct rx_sw_desc;
448
449struct sge_fl {
450 unsigned int avail;
451 unsigned int pend_cred;
452 unsigned int cidx;
453 unsigned int pidx;
454 unsigned long alloc_failed;
455 unsigned long large_alloc_failed;
456 unsigned long starving;
457
458 unsigned int cntxt_id;
459 unsigned int size;
460 struct rx_sw_desc *sdesc;
461 __be64 *desc;
462 dma_addr_t addr;
463 void __iomem *bar2_addr;
464 unsigned int bar2_qid;
465};
466
467
468struct pkt_gl {
469 struct page_frag frags[MAX_SKB_FRAGS];
470 void *va;
471 unsigned int nfrags;
472 unsigned int tot_len;
473};
474
475typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
476 const struct pkt_gl *gl);
477
478struct sge_rspq {
479 struct napi_struct napi;
480 const __be64 *cur_desc;
481 unsigned int cidx;
482 u8 gen;
483 u8 intr_params;
484 u8 next_intr_params;
485 u8 adaptive_rx;
486 u8 pktcnt_idx;
487 u8 uld;
488 u8 idx;
489 int offset;
490 u16 cntxt_id;
491 u16 abs_id;
492 __be64 *desc;
493 dma_addr_t phys_addr;
494 void __iomem *bar2_addr;
495 unsigned int bar2_qid;
496 unsigned int iqe_len;
497 unsigned int size;
498 struct adapter *adap;
499 struct net_device *netdev;
500 rspq_handler_t handler;
501#ifdef CONFIG_NET_RX_BUSY_POLL
502#define CXGB_POLL_STATE_IDLE 0
503#define CXGB_POLL_STATE_NAPI BIT(0)
504#define CXGB_POLL_STATE_POLL BIT(1)
505#define CXGB_POLL_STATE_NAPI_YIELD BIT(2)
506#define CXGB_POLL_STATE_POLL_YIELD BIT(3)
507#define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
508 CXGB_POLL_STATE_POLL_YIELD)
509#define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
510 CXGB_POLL_STATE_POLL)
511#define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
512 CXGB_POLL_STATE_POLL_YIELD)
513 unsigned int bpoll_state;
514 spinlock_t bpoll_lock;
515#endif
516
517};
518
519struct sge_eth_stats {
520 unsigned long pkts;
521 unsigned long lro_pkts;
522 unsigned long lro_merged;
523 unsigned long rx_cso;
524 unsigned long vlan_ex;
525 unsigned long rx_drops;
526};
527
528struct sge_eth_rxq {
529 struct sge_rspq rspq;
530 struct sge_fl fl;
531 struct sge_eth_stats stats;
532} ____cacheline_aligned_in_smp;
533
534struct sge_ofld_stats {
535 unsigned long pkts;
536 unsigned long imm;
537 unsigned long an;
538 unsigned long nomem;
539};
540
541struct sge_ofld_rxq {
542 struct sge_rspq rspq;
543 struct sge_fl fl;
544 struct sge_ofld_stats stats;
545} ____cacheline_aligned_in_smp;
546
547struct tx_desc {
548 __be64 flit[8];
549};
550
551struct tx_sw_desc;
552
553struct sge_txq {
554 unsigned int in_use;
555 unsigned int size;
556 unsigned int cidx;
557 unsigned int pidx;
558 unsigned long stops;
559 unsigned long restarts;
560 unsigned int cntxt_id;
561 struct tx_desc *desc;
562 struct tx_sw_desc *sdesc;
563 struct sge_qstat *stat;
564 dma_addr_t phys_addr;
565 spinlock_t db_lock;
566 int db_disabled;
567 unsigned short db_pidx;
568 unsigned short db_pidx_inc;
569 void __iomem *bar2_addr;
570 unsigned int bar2_qid;
571};
572
573struct sge_eth_txq {
574 struct sge_txq q;
575 struct netdev_queue *txq;
576#ifdef CONFIG_CHELSIO_T4_DCB
577 u8 dcb_prio;
578#endif
579 unsigned long tso;
580 unsigned long tx_cso;
581 unsigned long vlan_ins;
582 unsigned long mapping_err;
583} ____cacheline_aligned_in_smp;
584
585struct sge_ofld_txq {
586 struct sge_txq q;
587 struct adapter *adap;
588 struct sk_buff_head sendq;
589 struct tasklet_struct qresume_tsk;
590 u8 full;
591 unsigned long mapping_err;
592} ____cacheline_aligned_in_smp;
593
594struct sge_ctrl_txq {
595 struct sge_txq q;
596 struct adapter *adap;
597 struct sk_buff_head sendq;
598 struct tasklet_struct qresume_tsk;
599 u8 full;
600} ____cacheline_aligned_in_smp;
601
602struct sge {
603 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
604 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
605 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
606
607 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
608 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
609 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
610 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
611 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
612
613 struct sge_rspq intrq ____cacheline_aligned_in_smp;
614 spinlock_t intrq_lock;
615
616 u16 max_ethqsets;
617 u16 ethqsets;
618 u16 ethtxq_rover;
619 u16 ofldqsets;
620 u16 rdmaqs;
621 u16 rdmaciqs;
622 u16 ofld_rxq[MAX_OFLD_QSETS];
623 u16 rdma_rxq[MAX_RDMA_QUEUES];
624 u16 rdma_ciq[MAX_RDMA_CIQS];
625 u16 timer_val[SGE_NTIMERS];
626 u8 counter_val[SGE_NCOUNTERS];
627 u32 fl_pg_order;
628 u32 stat_len;
629 u32 pktshift;
630 u32 fl_align;
631 u32 fl_starve_thres;
632
633
634 unsigned int idma_1s_thresh;
635 unsigned int idma_stalled[2];
636 unsigned int idma_state[2];
637 unsigned int idma_qid[2];
638
639 unsigned int egr_start;
640 unsigned int egr_sz;
641 unsigned int ingr_start;
642 unsigned int ingr_sz;
643 void **egr_map;
644 struct sge_rspq **ingr_map;
645 unsigned long *starving_fl;
646 unsigned long *txq_maperr;
647 struct timer_list rx_timer;
648 struct timer_list tx_timer;
649};
650
651#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
652#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
653#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
654#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
655
656struct l2t_data;
657
658#ifdef CONFIG_PCI_IOV
659
660
661
662
663
664#define NUM_OF_PF_WITH_SRIOV 4
665
666#endif
667
668struct adapter {
669 void __iomem *regs;
670 void __iomem *bar2;
671 u32 t4_bar0;
672 struct pci_dev *pdev;
673 struct device *pdev_dev;
674 unsigned int mbox;
675 unsigned int fn;
676 unsigned int flags;
677 enum chip_type chip;
678
679 int msg_enable;
680
681 struct adapter_params params;
682 struct cxgb4_virt_res vres;
683 unsigned int swintr;
684
685 unsigned int wol;
686
687 struct {
688 unsigned short vec;
689 char desc[IFNAMSIZ + 10];
690 } msix_info[MAX_INGQ + 1];
691
692 struct sge sge;
693
694 struct net_device *port[MAX_NPORTS];
695 u8 chan_map[NCHAN];
696
697 u32 filter_mode;
698 unsigned int l2t_start;
699 unsigned int l2t_end;
700 struct l2t_data *l2t;
701 unsigned int clipt_start;
702 unsigned int clipt_end;
703 struct clip_tbl *clipt;
704 void *uld_handle[CXGB4_ULD_MAX];
705 struct list_head list_node;
706 struct list_head rcu_node;
707
708 struct tid_info tids;
709 void **tid_release_head;
710 spinlock_t tid_release_lock;
711 struct workqueue_struct *workq;
712 struct work_struct tid_release_task;
713 struct work_struct db_full_task;
714 struct work_struct db_drop_task;
715 bool tid_release_task_busy;
716
717 struct dentry *debugfs_root;
718
719 spinlock_t stats_lock;
720 spinlock_t win0_lock ____cacheline_aligned_in_smp;
721};
722
723
724
725#define ETHTYPE_BITWIDTH 16
726#define FRAG_BITWIDTH 1
727#define MACIDX_BITWIDTH 9
728#define FCOE_BITWIDTH 1
729#define IPORT_BITWIDTH 3
730#define MATCHTYPE_BITWIDTH 3
731#define PROTO_BITWIDTH 8
732#define TOS_BITWIDTH 8
733#define PF_BITWIDTH 8
734#define VF_BITWIDTH 8
735#define IVLAN_BITWIDTH 16
736#define OVLAN_BITWIDTH 16
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755struct ch_filter_tuple {
756
757
758
759
760
761
762 uint32_t ethtype:ETHTYPE_BITWIDTH;
763 uint32_t frag:FRAG_BITWIDTH;
764 uint32_t ivlan_vld:1;
765 uint32_t ovlan_vld:1;
766 uint32_t pfvf_vld:1;
767 uint32_t macidx:MACIDX_BITWIDTH;
768 uint32_t fcoe:FCOE_BITWIDTH;
769 uint32_t iport:IPORT_BITWIDTH;
770 uint32_t matchtype:MATCHTYPE_BITWIDTH;
771 uint32_t proto:PROTO_BITWIDTH;
772 uint32_t tos:TOS_BITWIDTH;
773 uint32_t pf:PF_BITWIDTH;
774 uint32_t vf:VF_BITWIDTH;
775 uint32_t ivlan:IVLAN_BITWIDTH;
776 uint32_t ovlan:OVLAN_BITWIDTH;
777
778
779
780
781 uint8_t lip[16];
782 uint8_t fip[16];
783 uint16_t lport;
784 uint16_t fport;
785};
786
787
788
789struct ch_filter_specification {
790
791
792 uint32_t hitcnts:1;
793 uint32_t prio:1;
794
795
796
797
798 uint32_t type:1;
799
800
801
802
803
804 uint32_t action:2;
805
806 uint32_t rpttid:1;
807
808 uint32_t dirsteer:1;
809 uint32_t iq:10;
810
811 uint32_t maskhash:1;
812 uint32_t dirsteerhash:1;
813
814
815
816
817
818
819 uint32_t eport:2;
820 uint32_t newdmac:1;
821 uint32_t newsmac:1;
822 uint32_t newvlan:2;
823 uint8_t dmac[ETH_ALEN];
824 uint8_t smac[ETH_ALEN];
825 uint16_t vlan;
826
827
828
829 struct ch_filter_tuple val;
830 struct ch_filter_tuple mask;
831};
832
833enum {
834 FILTER_PASS = 0,
835 FILTER_DROP,
836 FILTER_SWITCH
837};
838
839enum {
840 VLAN_NOCHANGE = 0,
841 VLAN_REMOVE,
842 VLAN_INSERT,
843 VLAN_REWRITE
844};
845
846static inline int is_t5(enum chip_type chip)
847{
848 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
849}
850
851static inline int is_t4(enum chip_type chip)
852{
853 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
854}
855
856static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
857{
858 return readl(adap->regs + reg_addr);
859}
860
861static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
862{
863 writel(val, adap->regs + reg_addr);
864}
865
866#ifndef readq
867static inline u64 readq(const volatile void __iomem *addr)
868{
869 return readl(addr) + ((u64)readl(addr + 4) << 32);
870}
871
872static inline void writeq(u64 val, volatile void __iomem *addr)
873{
874 writel(val, addr);
875 writel(val >> 32, addr + 4);
876}
877#endif
878
879static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
880{
881 return readq(adap->regs + reg_addr);
882}
883
884static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
885{
886 writeq(val, adap->regs + reg_addr);
887}
888
889
890
891
892
893
894
895static inline struct port_info *netdev2pinfo(const struct net_device *dev)
896{
897 return netdev_priv(dev);
898}
899
900
901
902
903
904
905
906
907static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
908{
909 return netdev_priv(adap->port[idx]);
910}
911
912
913
914
915
916
917
918static inline struct adapter *netdev2adap(const struct net_device *dev)
919{
920 return netdev2pinfo(dev)->adapter;
921}
922
923#ifdef CONFIG_NET_RX_BUSY_POLL
924static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
925{
926 spin_lock_init(&q->bpoll_lock);
927 q->bpoll_state = CXGB_POLL_STATE_IDLE;
928}
929
930static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
931{
932 bool rc = true;
933
934 spin_lock(&q->bpoll_lock);
935 if (q->bpoll_state & CXGB_POLL_LOCKED) {
936 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
937 rc = false;
938 } else {
939 q->bpoll_state = CXGB_POLL_STATE_NAPI;
940 }
941 spin_unlock(&q->bpoll_lock);
942 return rc;
943}
944
945static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
946{
947 bool rc = false;
948
949 spin_lock(&q->bpoll_lock);
950 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
951 rc = true;
952 q->bpoll_state = CXGB_POLL_STATE_IDLE;
953 spin_unlock(&q->bpoll_lock);
954 return rc;
955}
956
957static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
958{
959 bool rc = true;
960
961 spin_lock_bh(&q->bpoll_lock);
962 if (q->bpoll_state & CXGB_POLL_LOCKED) {
963 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
964 rc = false;
965 } else {
966 q->bpoll_state |= CXGB_POLL_STATE_POLL;
967 }
968 spin_unlock_bh(&q->bpoll_lock);
969 return rc;
970}
971
972static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
973{
974 bool rc = false;
975
976 spin_lock_bh(&q->bpoll_lock);
977 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
978 rc = true;
979 q->bpoll_state = CXGB_POLL_STATE_IDLE;
980 spin_unlock_bh(&q->bpoll_lock);
981 return rc;
982}
983
984static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
985{
986 return q->bpoll_state & CXGB_POLL_USER_PEND;
987}
988#else
989static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
990{
991}
992
993static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
994{
995 return true;
996}
997
998static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
999{
1000 return false;
1001}
1002
1003static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1004{
1005 return false;
1006}
1007
1008static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1009{
1010 return false;
1011}
1012
1013static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1014{
1015 return false;
1016}
1017#endif
1018
1019
1020
1021
1022
1023
1024static inline unsigned int mk_adap_vers(struct adapter *ap)
1025{
1026 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1027 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1028}
1029
1030
1031static inline unsigned int qtimer_val(const struct adapter *adap,
1032 const struct sge_rspq *q)
1033{
1034 unsigned int idx = q->intr_params >> 1;
1035
1036 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1037}
1038
1039
1040extern char cxgb4_driver_name[];
1041extern const char cxgb4_driver_version[];
1042
1043void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1044void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1045
1046void *t4_alloc_mem(size_t size);
1047
1048void t4_free_sge_resources(struct adapter *adap);
1049void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1050irq_handler_t t4_intr_handler(struct adapter *adap);
1051netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1052int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1053 const struct pkt_gl *gl);
1054int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1055int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1056int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1057 struct net_device *dev, int intr_idx,
1058 struct sge_fl *fl, rspq_handler_t hnd);
1059int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1060 struct net_device *dev, struct netdev_queue *netdevq,
1061 unsigned int iqid);
1062int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1063 struct net_device *dev, unsigned int iqid,
1064 unsigned int cmplqid);
1065int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1066 struct net_device *dev, unsigned int iqid);
1067irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1068int t4_sge_init(struct adapter *adap);
1069void t4_sge_start(struct adapter *adap);
1070void t4_sge_stop(struct adapter *adap);
1071int cxgb_busy_poll(struct napi_struct *napi);
1072int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1073 unsigned int cnt);
1074void cxgb4_set_ethtool_ops(struct net_device *netdev);
1075int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1076extern int dbfifo_int_thresh;
1077
1078#define for_each_port(adapter, iter) \
1079 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1080
1081static inline int is_bypass(struct adapter *adap)
1082{
1083 return adap->params.bypass;
1084}
1085
1086static inline int is_bypass_device(int device)
1087{
1088
1089 switch (device) {
1090 case 0x440b:
1091 case 0x440c:
1092 return 1;
1093 default:
1094 return 0;
1095 }
1096}
1097
1098static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1099{
1100 return adap->params.vpd.cclk / 1000;
1101}
1102
1103static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1104 unsigned int us)
1105{
1106 return (us * adap->params.vpd.cclk) / 1000;
1107}
1108
1109static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1110 unsigned int ticks)
1111{
1112
1113 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1114 adapter->params.vpd.cclk);
1115}
1116
1117void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1118 u32 val);
1119
1120int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1121 void *rpl, bool sleep_ok);
1122
1123static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1124 int size, void *rpl)
1125{
1126 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1127}
1128
1129static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1130 int size, void *rpl)
1131{
1132 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1133}
1134
1135void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1136 unsigned int data_reg, const u32 *vals,
1137 unsigned int nregs, unsigned int start_idx);
1138void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1139 unsigned int data_reg, u32 *vals, unsigned int nregs,
1140 unsigned int start_idx);
1141void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1142
1143struct fw_filter_wr;
1144
1145void t4_intr_enable(struct adapter *adapter);
1146void t4_intr_disable(struct adapter *adapter);
1147int t4_slow_intr_handler(struct adapter *adapter);
1148
1149int t4_wait_dev_ready(void __iomem *regs);
1150int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1151 struct link_config *lc);
1152int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1153
1154#define T4_MEMORY_WRITE 0
1155#define T4_MEMORY_READ 1
1156int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1157 void *buf, int dir);
1158static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1159 u32 len, __be32 *buf)
1160{
1161 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1162}
1163
1164unsigned int t4_get_regs_len(struct adapter *adapter);
1165void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1166
1167int t4_seeprom_wp(struct adapter *adapter, bool enable);
1168int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1169int t4_read_flash(struct adapter *adapter, unsigned int addr,
1170 unsigned int nwords, u32 *data, int byte_oriented);
1171int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1172int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1173int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1174 const u8 *fw_data, unsigned int size, int force);
1175unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1176int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1177int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1178int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1179int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1180 const u8 *fw_data, unsigned int fw_size,
1181 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1182int t4_prep_adapter(struct adapter *adapter);
1183
1184enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1185int cxgb4_t4_bar2_sge_qregs(struct adapter *adapter,
1186 unsigned int qid,
1187 enum t4_bar2_qtype qtype,
1188 u64 *pbar2_qoffset,
1189 unsigned int *pbar2_qid);
1190
1191unsigned int qtimer_val(const struct adapter *adap,
1192 const struct sge_rspq *q);
1193
1194int t4_init_devlog_params(struct adapter *adapter);
1195int t4_init_sge_params(struct adapter *adapter);
1196int t4_init_tp_params(struct adapter *adap);
1197int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1198int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1199void t4_fatal_err(struct adapter *adapter);
1200int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1201 int start, int n, const u16 *rspq, unsigned int nrspq);
1202int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1203 unsigned int flags);
1204int t4_read_rss(struct adapter *adapter, u16 *entries);
1205void t4_read_rss_key(struct adapter *adapter, u32 *key);
1206void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1207void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1208 u32 *valp);
1209void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1210 u32 *vfl, u32 *vfh);
1211u32 t4_read_rss_pf_map(struct adapter *adapter);
1212u32 t4_read_rss_pf_mask(struct adapter *adapter);
1213
1214int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
1215 u64 *parity);
1216int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
1217 u64 *parity);
1218void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1219void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1220int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1221 size_t n);
1222int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1223 size_t n);
1224int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1225 unsigned int *valp);
1226int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1227 const unsigned int *valp);
1228int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1229void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1230const char *t4_get_port_type_description(enum fw_port_type port_type);
1231void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1232void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1233void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1234void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1235 unsigned int mask, unsigned int val);
1236void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1237void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1238 struct tp_tcp_stats *v6);
1239void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1240 const unsigned short *alpha, const unsigned short *beta);
1241
1242void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1243
1244void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1245
1246void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1247 const u8 *addr);
1248int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1249 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1250
1251int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1252 enum dev_master master, enum dev_state *state);
1253int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1254int t4_early_init(struct adapter *adap, unsigned int mbox);
1255int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1256int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1257 unsigned int cache_line_size);
1258int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1259int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1260 unsigned int vf, unsigned int nparams, const u32 *params,
1261 u32 *val);
1262int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1263 unsigned int vf, unsigned int nparams, const u32 *params,
1264 const u32 *val);
1265int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox,
1266 unsigned int pf, unsigned int vf,
1267 unsigned int nparams, const u32 *params,
1268 const u32 *val);
1269int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1270 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1271 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1272 unsigned int vi, unsigned int cmask, unsigned int pmask,
1273 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1274int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1275 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1276 unsigned int *rss_size);
1277int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1278 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1279 bool sleep_ok);
1280int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1281 unsigned int viid, bool free, unsigned int naddr,
1282 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1283int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1284 int idx, const u8 *addr, bool persist, bool add_smt);
1285int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1286 bool ucast, u64 vec, bool sleep_ok);
1287int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1288 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1289int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1290 bool rx_en, bool tx_en);
1291int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1292 unsigned int nblinks);
1293int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1294 unsigned int mmd, unsigned int reg, u16 *valp);
1295int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1296 unsigned int mmd, unsigned int reg, u16 val);
1297int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1298 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1299 unsigned int fl0id, unsigned int fl1id);
1300int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1301 unsigned int vf, unsigned int eqid);
1302int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1303 unsigned int vf, unsigned int eqid);
1304int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1305 unsigned int vf, unsigned int eqid);
1306int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1307void t4_db_full(struct adapter *adapter);
1308void t4_db_dropped(struct adapter *adapter);
1309int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1310 u32 addr, u32 val);
1311void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1312void t4_free_mem(void *addr);
1313#endif
1314