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28#include "ixgbe.h"
29#include <linux/ptp_classify.h>
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85
86#define IXGBE_INCVAL_10GB 0x66666666
87#define IXGBE_INCVAL_1GB 0x40000000
88#define IXGBE_INCVAL_100 0x50000000
89
90#define IXGBE_INCVAL_SHIFT_10GB 28
91#define IXGBE_INCVAL_SHIFT_1GB 24
92#define IXGBE_INCVAL_SHIFT_100 21
93
94#define IXGBE_INCVAL_SHIFT_82599 7
95#define IXGBE_INCPER_SHIFT_82599 24
96#define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL
97
98#define IXGBE_OVERFLOW_PERIOD (HZ * 30)
99#define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
100
101
102
103
104
105#define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL
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118
119static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
120{
121 struct ixgbe_hw *hw = &adapter->hw;
122 int shift = adapter->cc.shift;
123 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
124 u64 ns = 0, clock_edge = 0;
125
126 if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
127 (hw->mac.type == ixgbe_mac_X540)) {
128
129
130 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
131 IXGBE_WRITE_FLUSH(hw);
132
133 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
134
135
136
137
138
139 esdp |= (IXGBE_ESDP_SDP0_DIR |
140 IXGBE_ESDP_SDP0_NATIVE);
141
142
143
144
145
146 tsauxc = (IXGBE_TSAUXC_EN_CLK |
147 IXGBE_TSAUXC_SYNCLK |
148 IXGBE_TSAUXC_SDP0_INT);
149
150
151 clktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift);
152 clktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32);
153
154
155
156
157
158
159 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
160 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
161 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
162
163 div_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem);
164 clock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift);
165
166
167 trgttiml = (u32)clock_edge;
168 trgttimh = (u32)(clock_edge >> 32);
169
170 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
171 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
172 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
173 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
174
175 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
176 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
177 } else {
178 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
179 }
180
181 IXGBE_WRITE_FLUSH(hw);
182}
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190
191
192static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
193{
194 struct ixgbe_adapter *adapter =
195 container_of(cc, struct ixgbe_adapter, cc);
196 struct ixgbe_hw *hw = &adapter->hw;
197 u64 stamp = 0;
198
199 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
200 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
201
202 return stamp;
203}
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211
212
213static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
214{
215 struct ixgbe_adapter *adapter =
216 container_of(ptp, struct ixgbe_adapter, ptp_caps);
217 struct ixgbe_hw *hw = &adapter->hw;
218 u64 freq;
219 u32 diff, incval;
220 int neg_adj = 0;
221
222 if (ppb < 0) {
223 neg_adj = 1;
224 ppb = -ppb;
225 }
226
227 smp_mb();
228 incval = ACCESS_ONCE(adapter->base_incval);
229
230 freq = incval;
231 freq *= ppb;
232 diff = div_u64(freq, 1000000000ULL);
233
234 incval = neg_adj ? (incval - diff) : (incval + diff);
235
236 switch (hw->mac.type) {
237 case ixgbe_mac_X540:
238 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
239 break;
240 case ixgbe_mac_82599EB:
241 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
242 (1 << IXGBE_INCPER_SHIFT_82599) |
243 incval);
244 break;
245 default:
246 break;
247 }
248
249 return 0;
250}
251
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253
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257
258
259static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
260{
261 struct ixgbe_adapter *adapter =
262 container_of(ptp, struct ixgbe_adapter, ptp_caps);
263 unsigned long flags;
264
265 spin_lock_irqsave(&adapter->tmreg_lock, flags);
266 timecounter_adjtime(&adapter->tc, delta);
267 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
268
269 ixgbe_ptp_setup_sdp(adapter);
270
271 return 0;
272}
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280
281
282static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
283{
284 struct ixgbe_adapter *adapter =
285 container_of(ptp, struct ixgbe_adapter, ptp_caps);
286 u64 ns;
287 unsigned long flags;
288
289 spin_lock_irqsave(&adapter->tmreg_lock, flags);
290 ns = timecounter_read(&adapter->tc);
291 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
292
293 *ts = ns_to_timespec64(ns);
294
295 return 0;
296}
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303
304
305
306static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
307 const struct timespec64 *ts)
308{
309 struct ixgbe_adapter *adapter =
310 container_of(ptp, struct ixgbe_adapter, ptp_caps);
311 u64 ns;
312 unsigned long flags;
313
314 ns = timespec64_to_ns(ts);
315
316
317 spin_lock_irqsave(&adapter->tmreg_lock, flags);
318 timecounter_init(&adapter->tc, &adapter->cc, ns);
319 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
320
321 ixgbe_ptp_setup_sdp(adapter);
322 return 0;
323}
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328
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331
332
333
334static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
335 struct ptp_clock_request *rq, int on)
336{
337 struct ixgbe_adapter *adapter =
338 container_of(ptp, struct ixgbe_adapter, ptp_caps);
339
340
341
342
343
344
345
346 if (rq->type == PTP_CLK_REQ_PPS) {
347 switch (adapter->hw.mac.type) {
348 case ixgbe_mac_X540:
349 if (on)
350 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
351 else
352 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
353
354 ixgbe_ptp_setup_sdp(adapter);
355 return 0;
356 default:
357 break;
358 }
359 }
360
361 return -ENOTSUPP;
362}
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370
371
372void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
373{
374 struct ixgbe_hw *hw = &adapter->hw;
375 struct ptp_clock_event event;
376
377 event.type = PTP_CLOCK_PPS;
378
379
380
381
382
383 if (!adapter->ptp_clock)
384 return;
385
386 switch (hw->mac.type) {
387 case ixgbe_mac_X540:
388 ptp_clock_event(adapter->ptp_clock, &event);
389 break;
390 default:
391 break;
392 }
393}
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401
402
403void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
404{
405 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
406 IXGBE_OVERFLOW_PERIOD);
407 struct timespec64 ts;
408
409 if (timeout) {
410 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
411 adapter->last_overflow_check = jiffies;
412 }
413}
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421
422
423
424void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
425{
426 struct ixgbe_hw *hw = &adapter->hw;
427 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
428 unsigned long rx_event;
429
430
431
432
433 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
434 adapter->last_rx_ptp_check = jiffies;
435 return;
436 }
437
438
439 rx_event = adapter->last_rx_ptp_check;
440 if (time_after(adapter->last_rx_timestamp, rx_event))
441 rx_event = adapter->last_rx_timestamp;
442
443
444 if (time_is_before_jiffies(rx_event + 5*HZ)) {
445 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
446 adapter->last_rx_ptp_check = jiffies;
447
448 e_warn(drv, "clearing RX Timestamp hang\n");
449 }
450}
451
452
453
454
455
456
457
458
459
460static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
461{
462 struct ixgbe_hw *hw = &adapter->hw;
463 struct skb_shared_hwtstamps shhwtstamps;
464 u64 regval = 0, ns;
465 unsigned long flags;
466
467 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
468 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
469
470 spin_lock_irqsave(&adapter->tmreg_lock, flags);
471 ns = timecounter_cyc2time(&adapter->tc, regval);
472 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
473
474 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
475 shhwtstamps.hwtstamp = ns_to_ktime(ns);
476 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
477
478 dev_kfree_skb_any(adapter->ptp_tx_skb);
479 adapter->ptp_tx_skb = NULL;
480 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
481}
482
483
484
485
486
487
488
489
490
491static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
492{
493 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
494 ptp_tx_work);
495 struct ixgbe_hw *hw = &adapter->hw;
496 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
497 IXGBE_PTP_TX_TIMEOUT);
498 u32 tsynctxctl;
499
500 if (timeout) {
501 dev_kfree_skb_any(adapter->ptp_tx_skb);
502 adapter->ptp_tx_skb = NULL;
503 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
504 e_warn(drv, "clearing Tx Timestamp hang\n");
505 return;
506 }
507
508 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
509 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID)
510 ixgbe_ptp_tx_hwtstamp(adapter);
511 else
512
513 schedule_work(&adapter->ptp_tx_work);
514}
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519
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522
523
524
525void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb)
526{
527 struct ixgbe_hw *hw = &adapter->hw;
528 struct skb_shared_hwtstamps *shhwtstamps;
529 u64 regval = 0, ns;
530 u32 tsyncrxctl;
531 unsigned long flags;
532
533 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
534 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
535 return;
536
537 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
538 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
539
540 spin_lock_irqsave(&adapter->tmreg_lock, flags);
541 ns = timecounter_cyc2time(&adapter->tc, regval);
542 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
543
544 shhwtstamps = skb_hwtstamps(skb);
545 shhwtstamps->hwtstamp = ns_to_ktime(ns);
546
547
548
549
550 adapter->last_rx_timestamp = jiffies;
551}
552
553int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
554{
555 struct hwtstamp_config *config = &adapter->tstamp_config;
556
557 return copy_to_user(ifr->ifr_data, config,
558 sizeof(*config)) ? -EFAULT : 0;
559}
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585
586static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
587 struct hwtstamp_config *config)
588{
589 struct ixgbe_hw *hw = &adapter->hw;
590 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
591 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
592 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
593 bool is_l2 = false;
594 u32 regval;
595
596
597 if (config->flags)
598 return -EINVAL;
599
600 switch (config->tx_type) {
601 case HWTSTAMP_TX_OFF:
602 tsync_tx_ctl = 0;
603 case HWTSTAMP_TX_ON:
604 break;
605 default:
606 return -ERANGE;
607 }
608
609 switch (config->rx_filter) {
610 case HWTSTAMP_FILTER_NONE:
611 tsync_rx_ctl = 0;
612 tsync_rx_mtrl = 0;
613 break;
614 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
615 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
616 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
617 break;
618 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
619 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
620 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
621 break;
622 case HWTSTAMP_FILTER_PTP_V2_EVENT:
623 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
624 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
625 case HWTSTAMP_FILTER_PTP_V2_SYNC:
626 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
627 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
628 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
629 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
630 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
631 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
632 is_l2 = true;
633 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
634 break;
635 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
636 case HWTSTAMP_FILTER_ALL:
637 default:
638
639
640
641
642
643
644 config->rx_filter = HWTSTAMP_FILTER_NONE;
645 return -ERANGE;
646 }
647
648 if (hw->mac.type == ixgbe_mac_82598EB) {
649 if (tsync_rx_ctl | tsync_tx_ctl)
650 return -ERANGE;
651 return 0;
652 }
653
654
655 if (is_l2)
656 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
657 (IXGBE_ETQF_FILTER_EN |
658 IXGBE_ETQF_1588 |
659 ETH_P_1588));
660 else
661 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
662
663
664 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
665 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
666 regval |= tsync_tx_ctl;
667 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
668
669
670 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
671 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
672 regval |= tsync_rx_ctl;
673 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
674
675
676 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
677
678 IXGBE_WRITE_FLUSH(hw);
679
680
681 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
682 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
683
684 return 0;
685}
686
687
688
689
690
691
692
693
694
695int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
696{
697 struct hwtstamp_config config;
698 int err;
699
700 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
701 return -EFAULT;
702
703 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
704 if (err)
705 return err;
706
707
708 memcpy(&adapter->tstamp_config, &config,
709 sizeof(adapter->tstamp_config));
710
711 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
712 -EFAULT : 0;
713}
714
715
716
717
718
719
720
721
722
723
724
725void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
726{
727 struct ixgbe_hw *hw = &adapter->hw;
728 u32 incval = 0;
729 u32 shift = 0;
730 unsigned long flags;
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746 switch (adapter->link_speed) {
747 case IXGBE_LINK_SPEED_100_FULL:
748 incval = IXGBE_INCVAL_100;
749 shift = IXGBE_INCVAL_SHIFT_100;
750 break;
751 case IXGBE_LINK_SPEED_1GB_FULL:
752 incval = IXGBE_INCVAL_1GB;
753 shift = IXGBE_INCVAL_SHIFT_1GB;
754 break;
755 case IXGBE_LINK_SPEED_10GB_FULL:
756 default:
757 incval = IXGBE_INCVAL_10GB;
758 shift = IXGBE_INCVAL_SHIFT_10GB;
759 break;
760 }
761
762
763
764
765
766
767
768 switch (hw->mac.type) {
769 case ixgbe_mac_X540:
770 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
771 break;
772 case ixgbe_mac_82599EB:
773 incval >>= IXGBE_INCVAL_SHIFT_82599;
774 shift -= IXGBE_INCVAL_SHIFT_82599;
775 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
776 (1 << IXGBE_INCPER_SHIFT_82599) |
777 incval);
778 break;
779 default:
780
781 return;
782 }
783
784
785 ACCESS_ONCE(adapter->base_incval) = incval;
786 smp_mb();
787
788
789 spin_lock_irqsave(&adapter->tmreg_lock, flags);
790
791 memset(&adapter->cc, 0, sizeof(adapter->cc));
792 adapter->cc.read = ixgbe_ptp_read;
793 adapter->cc.mask = CYCLECOUNTER_MASK(64);
794 adapter->cc.shift = shift;
795 adapter->cc.mult = 1;
796
797 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
798}
799
800
801
802
803
804
805
806
807
808
809
810
811
812void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
813{
814 struct ixgbe_hw *hw = &adapter->hw;
815 unsigned long flags;
816
817
818 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
819 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
820 IXGBE_WRITE_FLUSH(hw);
821
822
823 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
824
825 ixgbe_ptp_start_cyclecounter(adapter);
826
827 spin_lock_irqsave(&adapter->tmreg_lock, flags);
828
829
830 timecounter_init(&adapter->tc, &adapter->cc,
831 ktime_to_ns(ktime_get_real()));
832
833 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
834
835
836
837
838
839 ixgbe_ptp_setup_sdp(adapter);
840}
841
842
843
844
845
846
847
848
849
850
851
852static int ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
853{
854 struct net_device *netdev = adapter->netdev;
855 long err;
856
857
858 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
859 return 0;
860
861 switch (adapter->hw.mac.type) {
862 case ixgbe_mac_X540:
863 snprintf(adapter->ptp_caps.name,
864 sizeof(adapter->ptp_caps.name),
865 "%s", netdev->name);
866 adapter->ptp_caps.owner = THIS_MODULE;
867 adapter->ptp_caps.max_adj = 250000000;
868 adapter->ptp_caps.n_alarm = 0;
869 adapter->ptp_caps.n_ext_ts = 0;
870 adapter->ptp_caps.n_per_out = 0;
871 adapter->ptp_caps.pps = 1;
872 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
873 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
874 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
875 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
876 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
877 break;
878 case ixgbe_mac_82599EB:
879 snprintf(adapter->ptp_caps.name,
880 sizeof(adapter->ptp_caps.name),
881 "%s", netdev->name);
882 adapter->ptp_caps.owner = THIS_MODULE;
883 adapter->ptp_caps.max_adj = 250000000;
884 adapter->ptp_caps.n_alarm = 0;
885 adapter->ptp_caps.n_ext_ts = 0;
886 adapter->ptp_caps.n_per_out = 0;
887 adapter->ptp_caps.pps = 0;
888 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
889 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
890 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
891 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
892 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
893 break;
894 default:
895 adapter->ptp_clock = NULL;
896 return -EOPNOTSUPP;
897 }
898
899 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
900 &adapter->pdev->dev);
901 if (IS_ERR(adapter->ptp_clock)) {
902 err = PTR_ERR(adapter->ptp_clock);
903 adapter->ptp_clock = NULL;
904 e_dev_err("ptp_clock_register failed\n");
905 return err;
906 } else
907 e_dev_info("registered PHC device on %s\n", netdev->name);
908
909
910
911
912
913 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
914 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
915
916 return 0;
917}
918
919
920
921
922
923
924
925
926
927void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
928{
929
930
931
932
933 spin_lock_init(&adapter->tmreg_lock);
934
935
936 if (ixgbe_ptp_create_clock(adapter))
937 return;
938
939
940 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
941
942
943 ixgbe_ptp_reset(adapter);
944
945
946 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
947
948 return;
949}
950
951
952
953
954
955
956
957
958void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
959{
960
961 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
962 return;
963
964
965
966
967 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TSAUXC, 0x0);
968
969
970 cancel_work_sync(&adapter->ptp_tx_work);
971 if (adapter->ptp_tx_skb) {
972 dev_kfree_skb_any(adapter->ptp_tx_skb);
973 adapter->ptp_tx_skb = NULL;
974 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
975 }
976}
977
978
979
980
981
982
983
984
985void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
986{
987
988 ixgbe_ptp_suspend(adapter);
989
990
991 if (adapter->ptp_clock) {
992 ptp_clock_unregister(adapter->ptp_clock);
993 adapter->ptp_clock = NULL;
994 e_dev_info("removed PHC on %s\n",
995 adapter->netdev->name);
996 }
997}
998