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37#ifndef MLX4_H
38#define MLX4_H
39
40#include <linux/mutex.h>
41#include <linux/radix-tree.h>
42#include <linux/rbtree.h>
43#include <linux/timer.h>
44#include <linux/semaphore.h>
45#include <linux/workqueue.h>
46#include <linux/interrupt.h>
47#include <linux/spinlock.h>
48
49#include <linux/mlx4/device.h>
50#include <linux/mlx4/driver.h>
51#include <linux/mlx4/doorbell.h>
52#include <linux/mlx4/cmd.h>
53#include "fw_qos.h"
54
55#define DRV_NAME "mlx4_core"
56#define PFX DRV_NAME ": "
57#define DRV_VERSION "2.2-1"
58#define DRV_RELDATE "Feb, 2014"
59
60#define MLX4_FS_UDP_UC_EN (1 << 1)
61#define MLX4_FS_TCP_UC_EN (1 << 2)
62#define MLX4_FS_NUM_OF_L2_ADDR 8
63#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
64#define MLX4_FS_NUM_MCG (1 << 17)
65
66#define INIT_HCA_TPT_MW_ENABLE (1 << 7)
67
68enum {
69 MLX4_HCR_BASE = 0x80680,
70 MLX4_HCR_SIZE = 0x0001c,
71 MLX4_CLR_INT_SIZE = 0x00008,
72 MLX4_SLAVE_COMM_BASE = 0x0,
73 MLX4_COMM_PAGESIZE = 0x1000,
74 MLX4_CLOCK_SIZE = 0x00008,
75 MLX4_COMM_CHAN_CAPS = 0x8,
76 MLX4_COMM_CHAN_FLAGS = 0xc
77};
78
79enum {
80 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
81 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
82 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
83 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
84 MLX4_MTT_ENTRY_PER_SEG = 8,
85};
86
87enum {
88 MLX4_NUM_PDS = 1 << 15
89};
90
91enum {
92 MLX4_CMPT_TYPE_QP = 0,
93 MLX4_CMPT_TYPE_SRQ = 1,
94 MLX4_CMPT_TYPE_CQ = 2,
95 MLX4_CMPT_TYPE_EQ = 3,
96 MLX4_CMPT_NUM_TYPE
97};
98
99enum {
100 MLX4_CMPT_SHIFT = 24,
101 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
102};
103
104enum mlx4_mpt_state {
105 MLX4_MPT_DISABLED = 0,
106 MLX4_MPT_EN_HW,
107 MLX4_MPT_EN_SW
108};
109
110#define MLX4_COMM_TIME 10000
111#define MLX4_COMM_OFFLINE_TIME_OUT 30000
112#define MLX4_COMM_CMD_NA_OP 0x0
113
114
115enum {
116 MLX4_COMM_CMD_RESET,
117 MLX4_COMM_CMD_VHCR0,
118 MLX4_COMM_CMD_VHCR1,
119 MLX4_COMM_CMD_VHCR2,
120 MLX4_COMM_CMD_VHCR_EN,
121 MLX4_COMM_CMD_VHCR_POST,
122 MLX4_COMM_CMD_FLR = 254
123};
124
125enum {
126 MLX4_VF_SMI_DISABLED,
127 MLX4_VF_SMI_ENABLED
128};
129
130
131#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
132
133#define NUM_OF_RESET_RETRIES 10
134#define SLEEP_TIME_IN_RESET (2 * 1000)
135enum mlx4_resource {
136 RES_QP,
137 RES_CQ,
138 RES_SRQ,
139 RES_XRCD,
140 RES_MPT,
141 RES_MTT,
142 RES_MAC,
143 RES_VLAN,
144 RES_EQ,
145 RES_COUNTER,
146 RES_FS_RULE,
147 MLX4_NUM_OF_RESOURCE_TYPE
148};
149
150enum mlx4_alloc_mode {
151 RES_OP_RESERVE,
152 RES_OP_RESERVE_AND_MAP,
153 RES_OP_MAP_ICM,
154};
155
156enum mlx4_res_tracker_free_type {
157 RES_TR_FREE_ALL,
158 RES_TR_FREE_SLAVES_ONLY,
159 RES_TR_FREE_STRUCTS_ONLY,
160};
161
162
163
164
165
166
167
168
169
170
171struct mlx4_vhcr {
172 u64 in_param;
173 u64 out_param;
174 u32 in_modifier;
175 u32 errno;
176 u16 op;
177 u16 token;
178 u8 op_modifier;
179 u8 e_bit;
180};
181
182struct mlx4_vhcr_cmd {
183 __be64 in_param;
184 __be32 in_modifier;
185 u32 reserved1;
186 __be64 out_param;
187 __be16 token;
188 u16 reserved;
189 u8 status;
190 u8 flags;
191 __be16 opcode;
192};
193
194struct mlx4_cmd_info {
195 u16 opcode;
196 bool has_inbox;
197 bool has_outbox;
198 bool out_is_imm;
199 bool encode_slave_id;
200 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
201 struct mlx4_cmd_mailbox *inbox);
202 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
203 struct mlx4_cmd_mailbox *inbox,
204 struct mlx4_cmd_mailbox *outbox,
205 struct mlx4_cmd_info *cmd);
206};
207
208#ifdef CONFIG_MLX4_DEBUG
209extern int mlx4_debug_level;
210#else
211#define mlx4_debug_level (0)
212#endif
213
214#define mlx4_dbg(mdev, format, ...) \
215do { \
216 if (mlx4_debug_level) \
217 dev_printk(KERN_DEBUG, \
218 &(mdev)->persist->pdev->dev, format, \
219 ##__VA_ARGS__); \
220} while (0)
221
222#define mlx4_err(mdev, format, ...) \
223 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
224#define mlx4_info(mdev, format, ...) \
225 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
226#define mlx4_warn(mdev, format, ...) \
227 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
228
229extern int mlx4_log_num_mgm_entry_size;
230extern int log_mtts_per_seg;
231extern int mlx4_internal_err_reset;
232
233#define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \
234 MLX4_MFUNC_MAX))
235#define ALL_SLAVES 0xff
236
237struct mlx4_bitmap {
238 u32 last;
239 u32 top;
240 u32 max;
241 u32 reserved_top;
242 u32 mask;
243 u32 avail;
244 u32 effective_len;
245 spinlock_t lock;
246 unsigned long *table;
247};
248
249struct mlx4_buddy {
250 unsigned long **bits;
251 unsigned int *num_free;
252 u32 max_order;
253 spinlock_t lock;
254};
255
256struct mlx4_icm;
257
258struct mlx4_icm_table {
259 u64 virt;
260 int num_icm;
261 u32 num_obj;
262 int obj_size;
263 int lowmem;
264 int coherent;
265 struct mutex mutex;
266 struct mlx4_icm **icm;
267};
268
269#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
270#define MLX4_MPT_FLAG_FREE (0x3UL << 28)
271#define MLX4_MPT_FLAG_MIO (1 << 17)
272#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
273#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
274#define MLX4_MPT_FLAG_REGION (1 << 8)
275
276#define MLX4_MPT_PD_MASK (0x1FFFFUL)
277#define MLX4_MPT_PD_VF_MASK (0xFE0000UL)
278#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
279#define MLX4_MPT_PD_FLAG_RAE (1 << 28)
280#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
281
282#define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
283
284#define MLX4_MPT_STATUS_SW 0xF0
285#define MLX4_MPT_STATUS_HW 0x00
286
287#define MLX4_CQE_SIZE_MASK_STRIDE 0x3
288#define MLX4_EQE_SIZE_MASK_STRIDE 0x30
289
290
291
292
293struct mlx4_mpt_entry {
294 __be32 flags;
295 __be32 qpn;
296 __be32 key;
297 __be32 pd_flags;
298 __be64 start;
299 __be64 length;
300 __be32 lkey;
301 __be32 win_cnt;
302 u8 reserved1[3];
303 u8 mtt_rep;
304 __be64 mtt_addr;
305 __be32 mtt_sz;
306 __be32 entity_size;
307 __be32 first_byte_offset;
308} __packed;
309
310
311
312
313struct mlx4_eq_context {
314 __be32 flags;
315 u16 reserved1[3];
316 __be16 page_offset;
317 u8 log_eq_size;
318 u8 reserved2[4];
319 u8 eq_period;
320 u8 reserved3;
321 u8 eq_max_count;
322 u8 reserved4[3];
323 u8 intr;
324 u8 log_page_size;
325 u8 reserved5[2];
326 u8 mtt_base_addr_h;
327 __be32 mtt_base_addr_l;
328 u32 reserved6[2];
329 __be32 consumer_index;
330 __be32 producer_index;
331 u32 reserved7[4];
332};
333
334struct mlx4_cq_context {
335 __be32 flags;
336 u16 reserved1[3];
337 __be16 page_offset;
338 __be32 logsize_usrpage;
339 __be16 cq_period;
340 __be16 cq_max_count;
341 u8 reserved2[3];
342 u8 comp_eqn;
343 u8 log_page_size;
344 u8 reserved3[2];
345 u8 mtt_base_addr_h;
346 __be32 mtt_base_addr_l;
347 __be32 last_notified_index;
348 __be32 solicit_producer_index;
349 __be32 consumer_index;
350 __be32 producer_index;
351 u32 reserved4[2];
352 __be64 db_rec_addr;
353};
354
355struct mlx4_srq_context {
356 __be32 state_logsize_srqn;
357 u8 logstride;
358 u8 reserved1;
359 __be16 xrcd;
360 __be32 pg_offset_cqn;
361 u32 reserved2;
362 u8 log_page_size;
363 u8 reserved3[2];
364 u8 mtt_base_addr_h;
365 __be32 mtt_base_addr_l;
366 __be32 pd;
367 __be16 limit_watermark;
368 __be16 wqe_cnt;
369 u16 reserved4;
370 __be16 wqe_counter;
371 u32 reserved5;
372 __be64 db_rec_addr;
373};
374
375struct mlx4_eq_tasklet {
376 struct list_head list;
377 struct list_head process_list;
378 struct tasklet_struct task;
379
380 spinlock_t lock;
381};
382
383struct mlx4_eq {
384 struct mlx4_dev *dev;
385 void __iomem *doorbell;
386 int eqn;
387 u32 cons_index;
388 u16 irq;
389 u16 have_irq;
390 int nent;
391 struct mlx4_buf_list *page_list;
392 struct mlx4_mtt mtt;
393 struct mlx4_eq_tasklet tasklet_ctx;
394};
395
396struct mlx4_slave_eqe {
397 u8 type;
398 u8 port;
399 u32 param;
400};
401
402struct mlx4_slave_event_eq_info {
403 int eqn;
404 u16 token;
405};
406
407struct mlx4_profile {
408 int num_qp;
409 int rdmarc_per_qp;
410 int num_srq;
411 int num_cq;
412 int num_mcg;
413 int num_mpt;
414 unsigned num_mtt;
415};
416
417struct mlx4_fw {
418 u64 clr_int_base;
419 u64 catas_offset;
420 u64 comm_base;
421 u64 clock_offset;
422 struct mlx4_icm *fw_icm;
423 struct mlx4_icm *aux_icm;
424 u32 catas_size;
425 u16 fw_pages;
426 u8 clr_int_bar;
427 u8 catas_bar;
428 u8 comm_bar;
429 u8 clock_bar;
430};
431
432struct mlx4_comm {
433 u32 slave_write;
434 u32 slave_read;
435};
436
437enum {
438 MLX4_MCAST_CONFIG = 0,
439 MLX4_MCAST_DISABLE = 1,
440 MLX4_MCAST_ENABLE = 2,
441};
442
443#define VLAN_FLTR_SIZE 128
444
445struct mlx4_vlan_fltr {
446 __be32 entry[VLAN_FLTR_SIZE];
447};
448
449struct mlx4_mcast_entry {
450 struct list_head list;
451 u64 addr;
452};
453
454struct mlx4_promisc_qp {
455 struct list_head list;
456 u32 qpn;
457};
458
459struct mlx4_steer_index {
460 struct list_head list;
461 unsigned int index;
462 struct list_head duplicates;
463};
464
465#define MLX4_EVENT_TYPES_NUM 64
466
467struct mlx4_slave_state {
468 u8 comm_toggle;
469 u8 last_cmd;
470 u8 init_port_mask;
471 bool active;
472 bool old_vlan_api;
473 u8 function;
474 dma_addr_t vhcr_dma;
475 u16 mtu[MLX4_MAX_PORTS + 1];
476 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
477 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
478 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
479 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
480
481 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
482 u16 eq_pi;
483 u16 eq_ci;
484 spinlock_t lock;
485
486 u8 is_slave_going_down;
487 u32 cookie;
488 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
489};
490
491#define MLX4_VGT 4095
492#define NO_INDX (-1)
493
494struct mlx4_vport_state {
495 u64 mac;
496 u16 default_vlan;
497 u8 default_qos;
498 u32 tx_rate;
499 bool spoofchk;
500 u32 link_state;
501 u8 qos_vport;
502 __be64 guid;
503};
504
505struct mlx4_vf_admin_state {
506 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
507 u8 enable_smi[MLX4_MAX_PORTS + 1];
508};
509
510struct mlx4_vport_oper_state {
511 struct mlx4_vport_state state;
512 int mac_idx;
513 int vlan_idx;
514};
515
516struct mlx4_vf_oper_state {
517 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
518 u8 smi_enabled[MLX4_MAX_PORTS + 1];
519};
520
521struct slave_list {
522 struct mutex mutex;
523 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
524};
525
526struct resource_allocator {
527 spinlock_t alloc_lock;
528 union {
529 int res_reserved;
530 int res_port_rsvd[MLX4_MAX_PORTS];
531 };
532 union {
533 int res_free;
534 int res_port_free[MLX4_MAX_PORTS];
535 };
536 int *quota;
537 int *allocated;
538 int *guaranteed;
539};
540
541struct mlx4_resource_tracker {
542 spinlock_t lock;
543
544 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
545
546 struct slave_list *slave_list;
547 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
548};
549
550#define SLAVE_EVENT_EQ_SIZE 128
551struct mlx4_slave_event_eq {
552 u32 eqn;
553 u32 cons;
554 u32 prod;
555 spinlock_t event_lock;
556 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
557};
558
559struct mlx4_qos_manager {
560 int num_of_qos_vfs;
561 DECLARE_BITMAP(priority_bm, MLX4_NUM_UP);
562};
563
564struct mlx4_master_qp0_state {
565 int proxy_qp0_active;
566 int qp0_active;
567 int port_active;
568};
569
570struct mlx4_mfunc_master_ctx {
571 struct mlx4_slave_state *slave_state;
572 struct mlx4_vf_admin_state *vf_admin;
573 struct mlx4_vf_oper_state *vf_oper;
574 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
575 int init_port_ref[MLX4_MAX_PORTS + 1];
576 u16 max_mtu[MLX4_MAX_PORTS + 1];
577 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
578 struct mlx4_resource_tracker res_tracker;
579 struct workqueue_struct *comm_wq;
580 struct work_struct comm_work;
581 struct work_struct slave_event_work;
582 struct work_struct slave_flr_event_work;
583 spinlock_t slave_state_lock;
584 __be32 comm_arm_bit_vector[4];
585 struct mlx4_eqe cmd_eqe;
586 struct mlx4_slave_event_eq slave_eq;
587 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
588 struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1];
589};
590
591struct mlx4_mfunc {
592 struct mlx4_comm __iomem *comm;
593 struct mlx4_vhcr_cmd *vhcr;
594 dma_addr_t vhcr_dma;
595
596 struct mlx4_mfunc_master_ctx master;
597};
598
599#define MGM_QPN_MASK 0x00FFFFFF
600#define MGM_BLCK_LB_BIT 30
601
602struct mlx4_mgm {
603 __be32 next_gid_index;
604 __be32 members_count;
605 u32 reserved[2];
606 u8 gid[16];
607 __be32 qp[MLX4_MAX_QP_PER_MGM];
608};
609
610struct mlx4_cmd {
611 struct pci_pool *pool;
612 void __iomem *hcr;
613 struct mutex slave_cmd_mutex;
614 struct semaphore poll_sem;
615 struct semaphore event_sem;
616 int max_cmds;
617 spinlock_t context_lock;
618 int free_head;
619 struct mlx4_cmd_context *context;
620 u16 token_mask;
621 u8 use_events;
622 u8 toggle;
623 u8 comm_toggle;
624 u8 initialized;
625};
626
627enum {
628 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
629 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
630 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
631};
632struct mlx4_vf_immed_vlan_work {
633 struct work_struct work;
634 struct mlx4_priv *priv;
635 int flags;
636 int slave;
637 int vlan_ix;
638 int orig_vlan_ix;
639 u8 port;
640 u8 qos;
641 u8 qos_vport;
642 u16 vlan_id;
643 u16 orig_vlan_id;
644};
645
646
647struct mlx4_uar_table {
648 struct mlx4_bitmap bitmap;
649};
650
651struct mlx4_mr_table {
652 struct mlx4_bitmap mpt_bitmap;
653 struct mlx4_buddy mtt_buddy;
654 u64 mtt_base;
655 u64 mpt_base;
656 struct mlx4_icm_table mtt_table;
657 struct mlx4_icm_table dmpt_table;
658};
659
660struct mlx4_cq_table {
661 struct mlx4_bitmap bitmap;
662 spinlock_t lock;
663 struct radix_tree_root tree;
664 struct mlx4_icm_table table;
665 struct mlx4_icm_table cmpt_table;
666};
667
668struct mlx4_eq_table {
669 struct mlx4_bitmap bitmap;
670 char *irq_names;
671 void __iomem *clr_int;
672 void __iomem **uar_map;
673 u32 clr_mask;
674 struct mlx4_eq *eq;
675 struct mlx4_icm_table table;
676 struct mlx4_icm_table cmpt_table;
677 int have_irq;
678 u8 inta_pin;
679};
680
681struct mlx4_srq_table {
682 struct mlx4_bitmap bitmap;
683 spinlock_t lock;
684 struct radix_tree_root tree;
685 struct mlx4_icm_table table;
686 struct mlx4_icm_table cmpt_table;
687};
688
689enum mlx4_qp_table_zones {
690 MLX4_QP_TABLE_ZONE_GENERAL,
691 MLX4_QP_TABLE_ZONE_RSS,
692 MLX4_QP_TABLE_ZONE_RAW_ETH,
693 MLX4_QP_TABLE_ZONE_NUM
694};
695
696struct mlx4_qp_table {
697 struct mlx4_bitmap *bitmap_gen;
698 struct mlx4_zone_allocator *zones;
699 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM];
700 u32 rdmarc_base;
701 int rdmarc_shift;
702 spinlock_t lock;
703 struct mlx4_icm_table qp_table;
704 struct mlx4_icm_table auxc_table;
705 struct mlx4_icm_table altc_table;
706 struct mlx4_icm_table rdmarc_table;
707 struct mlx4_icm_table cmpt_table;
708};
709
710struct mlx4_mcg_table {
711 struct mutex mutex;
712 struct mlx4_bitmap bitmap;
713 struct mlx4_icm_table table;
714};
715
716struct mlx4_catas_err {
717 u32 __iomem *map;
718 struct timer_list timer;
719 struct list_head list;
720};
721
722#define MLX4_MAX_MAC_NUM 128
723#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
724
725struct mlx4_mac_table {
726 __be64 entries[MLX4_MAX_MAC_NUM];
727 int refs[MLX4_MAX_MAC_NUM];
728 struct mutex mutex;
729 int total;
730 int max;
731};
732
733#define MLX4_ROCE_GID_ENTRY_SIZE 16
734
735struct mlx4_roce_gid_entry {
736 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
737};
738
739struct mlx4_roce_gid_table {
740 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS];
741 struct mutex mutex;
742};
743
744#define MLX4_MAX_VLAN_NUM 128
745#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
746
747struct mlx4_vlan_table {
748 __be32 entries[MLX4_MAX_VLAN_NUM];
749 int refs[MLX4_MAX_VLAN_NUM];
750 struct mutex mutex;
751 int total;
752 int max;
753};
754
755#define SET_PORT_GEN_ALL_VALID 0x7
756#define SET_PORT_PROMISC_SHIFT 31
757#define SET_PORT_MC_PROMISC_SHIFT 30
758
759enum {
760 MCAST_DIRECT_ONLY = 0,
761 MCAST_DIRECT = 1,
762 MCAST_DEFAULT = 2
763};
764
765
766struct mlx4_set_port_general_context {
767 u16 reserved1;
768 u8 v_ignore_fcs;
769 u8 flags;
770 u8 ignore_fcs;
771 u8 reserved2;
772 __be16 mtu;
773 u8 pptx;
774 u8 pfctx;
775 u16 reserved3;
776 u8 pprx;
777 u8 pfcrx;
778 u16 reserved4;
779};
780
781struct mlx4_set_port_rqp_calc_context {
782 __be32 base_qpn;
783 u8 rererved;
784 u8 n_mac;
785 u8 n_vlan;
786 u8 n_prio;
787 u8 reserved2[3];
788 u8 mac_miss;
789 u8 intra_no_vlan;
790 u8 no_vlan;
791 u8 intra_vlan_miss;
792 u8 vlan_miss;
793 u8 reserved3[3];
794 u8 no_vlan_prio;
795 __be32 promisc;
796 __be32 mcast;
797};
798
799struct mlx4_port_info {
800 struct mlx4_dev *dev;
801 int port;
802 char dev_name[16];
803 struct device_attribute port_attr;
804 enum mlx4_port_type tmp_type;
805 char dev_mtu_name[16];
806 struct device_attribute port_mtu_attr;
807 struct mlx4_mac_table mac_table;
808 struct mlx4_vlan_table vlan_table;
809 struct mlx4_roce_gid_table gid_table;
810 int base_qpn;
811};
812
813struct mlx4_sense {
814 struct mlx4_dev *dev;
815 u8 do_sense_port[MLX4_MAX_PORTS + 1];
816 u8 sense_allowed[MLX4_MAX_PORTS + 1];
817 struct delayed_work sense_poll;
818};
819
820struct mlx4_msix_ctl {
821 u64 pool_bm;
822 struct mutex pool_lock;
823};
824
825struct mlx4_steer {
826 struct list_head promisc_qps[MLX4_NUM_STEERS];
827 struct list_head steer_entries[MLX4_NUM_STEERS];
828};
829
830enum {
831 MLX4_PCI_DEV_IS_VF = 1 << 0,
832 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
833};
834
835enum {
836 MLX4_NO_RR = 0,
837 MLX4_USE_RR = 1,
838};
839
840struct mlx4_priv {
841 struct mlx4_dev dev;
842
843 struct list_head dev_list;
844 struct list_head ctx_list;
845 spinlock_t ctx_lock;
846
847 int pci_dev_data;
848 int removed;
849
850 struct list_head pgdir_list;
851 struct mutex pgdir_mutex;
852
853 struct mlx4_fw fw;
854 struct mlx4_cmd cmd;
855 struct mlx4_mfunc mfunc;
856
857 struct mlx4_bitmap pd_bitmap;
858 struct mlx4_bitmap xrcd_bitmap;
859 struct mlx4_uar_table uar_table;
860 struct mlx4_mr_table mr_table;
861 struct mlx4_cq_table cq_table;
862 struct mlx4_eq_table eq_table;
863 struct mlx4_srq_table srq_table;
864 struct mlx4_qp_table qp_table;
865 struct mlx4_mcg_table mcg_table;
866 struct mlx4_bitmap counters_bitmap;
867
868 struct mlx4_catas_err catas_err;
869
870 void __iomem *clr_base;
871
872 struct mlx4_uar driver_uar;
873 void __iomem *kar;
874 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
875 struct mlx4_sense sense;
876 struct mutex port_mutex;
877 struct mlx4_msix_ctl msix_ctl;
878 struct mlx4_steer *steer;
879 struct list_head bf_list;
880 struct mutex bf_mutex;
881 struct io_mapping *bf_mapping;
882 void __iomem *clock_mapping;
883 int reserved_mtts;
884 int fs_hash_mode;
885 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
886 struct mlx4_port_map v2p;
887 struct mutex bond_mutex;
888 __be64 slave_node_guids[MLX4_MFUNC_MAX];
889
890 atomic_t opreq_count;
891 struct work_struct opreq_task;
892};
893
894static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
895{
896 return container_of(dev, struct mlx4_priv, dev);
897}
898
899#define MLX4_SENSE_RANGE (HZ * 3)
900
901extern struct workqueue_struct *mlx4_wq;
902
903u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
904void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
905u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
906 int align, u32 skip_mask);
907void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
908 int use_rr);
909u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
910int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
911 u32 reserved_bot, u32 resetrved_top);
912void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
913
914int mlx4_reset(struct mlx4_dev *dev);
915
916int mlx4_alloc_eq_table(struct mlx4_dev *dev);
917void mlx4_free_eq_table(struct mlx4_dev *dev);
918
919int mlx4_init_pd_table(struct mlx4_dev *dev);
920int mlx4_init_xrcd_table(struct mlx4_dev *dev);
921int mlx4_init_uar_table(struct mlx4_dev *dev);
922int mlx4_init_mr_table(struct mlx4_dev *dev);
923int mlx4_init_eq_table(struct mlx4_dev *dev);
924int mlx4_init_cq_table(struct mlx4_dev *dev);
925int mlx4_init_qp_table(struct mlx4_dev *dev);
926int mlx4_init_srq_table(struct mlx4_dev *dev);
927int mlx4_init_mcg_table(struct mlx4_dev *dev);
928
929void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
930void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
931void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
932void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
933void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
934void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
935void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
936void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
937void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
938int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
939void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
940int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
941void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
942int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
943void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
944int __mlx4_mpt_reserve(struct mlx4_dev *dev);
945void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
946int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
947void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
948u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
949void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
950
951int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
952 struct mlx4_vhcr *vhcr,
953 struct mlx4_cmd_mailbox *inbox,
954 struct mlx4_cmd_mailbox *outbox,
955 struct mlx4_cmd_info *cmd);
956int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
957 struct mlx4_vhcr *vhcr,
958 struct mlx4_cmd_mailbox *inbox,
959 struct mlx4_cmd_mailbox *outbox,
960 struct mlx4_cmd_info *cmd);
961int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
962 struct mlx4_vhcr *vhcr,
963 struct mlx4_cmd_mailbox *inbox,
964 struct mlx4_cmd_mailbox *outbox,
965 struct mlx4_cmd_info *cmd);
966int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
967 struct mlx4_vhcr *vhcr,
968 struct mlx4_cmd_mailbox *inbox,
969 struct mlx4_cmd_mailbox *outbox,
970 struct mlx4_cmd_info *cmd);
971int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
972 struct mlx4_vhcr *vhcr,
973 struct mlx4_cmd_mailbox *inbox,
974 struct mlx4_cmd_mailbox *outbox,
975 struct mlx4_cmd_info *cmd);
976int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
977 struct mlx4_vhcr *vhcr,
978 struct mlx4_cmd_mailbox *inbox,
979 struct mlx4_cmd_mailbox *outbox,
980 struct mlx4_cmd_info *cmd);
981int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
982 struct mlx4_vhcr *vhcr,
983 struct mlx4_cmd_mailbox *inbox,
984 struct mlx4_cmd_mailbox *outbox,
985 struct mlx4_cmd_info *cmd);
986int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
987 struct mlx4_vhcr *vhcr,
988 struct mlx4_cmd_mailbox *inbox,
989 struct mlx4_cmd_mailbox *outbox,
990 struct mlx4_cmd_info *cmd);
991int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
992 int *base, u8 flags);
993void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
994int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
995void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
996int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
997 int start_index, int npages, u64 *page_list);
998int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
999void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1000int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1001void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1002
1003void mlx4_start_catas_poll(struct mlx4_dev *dev);
1004void mlx4_stop_catas_poll(struct mlx4_dev *dev);
1005int mlx4_catas_init(struct mlx4_dev *dev);
1006void mlx4_catas_end(struct mlx4_dev *dev);
1007int mlx4_restart_one(struct pci_dev *pdev);
1008int mlx4_register_device(struct mlx4_dev *dev);
1009void mlx4_unregister_device(struct mlx4_dev *dev);
1010void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1011 unsigned long param);
1012
1013struct mlx4_dev_cap;
1014struct mlx4_init_hca_param;
1015
1016u64 mlx4_make_profile(struct mlx4_dev *dev,
1017 struct mlx4_profile *request,
1018 struct mlx4_dev_cap *dev_cap,
1019 struct mlx4_init_hca_param *init_hca);
1020void mlx4_master_comm_channel(struct work_struct *work);
1021void mlx4_gen_slave_eqe(struct work_struct *work);
1022void mlx4_master_handle_slave_flr(struct work_struct *work);
1023
1024int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1025 struct mlx4_vhcr *vhcr,
1026 struct mlx4_cmd_mailbox *inbox,
1027 struct mlx4_cmd_mailbox *outbox,
1028 struct mlx4_cmd_info *cmd);
1029int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1030 struct mlx4_vhcr *vhcr,
1031 struct mlx4_cmd_mailbox *inbox,
1032 struct mlx4_cmd_mailbox *outbox,
1033 struct mlx4_cmd_info *cmd);
1034int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1035 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1036 struct mlx4_cmd_mailbox *outbox,
1037 struct mlx4_cmd_info *cmd);
1038int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1039 struct mlx4_vhcr *vhcr,
1040 struct mlx4_cmd_mailbox *inbox,
1041 struct mlx4_cmd_mailbox *outbox,
1042 struct mlx4_cmd_info *cmd);
1043int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1044 struct mlx4_vhcr *vhcr,
1045 struct mlx4_cmd_mailbox *inbox,
1046 struct mlx4_cmd_mailbox *outbox,
1047 struct mlx4_cmd_info *cmd);
1048int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1049 struct mlx4_vhcr *vhcr,
1050 struct mlx4_cmd_mailbox *inbox,
1051 struct mlx4_cmd_mailbox *outbox,
1052 struct mlx4_cmd_info *cmd);
1053int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1054 struct mlx4_vhcr *vhcr,
1055 struct mlx4_cmd_mailbox *inbox,
1056 struct mlx4_cmd_mailbox *outbox,
1057 struct mlx4_cmd_info *cmd);
1058int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1059 struct mlx4_vhcr *vhcr,
1060 struct mlx4_cmd_mailbox *inbox,
1061 struct mlx4_cmd_mailbox *outbox,
1062 struct mlx4_cmd_info *cmd);
1063int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1064 struct mlx4_vhcr *vhcr,
1065 struct mlx4_cmd_mailbox *inbox,
1066 struct mlx4_cmd_mailbox *outbox,
1067 struct mlx4_cmd_info *cmd);
1068int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1069 struct mlx4_vhcr *vhcr,
1070 struct mlx4_cmd_mailbox *inbox,
1071 struct mlx4_cmd_mailbox *outbox,
1072 struct mlx4_cmd_info *cmd);
1073int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1074 struct mlx4_vhcr *vhcr,
1075 struct mlx4_cmd_mailbox *inbox,
1076 struct mlx4_cmd_mailbox *outbox,
1077 struct mlx4_cmd_info *cmd);
1078int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1079 struct mlx4_vhcr *vhcr,
1080 struct mlx4_cmd_mailbox *inbox,
1081 struct mlx4_cmd_mailbox *outbox,
1082 struct mlx4_cmd_info *cmd);
1083int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1084 struct mlx4_vhcr *vhcr,
1085 struct mlx4_cmd_mailbox *inbox,
1086 struct mlx4_cmd_mailbox *outbox,
1087 struct mlx4_cmd_info *cmd);
1088int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1089 struct mlx4_vhcr *vhcr,
1090 struct mlx4_cmd_mailbox *inbox,
1091 struct mlx4_cmd_mailbox *outbox,
1092 struct mlx4_cmd_info *cmd);
1093int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1094 struct mlx4_vhcr *vhcr,
1095 struct mlx4_cmd_mailbox *inbox,
1096 struct mlx4_cmd_mailbox *outbox,
1097 struct mlx4_cmd_info *cmd);
1098int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1099 struct mlx4_vhcr *vhcr,
1100 struct mlx4_cmd_mailbox *inbox,
1101 struct mlx4_cmd_mailbox *outbox,
1102 struct mlx4_cmd_info *cmd);
1103int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1104 struct mlx4_vhcr *vhcr,
1105 struct mlx4_cmd_mailbox *inbox,
1106 struct mlx4_cmd_mailbox *outbox,
1107 struct mlx4_cmd_info *cmd);
1108int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1109 struct mlx4_vhcr *vhcr,
1110 struct mlx4_cmd_mailbox *inbox,
1111 struct mlx4_cmd_mailbox *outbox,
1112 struct mlx4_cmd_info *cmd);
1113int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1114 struct mlx4_vhcr *vhcr,
1115 struct mlx4_cmd_mailbox *inbox,
1116 struct mlx4_cmd_mailbox *outbox,
1117 struct mlx4_cmd_info *cmd);
1118int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1119 struct mlx4_vhcr *vhcr,
1120 struct mlx4_cmd_mailbox *inbox,
1121 struct mlx4_cmd_mailbox *outbox,
1122 struct mlx4_cmd_info *cmd);
1123int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1124 struct mlx4_vhcr *vhcr,
1125 struct mlx4_cmd_mailbox *inbox,
1126 struct mlx4_cmd_mailbox *outbox,
1127 struct mlx4_cmd_info *cmd);
1128int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1129 struct mlx4_vhcr *vhcr,
1130 struct mlx4_cmd_mailbox *inbox,
1131 struct mlx4_cmd_mailbox *outbox,
1132 struct mlx4_cmd_info *cmd);
1133int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1134 struct mlx4_vhcr *vhcr,
1135 struct mlx4_cmd_mailbox *inbox,
1136 struct mlx4_cmd_mailbox *outbox,
1137 struct mlx4_cmd_info *cmd);
1138int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1139 struct mlx4_vhcr *vhcr,
1140 struct mlx4_cmd_mailbox *inbox,
1141 struct mlx4_cmd_mailbox *outbox,
1142 struct mlx4_cmd_info *cmd);
1143int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1144 struct mlx4_vhcr *vhcr,
1145 struct mlx4_cmd_mailbox *inbox,
1146 struct mlx4_cmd_mailbox *outbox,
1147 struct mlx4_cmd_info *cmd);
1148int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1149 struct mlx4_vhcr *vhcr,
1150 struct mlx4_cmd_mailbox *inbox,
1151 struct mlx4_cmd_mailbox *outbox,
1152 struct mlx4_cmd_info *cmd);
1153int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1154 struct mlx4_vhcr *vhcr,
1155 struct mlx4_cmd_mailbox *inbox,
1156 struct mlx4_cmd_mailbox *outbox,
1157 struct mlx4_cmd_info *cmd);
1158
1159int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1160
1161enum {
1162 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1163 MLX4_CMD_CLEANUP_POOL = 1UL << 1,
1164 MLX4_CMD_CLEANUP_HCR = 1UL << 2,
1165 MLX4_CMD_CLEANUP_VHCR = 1UL << 3,
1166 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1167};
1168
1169int mlx4_cmd_init(struct mlx4_dev *dev);
1170void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1171int mlx4_multi_func_init(struct mlx4_dev *dev);
1172int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev);
1173void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1174void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1175int mlx4_cmd_use_events(struct mlx4_dev *dev);
1176void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1177
1178int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1179 u16 op, unsigned long timeout);
1180
1181void mlx4_cq_tasklet_cb(unsigned long data);
1182void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1183void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1184
1185void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1186
1187void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1188
1189void mlx4_enter_error_state(struct mlx4_dev_persistent *persist);
1190
1191int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1192 enum mlx4_port_type *type);
1193void mlx4_do_sense_ports(struct mlx4_dev *dev,
1194 enum mlx4_port_type *stype,
1195 enum mlx4_port_type *defaults);
1196void mlx4_start_sense(struct mlx4_dev *dev);
1197void mlx4_stop_sense(struct mlx4_dev *dev);
1198void mlx4_sense_init(struct mlx4_dev *dev);
1199int mlx4_check_port_params(struct mlx4_dev *dev,
1200 enum mlx4_port_type *port_type);
1201int mlx4_change_port_types(struct mlx4_dev *dev,
1202 enum mlx4_port_type *port_types);
1203
1204void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1205void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1206void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1207 struct mlx4_roce_gid_table *table);
1208void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1209int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1210
1211int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1212
1213int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1214 enum mlx4_resource resource_type,
1215 u64 resource_id, int *slave);
1216void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1217void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1218int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1219
1220void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1221 enum mlx4_res_tracker_free_type type);
1222
1223int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1224 struct mlx4_vhcr *vhcr,
1225 struct mlx4_cmd_mailbox *inbox,
1226 struct mlx4_cmd_mailbox *outbox,
1227 struct mlx4_cmd_info *cmd);
1228int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1229 struct mlx4_vhcr *vhcr,
1230 struct mlx4_cmd_mailbox *inbox,
1231 struct mlx4_cmd_mailbox *outbox,
1232 struct mlx4_cmd_info *cmd);
1233int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1234 struct mlx4_vhcr *vhcr,
1235 struct mlx4_cmd_mailbox *inbox,
1236 struct mlx4_cmd_mailbox *outbox,
1237 struct mlx4_cmd_info *cmd);
1238int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1239 struct mlx4_vhcr *vhcr,
1240 struct mlx4_cmd_mailbox *inbox,
1241 struct mlx4_cmd_mailbox *outbox,
1242 struct mlx4_cmd_info *cmd);
1243int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1244 struct mlx4_vhcr *vhcr,
1245 struct mlx4_cmd_mailbox *inbox,
1246 struct mlx4_cmd_mailbox *outbox,
1247 struct mlx4_cmd_info *cmd);
1248int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1249 struct mlx4_vhcr *vhcr,
1250 struct mlx4_cmd_mailbox *inbox,
1251 struct mlx4_cmd_mailbox *outbox,
1252 struct mlx4_cmd_info *cmd);
1253int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1254
1255int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1256 int *gid_tbl_len, int *pkey_tbl_len);
1257
1258int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1259 struct mlx4_vhcr *vhcr,
1260 struct mlx4_cmd_mailbox *inbox,
1261 struct mlx4_cmd_mailbox *outbox,
1262 struct mlx4_cmd_info *cmd);
1263
1264int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1265 struct mlx4_vhcr *vhcr,
1266 struct mlx4_cmd_mailbox *inbox,
1267 struct mlx4_cmd_mailbox *outbox,
1268 struct mlx4_cmd_info *cmd);
1269
1270int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1271 struct mlx4_vhcr *vhcr,
1272 struct mlx4_cmd_mailbox *inbox,
1273 struct mlx4_cmd_mailbox *outbox,
1274 struct mlx4_cmd_info *cmd);
1275int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1276 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1277int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1278 int block_mcast_loopback, enum mlx4_protocol prot,
1279 enum mlx4_steer_type steer);
1280int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1281 u8 gid[16], u8 port,
1282 int block_mcast_loopback,
1283 enum mlx4_protocol prot, u64 *reg_id);
1284int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1285 struct mlx4_vhcr *vhcr,
1286 struct mlx4_cmd_mailbox *inbox,
1287 struct mlx4_cmd_mailbox *outbox,
1288 struct mlx4_cmd_info *cmd);
1289int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1290 struct mlx4_vhcr *vhcr,
1291 struct mlx4_cmd_mailbox *inbox,
1292 struct mlx4_cmd_mailbox *outbox,
1293 struct mlx4_cmd_info *cmd);
1294int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1295 int port, void *buf);
1296int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1297 struct mlx4_cmd_mailbox *outbox);
1298int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1299 struct mlx4_vhcr *vhcr,
1300 struct mlx4_cmd_mailbox *inbox,
1301 struct mlx4_cmd_mailbox *outbox,
1302 struct mlx4_cmd_info *cmd);
1303int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1304 struct mlx4_vhcr *vhcr,
1305 struct mlx4_cmd_mailbox *inbox,
1306 struct mlx4_cmd_mailbox *outbox,
1307 struct mlx4_cmd_info *cmd);
1308int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1309 struct mlx4_vhcr *vhcr,
1310 struct mlx4_cmd_mailbox *inbox,
1311 struct mlx4_cmd_mailbox *outbox,
1312 struct mlx4_cmd_info *cmd);
1313int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1314 struct mlx4_vhcr *vhcr,
1315 struct mlx4_cmd_mailbox *inbox,
1316 struct mlx4_cmd_mailbox *outbox,
1317 struct mlx4_cmd_info *cmd);
1318int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1319 struct mlx4_vhcr *vhcr,
1320 struct mlx4_cmd_mailbox *inbox,
1321 struct mlx4_cmd_mailbox *outbox,
1322 struct mlx4_cmd_info *cmd);
1323int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1324 struct mlx4_vhcr *vhcr,
1325 struct mlx4_cmd_mailbox *inbox,
1326 struct mlx4_cmd_mailbox *outbox,
1327 struct mlx4_cmd_info *cmd);
1328
1329int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1330int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1331
1332static inline void set_param_l(u64 *arg, u32 val)
1333{
1334 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1335}
1336
1337static inline void set_param_h(u64 *arg, u32 val)
1338{
1339 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1340}
1341
1342static inline u32 get_param_l(u64 *arg)
1343{
1344 return (u32) (*arg & 0xffffffff);
1345}
1346
1347static inline u32 get_param_h(u64 *arg)
1348{
1349 return (u32)(*arg >> 32);
1350}
1351
1352static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1353{
1354 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1355}
1356
1357#define NOT_MASKED_PD_BITS 17
1358
1359void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1360
1361void mlx4_init_quotas(struct mlx4_dev *dev);
1362
1363int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1364
1365int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1366int mlx4_config_mad_demux(struct mlx4_dev *dev);
1367int mlx4_do_bond(struct mlx4_dev *dev, bool enable);
1368
1369enum mlx4_zone_flags {
1370 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0,
1371 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1,
1372 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2,
1373 MLX4_ZONE_USE_RR = 1UL << 3,
1374};
1375
1376enum mlx4_zone_alloc_flags {
1377
1378
1379
1380
1381
1382 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0,
1383};
1384
1385struct mlx4_zone_allocator;
1386
1387
1388struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1400 struct mlx4_bitmap *bitmap,
1401 u32 flags,
1402 int priority,
1403 int offset,
1404 u32 *puid);
1405
1406
1407int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1408
1409
1410
1411
1412void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1413
1414
1415
1416
1417
1418
1419u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1420 int align, u32 skip_mask, u32 *puid);
1421
1422
1423
1424
1425u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1426 u32 uid, u32 obj, u32 count);
1427
1428
1429
1430
1431
1432u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1433
1434
1435struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);
1436
1437#endif
1438