linux/drivers/net/ethernet/silan/sc92031.c
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   1/*  Silan SC92031 PCI Fast Ethernet Adapter driver
   2 *
   3 *  Based on vendor drivers:
   4 *  Silan Fast Ethernet Netcard Driver:
   5 *    MODULE_AUTHOR ("gaoyonghong");
   6 *    MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
   7 *    MODULE_LICENSE("GPL");
   8 *  8139D Fast Ethernet driver:
   9 *    (C) 2002 by gaoyonghong
  10 *    MODULE_AUTHOR ("gaoyonghong");
  11 *    MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
  12 *    MODULE_LICENSE("GPL");
  13 *  Both are almost identical and seem to be based on pci-skeleton.c
  14 *
  15 *  Rewritten for 2.6 by Cesar Eduardo Barros
  16 *
  17 *  A datasheet for this chip can be found at
  18 *  http://www.silan.com.cn/english/product/pdf/SC92031AY.pdf 
  19 */
  20
  21/* Note about set_mac_address: I don't know how to change the hardware
  22 * matching, so you need to enable IFF_PROMISC when using it.
  23 */
  24
  25#include <linux/interrupt.h>
  26#include <linux/module.h>
  27#include <linux/kernel.h>
  28#include <linux/delay.h>
  29#include <linux/pci.h>
  30#include <linux/dma-mapping.h>
  31#include <linux/netdevice.h>
  32#include <linux/etherdevice.h>
  33#include <linux/ethtool.h>
  34#include <linux/mii.h>
  35#include <linux/crc32.h>
  36
  37#include <asm/irq.h>
  38
  39#define SC92031_NAME "sc92031"
  40
  41/* BAR 0 is MMIO, BAR 1 is PIO */
  42#define SC92031_USE_PIO 0
  43
  44/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
  45static int multicast_filter_limit = 64;
  46module_param(multicast_filter_limit, int, 0);
  47MODULE_PARM_DESC(multicast_filter_limit,
  48        "Maximum number of filtered multicast addresses");
  49
  50static int media;
  51module_param(media, int, 0);
  52MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
  53        " 0x01 = 10M half, 0x02 = 10M full,"
  54        " 0x04 = 100M half, 0x08 = 100M full)");
  55
  56/* Size of the in-memory receive ring. */
  57#define  RX_BUF_LEN_IDX  3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
  58#define  RX_BUF_LEN     (8192 << RX_BUF_LEN_IDX)
  59
  60/* Number of Tx descriptor registers. */
  61#define  NUM_TX_DESC       4
  62
  63/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
  64#define  MAX_ETH_FRAME_SIZE       1536
  65
  66/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
  67#define  TX_BUF_SIZE       MAX_ETH_FRAME_SIZE
  68#define  TX_BUF_TOT_LEN    (TX_BUF_SIZE * NUM_TX_DESC)
  69
  70/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
  71#define  RX_FIFO_THRESH    7     /* Rx buffer level before first PCI xfer.  */
  72
  73/* Time in jiffies before concluding the transmitter is hung. */
  74#define  TX_TIMEOUT     (4*HZ)
  75
  76#define  SILAN_STATS_NUM    2    /* number of ETHTOOL_GSTATS */
  77
  78/* media options */
  79#define  AUTOSELECT    0x00
  80#define  M10_HALF      0x01
  81#define  M10_FULL      0x02
  82#define  M100_HALF     0x04
  83#define  M100_FULL     0x08
  84
  85 /* Symbolic offsets to registers. */
  86enum  silan_registers {
  87   Config0    = 0x00,         // Config0
  88   Config1    = 0x04,         // Config1
  89   RxBufWPtr  = 0x08,         // Rx buffer writer poiter
  90   IntrStatus = 0x0C,         // Interrupt status
  91   IntrMask   = 0x10,         // Interrupt mask
  92   RxbufAddr  = 0x14,         // Rx buffer start address
  93   RxBufRPtr  = 0x18,         // Rx buffer read pointer
  94   Txstatusall = 0x1C,        // Transmit status of all descriptors
  95   TxStatus0  = 0x20,         // Transmit status (Four 32bit registers).
  96   TxAddr0    = 0x30,         // Tx descriptors (also four 32bit).
  97   RxConfig   = 0x40,         // Rx configuration
  98   MAC0       = 0x44,         // Ethernet hardware address.
  99   MAR0       = 0x4C,         // Multicast filter.
 100   RxStatus0  = 0x54,         // Rx status
 101   TxConfig   = 0x5C,         // Tx configuration
 102   PhyCtrl    = 0x60,         // physical control
 103   FlowCtrlConfig = 0x64,     // flow control
 104   Miicmd0    = 0x68,         // Mii command0 register
 105   Miicmd1    = 0x6C,         // Mii command1 register
 106   Miistatus  = 0x70,         // Mii status register
 107   Timercnt   = 0x74,         // Timer counter register
 108   TimerIntr  = 0x78,         // Timer interrupt register
 109   PMConfig   = 0x7C,         // Power Manager configuration
 110   CRC0       = 0x80,         // Power Manager CRC ( Two 32bit regisers)
 111   Wakeup0    = 0x88,         // power Manager wakeup( Eight 64bit regiser)
 112   LSBCRC0    = 0xC8,         // power Manager LSBCRC(Two 32bit regiser)
 113   TestD0     = 0xD0,
 114   TestD4     = 0xD4,
 115   TestD8     = 0xD8,
 116};
 117
 118#define MII_JAB             16
 119#define MII_OutputStatus    24
 120
 121#define PHY_16_JAB_ENB      0x1000
 122#define PHY_16_PORT_ENB     0x1
 123
 124enum IntrStatusBits {
 125   LinkFail       = 0x80000000,
 126   LinkOK         = 0x40000000,
 127   TimeOut        = 0x20000000,
 128   RxOverflow     = 0x0040,
 129   RxOK           = 0x0020,
 130   TxOK           = 0x0001,
 131   IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
 132};
 133
 134enum TxStatusBits {
 135   TxCarrierLost = 0x20000000,
 136   TxAborted     = 0x10000000,
 137   TxOutOfWindow = 0x08000000,
 138   TxNccShift    = 22,
 139   EarlyTxThresShift = 16,
 140   TxStatOK      = 0x8000,
 141   TxUnderrun    = 0x4000,
 142   TxOwn         = 0x2000,
 143};
 144
 145enum RxStatusBits {
 146   RxStatesOK   = 0x80000,
 147   RxBadAlign   = 0x40000,
 148   RxHugeFrame  = 0x20000,
 149   RxSmallFrame = 0x10000,
 150   RxCRCOK      = 0x8000,
 151   RxCrlFrame   = 0x4000,
 152   Rx_Broadcast = 0x2000,
 153   Rx_Multicast = 0x1000,
 154   RxAddrMatch  = 0x0800,
 155   MiiErr       = 0x0400,
 156};
 157
 158enum RxConfigBits {
 159   RxFullDx    = 0x80000000,
 160   RxEnb       = 0x40000000,
 161   RxSmall     = 0x20000000,
 162   RxHuge      = 0x10000000,
 163   RxErr       = 0x08000000,
 164   RxAllphys   = 0x04000000,
 165   RxMulticast = 0x02000000,
 166   RxBroadcast = 0x01000000,
 167   RxLoopBack  = (1 << 23) | (1 << 22),
 168   LowThresholdShift  = 12,
 169   HighThresholdShift = 2,
 170};
 171
 172enum TxConfigBits {
 173   TxFullDx       = 0x80000000,
 174   TxEnb          = 0x40000000,
 175   TxEnbPad       = 0x20000000,
 176   TxEnbHuge      = 0x10000000,
 177   TxEnbFCS       = 0x08000000,
 178   TxNoBackOff    = 0x04000000,
 179   TxEnbPrem      = 0x02000000,
 180   TxCareLostCrs  = 0x1000000,
 181   TxExdCollNum   = 0xf00000,
 182   TxDataRate     = 0x80000,
 183};
 184
 185enum PhyCtrlconfigbits {
 186   PhyCtrlAne         = 0x80000000,
 187   PhyCtrlSpd100      = 0x40000000,
 188   PhyCtrlSpd10       = 0x20000000,
 189   PhyCtrlPhyBaseAddr = 0x1f000000,
 190   PhyCtrlDux         = 0x800000,
 191   PhyCtrlReset       = 0x400000,
 192};
 193
 194enum FlowCtrlConfigBits {
 195   FlowCtrlFullDX = 0x80000000,
 196   FlowCtrlEnb    = 0x40000000,
 197};
 198
 199enum Config0Bits {
 200   Cfg0_Reset  = 0x80000000,
 201   Cfg0_Anaoff = 0x40000000,
 202   Cfg0_LDPS   = 0x20000000,
 203};
 204
 205enum Config1Bits {
 206   Cfg1_EarlyRx = 1 << 31,
 207   Cfg1_EarlyTx = 1 << 30,
 208
 209   //rx buffer size
 210   Cfg1_Rcv8K   = 0x0,
 211   Cfg1_Rcv16K  = 0x1,
 212   Cfg1_Rcv32K  = 0x3,
 213   Cfg1_Rcv64K  = 0x7,
 214   Cfg1_Rcv128K = 0xf,
 215};
 216
 217enum MiiCmd0Bits {
 218   Mii_Divider = 0x20000000,
 219   Mii_WRITE   = 0x400000,
 220   Mii_READ    = 0x200000,
 221   Mii_SCAN    = 0x100000,
 222   Mii_Tamod   = 0x80000,
 223   Mii_Drvmod  = 0x40000,
 224   Mii_mdc     = 0x20000,
 225   Mii_mdoen   = 0x10000,
 226   Mii_mdo     = 0x8000,
 227   Mii_mdi     = 0x4000,
 228};
 229
 230enum MiiStatusBits {
 231    Mii_StatusBusy = 0x80000000,
 232};
 233
 234enum PMConfigBits {
 235   PM_Enable  = 1 << 31,
 236   PM_LongWF  = 1 << 30,
 237   PM_Magic   = 1 << 29,
 238   PM_LANWake = 1 << 28,
 239   PM_LWPTN   = (1 << 27 | 1<< 26),
 240   PM_LinkUp  = 1 << 25,
 241   PM_WakeUp  = 1 << 24,
 242};
 243
 244/* Locking rules:
 245 * priv->lock protects most of the fields of priv and most of the
 246 * hardware registers. It does not have to protect against softirqs
 247 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
 248 * it also does not need to be used in ->open and ->stop while the
 249 * device interrupts are off.
 250 * Not having to protect against softirqs is very useful due to heavy
 251 * use of mdelay() at _sc92031_reset.
 252 * Functions prefixed with _sc92031_ must be called with the lock held;
 253 * functions prefixed with sc92031_ must be called without the lock held.
 254 * Use mmiowb() before unlocking if the hardware was written to.
 255 */
 256
 257/* Locking rules for the interrupt:
 258 * - the interrupt and the tasklet never run at the same time
 259 * - neither run between sc92031_disable_interrupts and
 260 *   sc92031_enable_interrupt
 261 */
 262
 263struct sc92031_priv {
 264        spinlock_t              lock;
 265        /* iomap.h cookie */
 266        void __iomem            *port_base;
 267        /* pci device structure */
 268        struct pci_dev          *pdev;
 269        /* tasklet */
 270        struct tasklet_struct   tasklet;
 271
 272        /* CPU address of rx ring */
 273        void                    *rx_ring;
 274        /* PCI address of rx ring */
 275        dma_addr_t              rx_ring_dma_addr;
 276        /* PCI address of rx ring read pointer */
 277        dma_addr_t              rx_ring_tail;
 278
 279        /* tx ring write index */
 280        unsigned                tx_head;
 281        /* tx ring read index */
 282        unsigned                tx_tail;
 283        /* CPU address of tx bounce buffer */
 284        void                    *tx_bufs;
 285        /* PCI address of tx bounce buffer */
 286        dma_addr_t              tx_bufs_dma_addr;
 287
 288        /* copies of some hardware registers */
 289        u32                     intr_status;
 290        atomic_t                intr_mask;
 291        u32                     rx_config;
 292        u32                     tx_config;
 293        u32                     pm_config;
 294
 295        /* copy of some flags from dev->flags */
 296        unsigned int            mc_flags;
 297
 298        /* for ETHTOOL_GSTATS */
 299        u64                     tx_timeouts;
 300        u64                     rx_loss;
 301
 302        /* for dev->get_stats */
 303        long                    rx_value;
 304};
 305
 306/* I don't know which registers can be safely read; however, I can guess
 307 * MAC0 is one of them. */
 308static inline void _sc92031_dummy_read(void __iomem *port_base)
 309{
 310        ioread32(port_base + MAC0);
 311}
 312
 313static u32 _sc92031_mii_wait(void __iomem *port_base)
 314{
 315        u32 mii_status;
 316
 317        do {
 318                udelay(10);
 319                mii_status = ioread32(port_base + Miistatus);
 320        } while (mii_status & Mii_StatusBusy);
 321
 322        return mii_status;
 323}
 324
 325static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
 326{
 327        iowrite32(Mii_Divider, port_base + Miicmd0);
 328
 329        _sc92031_mii_wait(port_base);
 330
 331        iowrite32(cmd1, port_base + Miicmd1);
 332        iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
 333
 334        return _sc92031_mii_wait(port_base);
 335}
 336
 337static void _sc92031_mii_scan(void __iomem *port_base)
 338{
 339        _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
 340}
 341
 342static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
 343{
 344        return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
 345}
 346
 347static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
 348{
 349        _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
 350}
 351
 352static void sc92031_disable_interrupts(struct net_device *dev)
 353{
 354        struct sc92031_priv *priv = netdev_priv(dev);
 355        void __iomem *port_base = priv->port_base;
 356
 357        /* tell the tasklet/interrupt not to enable interrupts */
 358        atomic_set(&priv->intr_mask, 0);
 359        wmb();
 360
 361        /* stop interrupts */
 362        iowrite32(0, port_base + IntrMask);
 363        _sc92031_dummy_read(port_base);
 364        mmiowb();
 365
 366        /* wait for any concurrent interrupt/tasklet to finish */
 367        synchronize_irq(priv->pdev->irq);
 368        tasklet_disable(&priv->tasklet);
 369}
 370
 371static void sc92031_enable_interrupts(struct net_device *dev)
 372{
 373        struct sc92031_priv *priv = netdev_priv(dev);
 374        void __iomem *port_base = priv->port_base;
 375
 376        tasklet_enable(&priv->tasklet);
 377
 378        atomic_set(&priv->intr_mask, IntrBits);
 379        wmb();
 380
 381        iowrite32(IntrBits, port_base + IntrMask);
 382        mmiowb();
 383}
 384
 385static void _sc92031_disable_tx_rx(struct net_device *dev)
 386{
 387        struct sc92031_priv *priv = netdev_priv(dev);
 388        void __iomem *port_base = priv->port_base;
 389
 390        priv->rx_config &= ~RxEnb;
 391        priv->tx_config &= ~TxEnb;
 392        iowrite32(priv->rx_config, port_base + RxConfig);
 393        iowrite32(priv->tx_config, port_base + TxConfig);
 394}
 395
 396static void _sc92031_enable_tx_rx(struct net_device *dev)
 397{
 398        struct sc92031_priv *priv = netdev_priv(dev);
 399        void __iomem *port_base = priv->port_base;
 400
 401        priv->rx_config |= RxEnb;
 402        priv->tx_config |= TxEnb;
 403        iowrite32(priv->rx_config, port_base + RxConfig);
 404        iowrite32(priv->tx_config, port_base + TxConfig);
 405}
 406
 407static void _sc92031_tx_clear(struct net_device *dev)
 408{
 409        struct sc92031_priv *priv = netdev_priv(dev);
 410
 411        while (priv->tx_head - priv->tx_tail > 0) {
 412                priv->tx_tail++;
 413                dev->stats.tx_dropped++;
 414        }
 415        priv->tx_head = priv->tx_tail = 0;
 416}
 417
 418static void _sc92031_set_mar(struct net_device *dev)
 419{
 420        struct sc92031_priv *priv = netdev_priv(dev);
 421        void __iomem *port_base = priv->port_base;
 422        u32 mar0 = 0, mar1 = 0;
 423
 424        if ((dev->flags & IFF_PROMISC) ||
 425            netdev_mc_count(dev) > multicast_filter_limit ||
 426            (dev->flags & IFF_ALLMULTI))
 427                mar0 = mar1 = 0xffffffff;
 428        else if (dev->flags & IFF_MULTICAST) {
 429                struct netdev_hw_addr *ha;
 430
 431                netdev_for_each_mc_addr(ha, dev) {
 432                        u32 crc;
 433                        unsigned bit = 0;
 434
 435                        crc = ~ether_crc(ETH_ALEN, ha->addr);
 436                        crc >>= 24;
 437
 438                        if (crc & 0x01) bit |= 0x02;
 439                        if (crc & 0x02) bit |= 0x01;
 440                        if (crc & 0x10) bit |= 0x20;
 441                        if (crc & 0x20) bit |= 0x10;
 442                        if (crc & 0x40) bit |= 0x08;
 443                        if (crc & 0x80) bit |= 0x04;
 444
 445                        if (bit > 31)
 446                                mar0 |= 0x1 << (bit - 32);
 447                        else
 448                                mar1 |= 0x1 << bit;
 449                }
 450        }
 451
 452        iowrite32(mar0, port_base + MAR0);
 453        iowrite32(mar1, port_base + MAR0 + 4);
 454}
 455
 456static void _sc92031_set_rx_config(struct net_device *dev)
 457{
 458        struct sc92031_priv *priv = netdev_priv(dev);
 459        void __iomem *port_base = priv->port_base;
 460        unsigned int old_mc_flags;
 461        u32 rx_config_bits = 0;
 462
 463        old_mc_flags = priv->mc_flags;
 464
 465        if (dev->flags & IFF_PROMISC)
 466                rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
 467                                | RxMulticast | RxAllphys;
 468
 469        if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
 470                rx_config_bits |= RxMulticast;
 471
 472        if (dev->flags & IFF_BROADCAST)
 473                rx_config_bits |= RxBroadcast;
 474
 475        priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
 476                        | RxMulticast | RxAllphys);
 477        priv->rx_config |= rx_config_bits;
 478
 479        priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
 480                        | IFF_MULTICAST | IFF_BROADCAST);
 481
 482        if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
 483                iowrite32(priv->rx_config, port_base + RxConfig);
 484}
 485
 486static bool _sc92031_check_media(struct net_device *dev)
 487{
 488        struct sc92031_priv *priv = netdev_priv(dev);
 489        void __iomem *port_base = priv->port_base;
 490        u16 bmsr;
 491
 492        bmsr = _sc92031_mii_read(port_base, MII_BMSR);
 493        rmb();
 494        if (bmsr & BMSR_LSTATUS) {
 495                bool speed_100, duplex_full;
 496                u32 flow_ctrl_config = 0;
 497                u16 output_status = _sc92031_mii_read(port_base,
 498                                MII_OutputStatus);
 499                _sc92031_mii_scan(port_base);
 500
 501                speed_100 = output_status & 0x2;
 502                duplex_full = output_status & 0x4;
 503
 504                /* Initial Tx/Rx configuration */
 505                priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
 506                priv->tx_config = 0x48800000;
 507
 508                /* NOTE: vendor driver had dead code here to enable tx padding */
 509
 510                if (!speed_100)
 511                        priv->tx_config |= 0x80000;
 512
 513                // configure rx mode
 514                _sc92031_set_rx_config(dev);
 515
 516                if (duplex_full) {
 517                        priv->rx_config |= RxFullDx;
 518                        priv->tx_config |= TxFullDx;
 519                        flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
 520                } else {
 521                        priv->rx_config &= ~RxFullDx;
 522                        priv->tx_config &= ~TxFullDx;
 523                }
 524
 525                _sc92031_set_mar(dev);
 526                _sc92031_set_rx_config(dev);
 527                _sc92031_enable_tx_rx(dev);
 528                iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
 529
 530                netif_carrier_on(dev);
 531
 532                if (printk_ratelimit())
 533                        printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
 534                                dev->name,
 535                                speed_100 ? "100" : "10",
 536                                duplex_full ? "full" : "half");
 537                return true;
 538        } else {
 539                _sc92031_mii_scan(port_base);
 540
 541                netif_carrier_off(dev);
 542
 543                _sc92031_disable_tx_rx(dev);
 544
 545                if (printk_ratelimit())
 546                        printk(KERN_INFO "%s: link down\n", dev->name);
 547                return false;
 548        }
 549}
 550
 551static void _sc92031_phy_reset(struct net_device *dev)
 552{
 553        struct sc92031_priv *priv = netdev_priv(dev);
 554        void __iomem *port_base = priv->port_base;
 555        u32 phy_ctrl;
 556
 557        phy_ctrl = ioread32(port_base + PhyCtrl);
 558        phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
 559        phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
 560
 561        switch (media) {
 562        default:
 563        case AUTOSELECT:
 564                phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
 565                break;
 566        case M10_HALF:
 567                phy_ctrl |= PhyCtrlSpd10;
 568                break;
 569        case M10_FULL:
 570                phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
 571                break;
 572        case M100_HALF:
 573                phy_ctrl |= PhyCtrlSpd100;
 574                break;
 575        case M100_FULL:
 576                phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
 577                break;
 578        }
 579
 580        iowrite32(phy_ctrl, port_base + PhyCtrl);
 581        mdelay(10);
 582
 583        phy_ctrl &= ~PhyCtrlReset;
 584        iowrite32(phy_ctrl, port_base + PhyCtrl);
 585        mdelay(1);
 586
 587        _sc92031_mii_write(port_base, MII_JAB,
 588                        PHY_16_JAB_ENB | PHY_16_PORT_ENB);
 589        _sc92031_mii_scan(port_base);
 590
 591        netif_carrier_off(dev);
 592        netif_stop_queue(dev);
 593}
 594
 595static void _sc92031_reset(struct net_device *dev)
 596{
 597        struct sc92031_priv *priv = netdev_priv(dev);
 598        void __iomem *port_base = priv->port_base;
 599
 600        /* disable PM */
 601        iowrite32(0, port_base + PMConfig);
 602
 603        /* soft reset the chip */
 604        iowrite32(Cfg0_Reset, port_base + Config0);
 605        mdelay(200);
 606
 607        iowrite32(0, port_base + Config0);
 608        mdelay(10);
 609
 610        /* disable interrupts */
 611        iowrite32(0, port_base + IntrMask);
 612
 613        /* clear multicast address */
 614        iowrite32(0, port_base + MAR0);
 615        iowrite32(0, port_base + MAR0 + 4);
 616
 617        /* init rx ring */
 618        iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
 619        priv->rx_ring_tail = priv->rx_ring_dma_addr;
 620
 621        /* init tx ring */
 622        _sc92031_tx_clear(dev);
 623
 624        /* clear old register values */
 625        priv->intr_status = 0;
 626        atomic_set(&priv->intr_mask, 0);
 627        priv->rx_config = 0;
 628        priv->tx_config = 0;
 629        priv->mc_flags = 0;
 630
 631        /* configure rx buffer size */
 632        /* NOTE: vendor driver had dead code here to enable early tx/rx */
 633        iowrite32(Cfg1_Rcv64K, port_base + Config1);
 634
 635        _sc92031_phy_reset(dev);
 636        _sc92031_check_media(dev);
 637
 638        /* calculate rx fifo overflow */
 639        priv->rx_value = 0;
 640
 641        /* enable PM */
 642        iowrite32(priv->pm_config, port_base + PMConfig);
 643
 644        /* clear intr register */
 645        ioread32(port_base + IntrStatus);
 646}
 647
 648static void _sc92031_tx_tasklet(struct net_device *dev)
 649{
 650        struct sc92031_priv *priv = netdev_priv(dev);
 651        void __iomem *port_base = priv->port_base;
 652
 653        unsigned old_tx_tail;
 654        unsigned entry;
 655        u32 tx_status;
 656
 657        old_tx_tail = priv->tx_tail;
 658        while (priv->tx_head - priv->tx_tail > 0) {
 659                entry = priv->tx_tail % NUM_TX_DESC;
 660                tx_status = ioread32(port_base + TxStatus0 + entry * 4);
 661
 662                if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
 663                        break;
 664
 665                priv->tx_tail++;
 666
 667                if (tx_status & TxStatOK) {
 668                        dev->stats.tx_bytes += tx_status & 0x1fff;
 669                        dev->stats.tx_packets++;
 670                        /* Note: TxCarrierLost is always asserted at 100mbps. */
 671                        dev->stats.collisions += (tx_status >> 22) & 0xf;
 672                }
 673
 674                if (tx_status & (TxOutOfWindow | TxAborted)) {
 675                        dev->stats.tx_errors++;
 676
 677                        if (tx_status & TxAborted)
 678                                dev->stats.tx_aborted_errors++;
 679
 680                        if (tx_status & TxCarrierLost)
 681                                dev->stats.tx_carrier_errors++;
 682
 683                        if (tx_status & TxOutOfWindow)
 684                                dev->stats.tx_window_errors++;
 685                }
 686
 687                if (tx_status & TxUnderrun)
 688                        dev->stats.tx_fifo_errors++;
 689        }
 690
 691        if (priv->tx_tail != old_tx_tail)
 692                if (netif_queue_stopped(dev))
 693                        netif_wake_queue(dev);
 694}
 695
 696static void _sc92031_rx_tasklet_error(struct net_device *dev,
 697                                      u32 rx_status, unsigned rx_size)
 698{
 699        if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
 700                dev->stats.rx_errors++;
 701                dev->stats.rx_length_errors++;
 702        }
 703
 704        if (!(rx_status & RxStatesOK)) {
 705                dev->stats.rx_errors++;
 706
 707                if (rx_status & (RxHugeFrame | RxSmallFrame))
 708                        dev->stats.rx_length_errors++;
 709
 710                if (rx_status & RxBadAlign)
 711                        dev->stats.rx_frame_errors++;
 712
 713                if (!(rx_status & RxCRCOK))
 714                        dev->stats.rx_crc_errors++;
 715        } else {
 716                struct sc92031_priv *priv = netdev_priv(dev);
 717                priv->rx_loss++;
 718        }
 719}
 720
 721static void _sc92031_rx_tasklet(struct net_device *dev)
 722{
 723        struct sc92031_priv *priv = netdev_priv(dev);
 724        void __iomem *port_base = priv->port_base;
 725
 726        dma_addr_t rx_ring_head;
 727        unsigned rx_len;
 728        unsigned rx_ring_offset;
 729        void *rx_ring = priv->rx_ring;
 730
 731        rx_ring_head = ioread32(port_base + RxBufWPtr);
 732        rmb();
 733
 734        /* rx_ring_head is only 17 bits in the RxBufWPtr register.
 735         * we need to change it to 32 bits physical address
 736         */
 737        rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
 738        rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
 739        if (rx_ring_head < priv->rx_ring_dma_addr)
 740                rx_ring_head += RX_BUF_LEN;
 741
 742        if (rx_ring_head >= priv->rx_ring_tail)
 743                rx_len = rx_ring_head - priv->rx_ring_tail;
 744        else
 745                rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
 746
 747        if (!rx_len)
 748                return;
 749
 750        if (unlikely(rx_len > RX_BUF_LEN)) {
 751                if (printk_ratelimit())
 752                        printk(KERN_ERR "%s: rx packets length > rx buffer\n",
 753                                        dev->name);
 754                return;
 755        }
 756
 757        rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
 758
 759        while (rx_len) {
 760                u32 rx_status;
 761                unsigned rx_size, rx_size_align, pkt_size;
 762                struct sk_buff *skb;
 763
 764                rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
 765                rmb();
 766
 767                rx_size = rx_status >> 20;
 768                rx_size_align = (rx_size + 3) & ~3;     // for 4 bytes aligned
 769                pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
 770
 771                rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
 772
 773                if (unlikely(rx_status == 0 ||
 774                             rx_size > (MAX_ETH_FRAME_SIZE + 4) ||
 775                             rx_size < 16 ||
 776                             !(rx_status & RxStatesOK))) {
 777                        _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
 778                        break;
 779                }
 780
 781                if (unlikely(rx_size_align + 4 > rx_len)) {
 782                        if (printk_ratelimit())
 783                                printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
 784                        break;
 785                }
 786
 787                rx_len -= rx_size_align + 4;
 788
 789                skb = netdev_alloc_skb_ip_align(dev, pkt_size);
 790                if (unlikely(!skb)) {
 791                        if (printk_ratelimit())
 792                                printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
 793                                                dev->name, pkt_size);
 794                        goto next;
 795                }
 796
 797                if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
 798                        memcpy(skb_put(skb, RX_BUF_LEN - rx_ring_offset),
 799                                rx_ring + rx_ring_offset, RX_BUF_LEN - rx_ring_offset);
 800                        memcpy(skb_put(skb, pkt_size - (RX_BUF_LEN - rx_ring_offset)),
 801                                rx_ring, pkt_size - (RX_BUF_LEN - rx_ring_offset));
 802                } else {
 803                        memcpy(skb_put(skb, pkt_size), rx_ring + rx_ring_offset, pkt_size);
 804                }
 805
 806                skb->protocol = eth_type_trans(skb, dev);
 807                netif_rx(skb);
 808
 809                dev->stats.rx_bytes += pkt_size;
 810                dev->stats.rx_packets++;
 811
 812                if (rx_status & Rx_Multicast)
 813                        dev->stats.multicast++;
 814
 815        next:
 816                rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
 817        }
 818        mb();
 819
 820        priv->rx_ring_tail = rx_ring_head;
 821        iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
 822}
 823
 824static void _sc92031_link_tasklet(struct net_device *dev)
 825{
 826        if (_sc92031_check_media(dev))
 827                netif_wake_queue(dev);
 828        else {
 829                netif_stop_queue(dev);
 830                dev->stats.tx_carrier_errors++;
 831        }
 832}
 833
 834static void sc92031_tasklet(unsigned long data)
 835{
 836        struct net_device *dev = (struct net_device *)data;
 837        struct sc92031_priv *priv = netdev_priv(dev);
 838        void __iomem *port_base = priv->port_base;
 839        u32 intr_status, intr_mask;
 840
 841        intr_status = priv->intr_status;
 842
 843        spin_lock(&priv->lock);
 844
 845        if (unlikely(!netif_running(dev)))
 846                goto out;
 847
 848        if (intr_status & TxOK)
 849                _sc92031_tx_tasklet(dev);
 850
 851        if (intr_status & RxOK)
 852                _sc92031_rx_tasklet(dev);
 853
 854        if (intr_status & RxOverflow)
 855                dev->stats.rx_errors++;
 856
 857        if (intr_status & TimeOut) {
 858                dev->stats.rx_errors++;
 859                dev->stats.rx_length_errors++;
 860        }
 861
 862        if (intr_status & (LinkFail | LinkOK))
 863                _sc92031_link_tasklet(dev);
 864
 865out:
 866        intr_mask = atomic_read(&priv->intr_mask);
 867        rmb();
 868
 869        iowrite32(intr_mask, port_base + IntrMask);
 870        mmiowb();
 871
 872        spin_unlock(&priv->lock);
 873}
 874
 875static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
 876{
 877        struct net_device *dev = dev_id;
 878        struct sc92031_priv *priv = netdev_priv(dev);
 879        void __iomem *port_base = priv->port_base;
 880        u32 intr_status, intr_mask;
 881
 882        /* mask interrupts before clearing IntrStatus */
 883        iowrite32(0, port_base + IntrMask);
 884        _sc92031_dummy_read(port_base);
 885
 886        intr_status = ioread32(port_base + IntrStatus);
 887        if (unlikely(intr_status == 0xffffffff))
 888                return IRQ_NONE;        // hardware has gone missing
 889
 890        intr_status &= IntrBits;
 891        if (!intr_status)
 892                goto out_none;
 893
 894        priv->intr_status = intr_status;
 895        tasklet_schedule(&priv->tasklet);
 896
 897        return IRQ_HANDLED;
 898
 899out_none:
 900        intr_mask = atomic_read(&priv->intr_mask);
 901        rmb();
 902
 903        iowrite32(intr_mask, port_base + IntrMask);
 904        mmiowb();
 905
 906        return IRQ_NONE;
 907}
 908
 909static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
 910{
 911        struct sc92031_priv *priv = netdev_priv(dev);
 912        void __iomem *port_base = priv->port_base;
 913
 914        // FIXME I do not understand what is this trying to do.
 915        if (netif_running(dev)) {
 916                int temp;
 917
 918                spin_lock_bh(&priv->lock);
 919
 920                /* Update the error count. */
 921                temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
 922
 923                if (temp == 0xffff) {
 924                        priv->rx_value += temp;
 925                        dev->stats.rx_fifo_errors = priv->rx_value;
 926                } else
 927                        dev->stats.rx_fifo_errors = temp + priv->rx_value;
 928
 929                spin_unlock_bh(&priv->lock);
 930        }
 931
 932        return &dev->stats;
 933}
 934
 935static netdev_tx_t sc92031_start_xmit(struct sk_buff *skb,
 936                                      struct net_device *dev)
 937{
 938        struct sc92031_priv *priv = netdev_priv(dev);
 939        void __iomem *port_base = priv->port_base;
 940        unsigned len;
 941        unsigned entry;
 942        u32 tx_status;
 943
 944        if (unlikely(skb->len > TX_BUF_SIZE)) {
 945                dev->stats.tx_dropped++;
 946                goto out;
 947        }
 948
 949        spin_lock(&priv->lock);
 950
 951        if (unlikely(!netif_carrier_ok(dev))) {
 952                dev->stats.tx_dropped++;
 953                goto out_unlock;
 954        }
 955
 956        BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
 957
 958        entry = priv->tx_head++ % NUM_TX_DESC;
 959
 960        skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
 961
 962        len = skb->len;
 963        if (len < ETH_ZLEN) {
 964                memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
 965                                0, ETH_ZLEN - len);
 966                len = ETH_ZLEN;
 967        }
 968
 969        wmb();
 970
 971        if (len < 100)
 972                tx_status = len;
 973        else if (len < 300)
 974                tx_status = 0x30000 | len;
 975        else
 976                tx_status = 0x50000 | len;
 977
 978        iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
 979                        port_base + TxAddr0 + entry * 4);
 980        iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
 981        mmiowb();
 982
 983        if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
 984                netif_stop_queue(dev);
 985
 986out_unlock:
 987        spin_unlock(&priv->lock);
 988
 989out:
 990        dev_consume_skb_any(skb);
 991
 992        return NETDEV_TX_OK;
 993}
 994
 995static int sc92031_open(struct net_device *dev)
 996{
 997        int err;
 998        struct sc92031_priv *priv = netdev_priv(dev);
 999        struct pci_dev *pdev = priv->pdev;
1000
1001        priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
1002                        &priv->rx_ring_dma_addr);
1003        if (unlikely(!priv->rx_ring)) {
1004                err = -ENOMEM;
1005                goto out_alloc_rx_ring;
1006        }
1007
1008        priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
1009                        &priv->tx_bufs_dma_addr);
1010        if (unlikely(!priv->tx_bufs)) {
1011                err = -ENOMEM;
1012                goto out_alloc_tx_bufs;
1013        }
1014        priv->tx_head = priv->tx_tail = 0;
1015
1016        err = request_irq(pdev->irq, sc92031_interrupt,
1017                        IRQF_SHARED, dev->name, dev);
1018        if (unlikely(err < 0))
1019                goto out_request_irq;
1020
1021        priv->pm_config = 0;
1022
1023        /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1024        spin_lock_bh(&priv->lock);
1025
1026        _sc92031_reset(dev);
1027        mmiowb();
1028
1029        spin_unlock_bh(&priv->lock);
1030        sc92031_enable_interrupts(dev);
1031
1032        if (netif_carrier_ok(dev))
1033                netif_start_queue(dev);
1034        else
1035                netif_tx_disable(dev);
1036
1037        return 0;
1038
1039out_request_irq:
1040        pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1041                        priv->tx_bufs_dma_addr);
1042out_alloc_tx_bufs:
1043        pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1044                        priv->rx_ring_dma_addr);
1045out_alloc_rx_ring:
1046        return err;
1047}
1048
1049static int sc92031_stop(struct net_device *dev)
1050{
1051        struct sc92031_priv *priv = netdev_priv(dev);
1052        struct pci_dev *pdev = priv->pdev;
1053
1054        netif_tx_disable(dev);
1055
1056        /* Disable interrupts, stop Tx and Rx. */
1057        sc92031_disable_interrupts(dev);
1058
1059        spin_lock_bh(&priv->lock);
1060
1061        _sc92031_disable_tx_rx(dev);
1062        _sc92031_tx_clear(dev);
1063        mmiowb();
1064
1065        spin_unlock_bh(&priv->lock);
1066
1067        free_irq(pdev->irq, dev);
1068        pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1069                        priv->tx_bufs_dma_addr);
1070        pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1071                        priv->rx_ring_dma_addr);
1072
1073        return 0;
1074}
1075
1076static void sc92031_set_multicast_list(struct net_device *dev)
1077{
1078        struct sc92031_priv *priv = netdev_priv(dev);
1079
1080        spin_lock_bh(&priv->lock);
1081
1082        _sc92031_set_mar(dev);
1083        _sc92031_set_rx_config(dev);
1084        mmiowb();
1085
1086        spin_unlock_bh(&priv->lock);
1087}
1088
1089static void sc92031_tx_timeout(struct net_device *dev)
1090{
1091        struct sc92031_priv *priv = netdev_priv(dev);
1092
1093        /* Disable interrupts by clearing the interrupt mask.*/
1094        sc92031_disable_interrupts(dev);
1095
1096        spin_lock(&priv->lock);
1097
1098        priv->tx_timeouts++;
1099
1100        _sc92031_reset(dev);
1101        mmiowb();
1102
1103        spin_unlock(&priv->lock);
1104
1105        /* enable interrupts */
1106        sc92031_enable_interrupts(dev);
1107
1108        if (netif_carrier_ok(dev))
1109                netif_wake_queue(dev);
1110}
1111
1112#ifdef CONFIG_NET_POLL_CONTROLLER
1113static void sc92031_poll_controller(struct net_device *dev)
1114{
1115        struct sc92031_priv *priv = netdev_priv(dev);
1116        const int irq = priv->pdev->irq;
1117
1118        disable_irq(irq);
1119        if (sc92031_interrupt(irq, dev) != IRQ_NONE)
1120                sc92031_tasklet((unsigned long)dev);
1121        enable_irq(irq);
1122}
1123#endif
1124
1125static int sc92031_ethtool_get_settings(struct net_device *dev,
1126                struct ethtool_cmd *cmd)
1127{
1128        struct sc92031_priv *priv = netdev_priv(dev);
1129        void __iomem *port_base = priv->port_base;
1130        u8 phy_address;
1131        u32 phy_ctrl;
1132        u16 output_status;
1133
1134        spin_lock_bh(&priv->lock);
1135
1136        phy_address = ioread32(port_base + Miicmd1) >> 27;
1137        phy_ctrl = ioread32(port_base + PhyCtrl);
1138
1139        output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1140        _sc92031_mii_scan(port_base);
1141        mmiowb();
1142
1143        spin_unlock_bh(&priv->lock);
1144
1145        cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1146                        | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1147                        | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1148
1149        cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
1150
1151        if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1152                        == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1153                cmd->advertising |= ADVERTISED_Autoneg;
1154
1155        if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1156                cmd->advertising |= ADVERTISED_10baseT_Half;
1157
1158        if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1159                        == (PhyCtrlSpd10 | PhyCtrlDux))
1160                cmd->advertising |= ADVERTISED_10baseT_Full;
1161
1162        if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1163                cmd->advertising |= ADVERTISED_100baseT_Half;
1164
1165        if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1166                        == (PhyCtrlSpd100 | PhyCtrlDux))
1167                cmd->advertising |= ADVERTISED_100baseT_Full;
1168
1169        if (phy_ctrl & PhyCtrlAne)
1170                cmd->advertising |= ADVERTISED_Autoneg;
1171
1172        ethtool_cmd_speed_set(cmd,
1173                              (output_status & 0x2) ? SPEED_100 : SPEED_10);
1174        cmd->duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1175        cmd->port = PORT_MII;
1176        cmd->phy_address = phy_address;
1177        cmd->transceiver = XCVR_INTERNAL;
1178        cmd->autoneg = (phy_ctrl & PhyCtrlAne) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1179
1180        return 0;
1181}
1182
1183static int sc92031_ethtool_set_settings(struct net_device *dev,
1184                struct ethtool_cmd *cmd)
1185{
1186        struct sc92031_priv *priv = netdev_priv(dev);
1187        void __iomem *port_base = priv->port_base;
1188        u32 speed = ethtool_cmd_speed(cmd);
1189        u32 phy_ctrl;
1190        u32 old_phy_ctrl;
1191
1192        if (!(speed == SPEED_10 || speed == SPEED_100))
1193                return -EINVAL;
1194        if (!(cmd->duplex == DUPLEX_HALF || cmd->duplex == DUPLEX_FULL))
1195                return -EINVAL;
1196        if (!(cmd->port == PORT_MII))
1197                return -EINVAL;
1198        if (!(cmd->phy_address == 0x1f))
1199                return -EINVAL;
1200        if (!(cmd->transceiver == XCVR_INTERNAL))
1201                return -EINVAL;
1202        if (!(cmd->autoneg == AUTONEG_DISABLE || cmd->autoneg == AUTONEG_ENABLE))
1203                return -EINVAL;
1204
1205        if (cmd->autoneg == AUTONEG_ENABLE) {
1206                if (!(cmd->advertising & (ADVERTISED_Autoneg
1207                                | ADVERTISED_100baseT_Full
1208                                | ADVERTISED_100baseT_Half
1209                                | ADVERTISED_10baseT_Full
1210                                | ADVERTISED_10baseT_Half)))
1211                        return -EINVAL;
1212
1213                phy_ctrl = PhyCtrlAne;
1214
1215                // FIXME: I'm not sure what the original code was trying to do
1216                if (cmd->advertising & ADVERTISED_Autoneg)
1217                        phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1218                if (cmd->advertising & ADVERTISED_100baseT_Full)
1219                        phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1220                if (cmd->advertising & ADVERTISED_100baseT_Half)
1221                        phy_ctrl |= PhyCtrlSpd100;
1222                if (cmd->advertising & ADVERTISED_10baseT_Full)
1223                        phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1224                if (cmd->advertising & ADVERTISED_10baseT_Half)
1225                        phy_ctrl |= PhyCtrlSpd10;
1226        } else {
1227                // FIXME: Whole branch guessed
1228                phy_ctrl = 0;
1229
1230                if (speed == SPEED_10)
1231                        phy_ctrl |= PhyCtrlSpd10;
1232                else /* cmd->speed == SPEED_100 */
1233                        phy_ctrl |= PhyCtrlSpd100;
1234
1235                if (cmd->duplex == DUPLEX_FULL)
1236                        phy_ctrl |= PhyCtrlDux;
1237        }
1238
1239        spin_lock_bh(&priv->lock);
1240
1241        old_phy_ctrl = ioread32(port_base + PhyCtrl);
1242        phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1243                        | PhyCtrlSpd100 | PhyCtrlSpd10);
1244        if (phy_ctrl != old_phy_ctrl)
1245                iowrite32(phy_ctrl, port_base + PhyCtrl);
1246
1247        spin_unlock_bh(&priv->lock);
1248
1249        return 0;
1250}
1251
1252static void sc92031_ethtool_get_wol(struct net_device *dev,
1253                struct ethtool_wolinfo *wolinfo)
1254{
1255        struct sc92031_priv *priv = netdev_priv(dev);
1256        void __iomem *port_base = priv->port_base;
1257        u32 pm_config;
1258
1259        spin_lock_bh(&priv->lock);
1260        pm_config = ioread32(port_base + PMConfig);
1261        spin_unlock_bh(&priv->lock);
1262
1263        // FIXME: Guessed
1264        wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1265                        | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1266        wolinfo->wolopts = 0;
1267
1268        if (pm_config & PM_LinkUp)
1269                wolinfo->wolopts |= WAKE_PHY;
1270
1271        if (pm_config & PM_Magic)
1272                wolinfo->wolopts |= WAKE_MAGIC;
1273
1274        if (pm_config & PM_WakeUp)
1275                // FIXME: Guessed
1276                wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1277}
1278
1279static int sc92031_ethtool_set_wol(struct net_device *dev,
1280                struct ethtool_wolinfo *wolinfo)
1281{
1282        struct sc92031_priv *priv = netdev_priv(dev);
1283        void __iomem *port_base = priv->port_base;
1284        u32 pm_config;
1285
1286        spin_lock_bh(&priv->lock);
1287
1288        pm_config = ioread32(port_base + PMConfig)
1289                        & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1290
1291        if (wolinfo->wolopts & WAKE_PHY)
1292                pm_config |= PM_LinkUp;
1293
1294        if (wolinfo->wolopts & WAKE_MAGIC)
1295                pm_config |= PM_Magic;
1296
1297        // FIXME: Guessed
1298        if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1299                pm_config |= PM_WakeUp;
1300
1301        priv->pm_config = pm_config;
1302        iowrite32(pm_config, port_base + PMConfig);
1303        mmiowb();
1304
1305        spin_unlock_bh(&priv->lock);
1306
1307        return 0;
1308}
1309
1310static int sc92031_ethtool_nway_reset(struct net_device *dev)
1311{
1312        int err = 0;
1313        struct sc92031_priv *priv = netdev_priv(dev);
1314        void __iomem *port_base = priv->port_base;
1315        u16 bmcr;
1316
1317        spin_lock_bh(&priv->lock);
1318
1319        bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1320        if (!(bmcr & BMCR_ANENABLE)) {
1321                err = -EINVAL;
1322                goto out;
1323        }
1324
1325        _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1326
1327out:
1328        _sc92031_mii_scan(port_base);
1329        mmiowb();
1330
1331        spin_unlock_bh(&priv->lock);
1332
1333        return err;
1334}
1335
1336static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1337        "tx_timeout",
1338        "rx_loss",
1339};
1340
1341static void sc92031_ethtool_get_strings(struct net_device *dev,
1342                u32 stringset, u8 *data)
1343{
1344        if (stringset == ETH_SS_STATS)
1345                memcpy(data, sc92031_ethtool_stats_strings,
1346                                SILAN_STATS_NUM * ETH_GSTRING_LEN);
1347}
1348
1349static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
1350{
1351        switch (sset) {
1352        case ETH_SS_STATS:
1353                return SILAN_STATS_NUM;
1354        default:
1355                return -EOPNOTSUPP;
1356        }
1357}
1358
1359static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1360                struct ethtool_stats *stats, u64 *data)
1361{
1362        struct sc92031_priv *priv = netdev_priv(dev);
1363
1364        spin_lock_bh(&priv->lock);
1365        data[0] = priv->tx_timeouts;
1366        data[1] = priv->rx_loss;
1367        spin_unlock_bh(&priv->lock);
1368}
1369
1370static const struct ethtool_ops sc92031_ethtool_ops = {
1371        .get_settings           = sc92031_ethtool_get_settings,
1372        .set_settings           = sc92031_ethtool_set_settings,
1373        .get_wol                = sc92031_ethtool_get_wol,
1374        .set_wol                = sc92031_ethtool_set_wol,
1375        .nway_reset             = sc92031_ethtool_nway_reset,
1376        .get_link               = ethtool_op_get_link,
1377        .get_strings            = sc92031_ethtool_get_strings,
1378        .get_sset_count         = sc92031_ethtool_get_sset_count,
1379        .get_ethtool_stats      = sc92031_ethtool_get_ethtool_stats,
1380};
1381
1382
1383static const struct net_device_ops sc92031_netdev_ops = {
1384        .ndo_get_stats          = sc92031_get_stats,
1385        .ndo_start_xmit         = sc92031_start_xmit,
1386        .ndo_open               = sc92031_open,
1387        .ndo_stop               = sc92031_stop,
1388        .ndo_set_rx_mode        = sc92031_set_multicast_list,
1389        .ndo_change_mtu         = eth_change_mtu,
1390        .ndo_validate_addr      = eth_validate_addr,
1391        .ndo_set_mac_address    = eth_mac_addr,
1392        .ndo_tx_timeout         = sc92031_tx_timeout,
1393#ifdef CONFIG_NET_POLL_CONTROLLER
1394        .ndo_poll_controller    = sc92031_poll_controller,
1395#endif
1396};
1397
1398static int sc92031_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1399{
1400        int err;
1401        void __iomem* port_base;
1402        struct net_device *dev;
1403        struct sc92031_priv *priv;
1404        u32 mac0, mac1;
1405
1406        err = pci_enable_device(pdev);
1407        if (unlikely(err < 0))
1408                goto out_enable_device;
1409
1410        pci_set_master(pdev);
1411
1412        err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1413        if (unlikely(err < 0))
1414                goto out_set_dma_mask;
1415
1416        err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1417        if (unlikely(err < 0))
1418                goto out_set_dma_mask;
1419
1420        err = pci_request_regions(pdev, SC92031_NAME);
1421        if (unlikely(err < 0))
1422                goto out_request_regions;
1423
1424        port_base = pci_iomap(pdev, SC92031_USE_PIO, 0);
1425        if (unlikely(!port_base)) {
1426                err = -EIO;
1427                goto out_iomap;
1428        }
1429
1430        dev = alloc_etherdev(sizeof(struct sc92031_priv));
1431        if (unlikely(!dev)) {
1432                err = -ENOMEM;
1433                goto out_alloc_etherdev;
1434        }
1435
1436        pci_set_drvdata(pdev, dev);
1437        SET_NETDEV_DEV(dev, &pdev->dev);
1438
1439        /* faked with skb_copy_and_csum_dev */
1440        dev->features = NETIF_F_SG | NETIF_F_HIGHDMA |
1441                NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1442
1443        dev->netdev_ops         = &sc92031_netdev_ops;
1444        dev->watchdog_timeo     = TX_TIMEOUT;
1445        dev->ethtool_ops        = &sc92031_ethtool_ops;
1446
1447        priv = netdev_priv(dev);
1448        spin_lock_init(&priv->lock);
1449        priv->port_base = port_base;
1450        priv->pdev = pdev;
1451        tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
1452        /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1453         * sc92031_open will work correctly */
1454        tasklet_disable_nosync(&priv->tasklet);
1455
1456        /* PCI PM Wakeup */
1457        iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1458
1459        mac0 = ioread32(port_base + MAC0);
1460        mac1 = ioread32(port_base + MAC0 + 4);
1461        dev->dev_addr[0] = mac0 >> 24;
1462        dev->dev_addr[1] = mac0 >> 16;
1463        dev->dev_addr[2] = mac0 >> 8;
1464        dev->dev_addr[3] = mac0;
1465        dev->dev_addr[4] = mac1 >> 8;
1466        dev->dev_addr[5] = mac1;
1467
1468        err = register_netdev(dev);
1469        if (err < 0)
1470                goto out_register_netdev;
1471
1472        printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name,
1473               (long)pci_resource_start(pdev, SC92031_USE_PIO), dev->dev_addr,
1474               pdev->irq);
1475
1476        return 0;
1477
1478out_register_netdev:
1479        free_netdev(dev);
1480out_alloc_etherdev:
1481        pci_iounmap(pdev, port_base);
1482out_iomap:
1483        pci_release_regions(pdev);
1484out_request_regions:
1485out_set_dma_mask:
1486        pci_disable_device(pdev);
1487out_enable_device:
1488        return err;
1489}
1490
1491static void sc92031_remove(struct pci_dev *pdev)
1492{
1493        struct net_device *dev = pci_get_drvdata(pdev);
1494        struct sc92031_priv *priv = netdev_priv(dev);
1495        void __iomem* port_base = priv->port_base;
1496
1497        unregister_netdev(dev);
1498        free_netdev(dev);
1499        pci_iounmap(pdev, port_base);
1500        pci_release_regions(pdev);
1501        pci_disable_device(pdev);
1502}
1503
1504static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1505{
1506        struct net_device *dev = pci_get_drvdata(pdev);
1507        struct sc92031_priv *priv = netdev_priv(dev);
1508
1509        pci_save_state(pdev);
1510
1511        if (!netif_running(dev))
1512                goto out;
1513
1514        netif_device_detach(dev);
1515
1516        /* Disable interrupts, stop Tx and Rx. */
1517        sc92031_disable_interrupts(dev);
1518
1519        spin_lock_bh(&priv->lock);
1520
1521        _sc92031_disable_tx_rx(dev);
1522        _sc92031_tx_clear(dev);
1523        mmiowb();
1524
1525        spin_unlock_bh(&priv->lock);
1526
1527out:
1528        pci_set_power_state(pdev, pci_choose_state(pdev, state));
1529
1530        return 0;
1531}
1532
1533static int sc92031_resume(struct pci_dev *pdev)
1534{
1535        struct net_device *dev = pci_get_drvdata(pdev);
1536        struct sc92031_priv *priv = netdev_priv(dev);
1537
1538        pci_restore_state(pdev);
1539        pci_set_power_state(pdev, PCI_D0);
1540
1541        if (!netif_running(dev))
1542                goto out;
1543
1544        /* Interrupts already disabled by sc92031_suspend */
1545        spin_lock_bh(&priv->lock);
1546
1547        _sc92031_reset(dev);
1548        mmiowb();
1549
1550        spin_unlock_bh(&priv->lock);
1551        sc92031_enable_interrupts(dev);
1552
1553        netif_device_attach(dev);
1554
1555        if (netif_carrier_ok(dev))
1556                netif_wake_queue(dev);
1557        else
1558                netif_tx_disable(dev);
1559
1560out:
1561        return 0;
1562}
1563
1564static const struct pci_device_id sc92031_pci_device_id_table[] = {
1565        { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x2031) },
1566        { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x8139) },
1567        { PCI_DEVICE(0x1088, 0x2031) },
1568        { 0, }
1569};
1570MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1571
1572static struct pci_driver sc92031_pci_driver = {
1573        .name           = SC92031_NAME,
1574        .id_table       = sc92031_pci_device_id_table,
1575        .probe          = sc92031_probe,
1576        .remove         = sc92031_remove,
1577        .suspend        = sc92031_suspend,
1578        .resume         = sc92031_resume,
1579};
1580
1581module_pci_driver(sc92031_pci_driver);
1582MODULE_LICENSE("GPL");
1583MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1584MODULE_DESCRIPTION("Silan SC92031 PCI Fast Ethernet Adapter driver");
1585