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18#ifndef _CORE_H_
19#define _CORE_H_
20
21#include <linux/completion.h>
22#include <linux/if_ether.h>
23#include <linux/types.h>
24#include <linux/pci.h>
25#include <linux/uuid.h>
26#include <linux/time.h>
27
28#include "htt.h"
29#include "htc.h"
30#include "hw.h"
31#include "targaddrs.h"
32#include "wmi.h"
33#include "../ath.h"
34#include "../regd.h"
35#include "../dfs_pattern_detector.h"
36#include "spectral.h"
37#include "thermal.h"
38
39#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
40#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
41#define WO(_f) ((_f##_OFFSET) >> 2)
42
43#define ATH10K_SCAN_ID 0
44#define WMI_READY_TIMEOUT (5 * HZ)
45#define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
46#define ATH10K_NUM_CHANS 38
47
48
49#define ATH10K_DEFAULT_NOISE_FLOOR -95
50
51#define ATH10K_MAX_NUM_MGMT_PENDING 128
52
53
54#define ATH10K_KICKOUT_THRESHOLD 50
55
56
57
58
59
60
61#define ATH10K_KEEPALIVE_MIN_IDLE 3747
62#define ATH10K_KEEPALIVE_MAX_IDLE 3895
63#define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
64
65struct ath10k;
66
67enum ath10k_bus {
68 ATH10K_BUS_PCI,
69};
70
71static inline const char *ath10k_bus_str(enum ath10k_bus bus)
72{
73 switch (bus) {
74 case ATH10K_BUS_PCI:
75 return "pci";
76 }
77
78 return "unknown";
79}
80
81struct ath10k_skb_cb {
82 dma_addr_t paddr;
83 u8 eid;
84 u8 vdev_id;
85
86 struct {
87 u8 tid;
88 u16 freq;
89 bool is_offchan;
90 struct ath10k_htt_txbuf *txbuf;
91 u32 txbuf_paddr;
92 } __packed htt;
93
94 struct {
95 bool dtim_zero;
96 bool deliver_cab;
97 } bcn;
98} __packed;
99
100struct ath10k_skb_rxcb {
101 dma_addr_t paddr;
102 struct hlist_node hlist;
103};
104
105static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
106{
107 BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
108 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
109 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
110}
111
112static inline struct ath10k_skb_rxcb *ATH10K_SKB_RXCB(struct sk_buff *skb)
113{
114 BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb));
115 return (struct ath10k_skb_rxcb *)skb->cb;
116}
117
118#define ATH10K_RXCB_SKB(rxcb) \
119 container_of((void *)rxcb, struct sk_buff, cb)
120
121static inline u32 host_interest_item_address(u32 item_offset)
122{
123 return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
124}
125
126struct ath10k_bmi {
127 bool done_sent;
128};
129
130struct ath10k_mem_chunk {
131 void *vaddr;
132 dma_addr_t paddr;
133 u32 len;
134 u32 req_id;
135};
136
137struct ath10k_wmi {
138 enum ath10k_fw_wmi_op_version op_version;
139 enum ath10k_htc_ep_id eid;
140 struct completion service_ready;
141 struct completion unified_ready;
142 wait_queue_head_t tx_credits_wq;
143 DECLARE_BITMAP(svc_map, WMI_SERVICE_MAX);
144 struct wmi_cmd_map *cmd;
145 struct wmi_vdev_param_map *vdev_param;
146 struct wmi_pdev_param_map *pdev_param;
147 const struct wmi_ops *ops;
148
149 u32 num_mem_chunks;
150 struct ath10k_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
151};
152
153struct ath10k_fw_stats_peer {
154 struct list_head list;
155
156 u8 peer_macaddr[ETH_ALEN];
157 u32 peer_rssi;
158 u32 peer_tx_rate;
159 u32 peer_rx_rate;
160};
161
162struct ath10k_fw_stats_vdev {
163 struct list_head list;
164
165 u32 vdev_id;
166 u32 beacon_snr;
167 u32 data_snr;
168 u32 num_tx_frames[4];
169 u32 num_rx_frames;
170 u32 num_tx_frames_retries[4];
171 u32 num_tx_frames_failures[4];
172 u32 num_rts_fail;
173 u32 num_rts_success;
174 u32 num_rx_err;
175 u32 num_rx_discard;
176 u32 num_tx_not_acked;
177 u32 tx_rate_history[10];
178 u32 beacon_rssi_history[10];
179};
180
181struct ath10k_fw_stats_pdev {
182 struct list_head list;
183
184
185 s32 ch_noise_floor;
186 u32 tx_frame_count;
187 u32 rx_frame_count;
188 u32 rx_clear_count;
189 u32 cycle_count;
190 u32 phy_err_count;
191 u32 chan_tx_power;
192 u32 ack_rx_bad;
193 u32 rts_bad;
194 u32 rts_good;
195 u32 fcs_bad;
196 u32 no_beacons;
197 u32 mib_int_count;
198
199
200 s32 comp_queued;
201 s32 comp_delivered;
202 s32 msdu_enqued;
203 s32 mpdu_enqued;
204 s32 wmm_drop;
205 s32 local_enqued;
206 s32 local_freed;
207 s32 hw_queued;
208 s32 hw_reaped;
209 s32 underrun;
210 s32 tx_abort;
211 s32 mpdus_requed;
212 u32 tx_ko;
213 u32 data_rc;
214 u32 self_triggers;
215 u32 sw_retry_failure;
216 u32 illgl_rate_phy_err;
217 u32 pdev_cont_xretry;
218 u32 pdev_tx_timeout;
219 u32 pdev_resets;
220 u32 phy_underrun;
221 u32 txop_ovf;
222
223
224 s32 mid_ppdu_route_change;
225 s32 status_rcvd;
226 s32 r0_frags;
227 s32 r1_frags;
228 s32 r2_frags;
229 s32 r3_frags;
230 s32 htt_msdus;
231 s32 htt_mpdus;
232 s32 loc_msdus;
233 s32 loc_mpdus;
234 s32 oversize_amsdu;
235 s32 phy_errs;
236 s32 phy_err_drop;
237 s32 mpdu_errs;
238};
239
240struct ath10k_fw_stats {
241 struct list_head pdevs;
242 struct list_head vdevs;
243 struct list_head peers;
244};
245
246struct ath10k_dfs_stats {
247 u32 phy_errors;
248 u32 pulses_total;
249 u32 pulses_detected;
250 u32 pulses_discarded;
251 u32 radar_detected;
252};
253
254#define ATH10K_MAX_NUM_PEER_IDS (1 << 11)
255
256struct ath10k_peer {
257 struct list_head list;
258 int vdev_id;
259 u8 addr[ETH_ALEN];
260 DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
261
262
263 struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
264};
265
266struct ath10k_sta {
267 struct ath10k_vif *arvif;
268
269
270 u32 changed;
271 u32 bw;
272 u32 nss;
273 u32 smps;
274
275 struct work_struct update_wk;
276
277#ifdef CONFIG_MAC80211_DEBUGFS
278
279 bool aggr_mode;
280#endif
281};
282
283#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)
284
285enum ath10k_beacon_state {
286 ATH10K_BEACON_SCHEDULED = 0,
287 ATH10K_BEACON_SENDING,
288 ATH10K_BEACON_SENT,
289};
290
291struct ath10k_vif {
292 struct list_head list;
293
294 u32 vdev_id;
295 enum wmi_vdev_type vdev_type;
296 enum wmi_vdev_subtype vdev_subtype;
297 u32 beacon_interval;
298 u32 dtim_period;
299 struct sk_buff *beacon;
300
301 enum ath10k_beacon_state beacon_state;
302 void *beacon_buf;
303 dma_addr_t beacon_paddr;
304
305 struct ath10k *ar;
306 struct ieee80211_vif *vif;
307
308 bool is_started;
309 bool is_up;
310 bool spectral_enabled;
311 bool ps;
312 u32 aid;
313 u8 bssid[ETH_ALEN];
314
315 struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
316 s8 def_wep_key_idx;
317
318 u16 tx_seq_no;
319
320 union {
321 struct {
322 u32 uapsd;
323 } sta;
324 struct {
325
326 u8 tim_bitmap[16];
327 u8 tim_len;
328 u32 ssid_len;
329 u8 ssid[IEEE80211_MAX_SSID_LEN];
330 bool hidden_ssid;
331
332 u32 noa_len;
333 u8 *noa_data;
334 } ap;
335 } u;
336
337 u8 fixed_rate;
338 u8 fixed_nss;
339 u8 force_sgi;
340 bool use_cts_prot;
341 int num_legacy_stations;
342 int txpower;
343 struct wmi_wmm_params_all_arg wmm_params;
344};
345
346struct ath10k_vif_iter {
347 u32 vdev_id;
348 struct ath10k_vif *arvif;
349};
350
351
352struct ath10k_fw_crash_data {
353 bool crashed_since_read;
354
355 uuid_le uuid;
356 struct timespec timestamp;
357 __le32 registers[REG_DUMP_COUNT_QCA988X];
358};
359
360struct ath10k_debug {
361 struct dentry *debugfs_phy;
362
363 struct ath10k_fw_stats fw_stats;
364 struct completion fw_stats_complete;
365 bool fw_stats_done;
366
367 unsigned long htt_stats_mask;
368 struct delayed_work htt_stats_dwork;
369 struct ath10k_dfs_stats dfs_stats;
370 struct ath_dfs_pool_stats dfs_pool_stats;
371
372
373 u32 fw_dbglog_mask;
374 u32 fw_dbglog_level;
375 u32 pktlog_filter;
376 u32 reg_addr;
377 u32 nf_cal_period;
378
379 u8 htt_max_amsdu;
380 u8 htt_max_ampdu;
381
382 struct ath10k_fw_crash_data *fw_crash_data;
383};
384
385enum ath10k_state {
386 ATH10K_STATE_OFF = 0,
387 ATH10K_STATE_ON,
388
389
390
391
392
393
394
395
396
397 ATH10K_STATE_RESTARTING,
398 ATH10K_STATE_RESTARTED,
399
400
401
402
403
404 ATH10K_STATE_WEDGED,
405
406
407 ATH10K_STATE_UTF,
408};
409
410enum ath10k_firmware_mode {
411
412 ATH10K_FIRMWARE_MODE_NORMAL,
413
414
415 ATH10K_FIRMWARE_MODE_UTF,
416};
417
418enum ath10k_fw_features {
419
420 ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
421
422
423 ATH10K_FW_FEATURE_WMI_10X = 1,
424
425
426 ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
427
428
429 ATH10K_FW_FEATURE_NO_P2P = 3,
430
431
432
433
434
435 ATH10K_FW_FEATURE_WMI_10_2 = 4,
436
437
438
439
440
441 ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT = 5,
442
443
444 ATH10K_FW_FEATURE_COUNT,
445};
446
447enum ath10k_dev_flags {
448
449 ATH10K_CAC_RUNNING,
450 ATH10K_FLAG_CORE_REGISTERED,
451
452
453
454
455 ATH10K_FLAG_CRASH_FLUSH,
456};
457
458enum ath10k_cal_mode {
459 ATH10K_CAL_MODE_FILE,
460 ATH10K_CAL_MODE_OTP,
461 ATH10K_CAL_MODE_DT,
462};
463
464static inline const char *ath10k_cal_mode_str(enum ath10k_cal_mode mode)
465{
466 switch (mode) {
467 case ATH10K_CAL_MODE_FILE:
468 return "file";
469 case ATH10K_CAL_MODE_OTP:
470 return "otp";
471 case ATH10K_CAL_MODE_DT:
472 return "dt";
473 }
474
475 return "unknown";
476}
477
478enum ath10k_scan_state {
479 ATH10K_SCAN_IDLE,
480 ATH10K_SCAN_STARTING,
481 ATH10K_SCAN_RUNNING,
482 ATH10K_SCAN_ABORTING,
483};
484
485static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state)
486{
487 switch (state) {
488 case ATH10K_SCAN_IDLE:
489 return "idle";
490 case ATH10K_SCAN_STARTING:
491 return "starting";
492 case ATH10K_SCAN_RUNNING:
493 return "running";
494 case ATH10K_SCAN_ABORTING:
495 return "aborting";
496 }
497
498 return "unknown";
499}
500
501struct ath10k {
502 struct ath_common ath_common;
503 struct ieee80211_hw *hw;
504 struct device *dev;
505 u8 mac_addr[ETH_ALEN];
506
507 enum ath10k_hw_rev hw_rev;
508 u32 chip_id;
509 u32 target_version;
510 u8 fw_version_major;
511 u32 fw_version_minor;
512 u16 fw_version_release;
513 u16 fw_version_build;
514 u32 phy_capability;
515 u32 hw_min_tx_power;
516 u32 hw_max_tx_power;
517 u32 ht_cap_info;
518 u32 vht_cap_info;
519 u32 num_rf_chains;
520
521 DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
522
523 bool p2p;
524
525 struct {
526 enum ath10k_bus bus;
527 const struct ath10k_hif_ops *ops;
528 } hif;
529
530 struct completion target_suspend;
531
532 const struct ath10k_hw_regs *regs;
533 struct ath10k_bmi bmi;
534 struct ath10k_wmi wmi;
535 struct ath10k_htc htc;
536 struct ath10k_htt htt;
537
538 struct ath10k_hw_params {
539 u32 id;
540 const char *name;
541 u32 patch_load_addr;
542 int uart_pin;
543
544 struct ath10k_hw_params_fw {
545 const char *dir;
546 const char *fw;
547 const char *otp;
548 const char *board;
549 size_t board_size;
550 size_t board_ext_size;
551 } fw;
552 } hw_params;
553
554 const struct firmware *board;
555 const void *board_data;
556 size_t board_len;
557
558 const struct firmware *otp;
559 const void *otp_data;
560 size_t otp_len;
561
562 const struct firmware *firmware;
563 const void *firmware_data;
564 size_t firmware_len;
565
566 const struct firmware *cal_file;
567
568 int fw_api;
569 enum ath10k_cal_mode cal_mode;
570
571 struct {
572 struct completion started;
573 struct completion completed;
574 struct completion on_channel;
575 struct delayed_work timeout;
576 enum ath10k_scan_state state;
577 bool is_roc;
578 int vdev_id;
579 int roc_freq;
580 } scan;
581
582 struct {
583 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
584 } mac;
585
586
587 struct ieee80211_channel *rx_channel;
588
589
590 struct ieee80211_channel *scan_channel;
591
592
593 struct cfg80211_chan_def chandef;
594
595 unsigned long long free_vdev_map;
596 bool monitor;
597 int monitor_vdev_id;
598 bool monitor_started;
599 unsigned int filter_flags;
600 unsigned long dev_flags;
601 u32 dfs_block_radar_events;
602
603
604 bool radar_enabled;
605 int num_started_vdevs;
606
607
608 u8 supp_tx_chainmask;
609 u8 supp_rx_chainmask;
610 u8 cfg_tx_chainmask;
611 u8 cfg_rx_chainmask;
612
613 struct completion install_key_done;
614
615 struct completion vdev_setup_done;
616
617 struct workqueue_struct *workqueue;
618
619
620 struct mutex conf_mutex;
621
622
623 spinlock_t data_lock;
624
625 struct list_head arvifs;
626 struct list_head peers;
627 wait_queue_head_t peer_mapping_wq;
628
629
630 int num_peers;
631 int num_stations;
632
633 int max_num_peers;
634 int max_num_stations;
635 int max_num_vdevs;
636
637 struct work_struct offchan_tx_work;
638 struct sk_buff_head offchan_tx_queue;
639 struct completion offchan_tx_completed;
640 struct sk_buff *offchan_tx_skb;
641
642 struct work_struct wmi_mgmt_tx_work;
643 struct sk_buff_head wmi_mgmt_tx_queue;
644
645 enum ath10k_state state;
646
647 struct work_struct register_work;
648 struct work_struct restart_work;
649
650
651
652 u32 survey_last_rx_clear_count;
653 u32 survey_last_cycle_count;
654 struct survey_info survey[ATH10K_NUM_CHANS];
655
656 struct dfs_pattern_detector *dfs_detector;
657
658#ifdef CONFIG_ATH10K_DEBUGFS
659 struct ath10k_debug debug;
660#endif
661
662 struct {
663
664 struct rchan *rfs_chan_spec_scan;
665
666
667 enum ath10k_spectral_mode mode;
668 struct ath10k_spec_scan config;
669 } spectral;
670
671 struct {
672
673 const struct firmware *utf;
674 DECLARE_BITMAP(orig_fw_features, ATH10K_FW_FEATURE_COUNT);
675 enum ath10k_fw_wmi_op_version orig_wmi_op_version;
676
677
678 bool utf_monitor;
679 } testmode;
680
681 struct {
682
683 u32 fw_crash_counter;
684 u32 fw_warm_reset_counter;
685 u32 fw_cold_reset_counter;
686 } stats;
687
688 struct ath10k_thermal thermal;
689
690
691 u8 drv_priv[0] __aligned(sizeof(void *));
692};
693
694struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
695 enum ath10k_bus bus,
696 enum ath10k_hw_rev hw_rev,
697 const struct ath10k_hif_ops *hif_ops);
698void ath10k_core_destroy(struct ath10k *ar);
699
700int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode);
701int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
702void ath10k_core_stop(struct ath10k *ar);
703int ath10k_core_register(struct ath10k *ar, u32 chip_id);
704void ath10k_core_unregister(struct ath10k *ar);
705
706#endif
707