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10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/of.h>
14#include <linux/of_pci.h>
15#include <linux/pci.h>
16#include <linux/pm.h>
17#include <linux/slab.h>
18#include <linux/module.h>
19#include <linux/spinlock.h>
20#include <linux/string.h>
21#include <linux/log2.h>
22#include <linux/pci-aspm.h>
23#include <linux/pm_wakeup.h>
24#include <linux/interrupt.h>
25#include <linux/device.h>
26#include <linux/pm_runtime.h>
27#include <linux/pci_hotplug.h>
28#include <asm-generic/pci-bridge.h>
29#include <asm/setup.h>
30#include "pci.h"
31
32const char *pci_power_names[] = {
33 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
34};
35EXPORT_SYMBOL_GPL(pci_power_names);
36
37int isa_dma_bridge_buggy;
38EXPORT_SYMBOL(isa_dma_bridge_buggy);
39
40int pci_pci_problems;
41EXPORT_SYMBOL(pci_pci_problems);
42
43unsigned int pci_pm_d3_delay;
44
45static void pci_pme_list_scan(struct work_struct *work);
46
47static LIST_HEAD(pci_pme_list);
48static DEFINE_MUTEX(pci_pme_list_mutex);
49static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
50
51struct pci_pme_device {
52 struct list_head list;
53 struct pci_dev *dev;
54};
55
56#define PME_TIMEOUT 1000
57
58static void pci_dev_d3_sleep(struct pci_dev *dev)
59{
60 unsigned int delay = dev->d3_delay;
61
62 if (delay < pci_pm_d3_delay)
63 delay = pci_pm_d3_delay;
64
65 msleep(delay);
66}
67
68#ifdef CONFIG_PCI_DOMAINS
69int pci_domains_supported = 1;
70#endif
71
72#define DEFAULT_CARDBUS_IO_SIZE (256)
73#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
74
75unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
76unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
77
78#define DEFAULT_HOTPLUG_IO_SIZE (256)
79#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
80
81unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
82unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
83
84enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
85
86
87
88
89
90
91
92u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
93u8 pci_cache_line_size;
94
95
96
97
98
99unsigned int pcibios_max_latency = 255;
100
101
102static bool pcie_ari_disabled;
103
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108
109
110
111unsigned char pci_bus_max_busnr(struct pci_bus *bus)
112{
113 struct pci_bus *tmp;
114 unsigned char max, n;
115
116 max = bus->busn_res.end;
117 list_for_each_entry(tmp, &bus->children, node) {
118 n = pci_bus_max_busnr(tmp);
119 if (n > max)
120 max = n;
121 }
122 return max;
123}
124EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
125
126#ifdef CONFIG_HAS_IOMEM
127void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
128{
129 struct resource *res = &pdev->resource[bar];
130
131
132
133
134 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
135 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
136 return NULL;
137 }
138 return ioremap_nocache(res->start, resource_size(res));
139}
140EXPORT_SYMBOL_GPL(pci_ioremap_bar);
141#endif
142
143#define PCI_FIND_CAP_TTL 48
144
145static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
146 u8 pos, int cap, int *ttl)
147{
148 u8 id;
149 u16 ent;
150
151 pci_bus_read_config_byte(bus, devfn, pos, &pos);
152
153 while ((*ttl)--) {
154 if (pos < 0x40)
155 break;
156 pos &= ~3;
157 pci_bus_read_config_word(bus, devfn, pos, &ent);
158
159 id = ent & 0xff;
160 if (id == 0xff)
161 break;
162 if (id == cap)
163 return pos;
164 pos = (ent >> 8);
165 }
166 return 0;
167}
168
169static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
170 u8 pos, int cap)
171{
172 int ttl = PCI_FIND_CAP_TTL;
173
174 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
175}
176
177int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
178{
179 return __pci_find_next_cap(dev->bus, dev->devfn,
180 pos + PCI_CAP_LIST_NEXT, cap);
181}
182EXPORT_SYMBOL_GPL(pci_find_next_capability);
183
184static int __pci_bus_find_cap_start(struct pci_bus *bus,
185 unsigned int devfn, u8 hdr_type)
186{
187 u16 status;
188
189 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
190 if (!(status & PCI_STATUS_CAP_LIST))
191 return 0;
192
193 switch (hdr_type) {
194 case PCI_HEADER_TYPE_NORMAL:
195 case PCI_HEADER_TYPE_BRIDGE:
196 return PCI_CAPABILITY_LIST;
197 case PCI_HEADER_TYPE_CARDBUS:
198 return PCI_CB_CAPABILITY_LIST;
199 default:
200 return 0;
201 }
202
203 return 0;
204}
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224
225int pci_find_capability(struct pci_dev *dev, int cap)
226{
227 int pos;
228
229 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
230 if (pos)
231 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
232
233 return pos;
234}
235EXPORT_SYMBOL(pci_find_capability);
236
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248
249
250int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
251{
252 int pos;
253 u8 hdr_type;
254
255 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
256
257 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
258 if (pos)
259 pos = __pci_find_next_cap(bus, devfn, pos, cap);
260
261 return pos;
262}
263EXPORT_SYMBOL(pci_bus_find_capability);
264
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274
275
276int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
277{
278 u32 header;
279 int ttl;
280 int pos = PCI_CFG_SPACE_SIZE;
281
282
283 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
284
285 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
286 return 0;
287
288 if (start)
289 pos = start;
290
291 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
292 return 0;
293
294
295
296
297
298 if (header == 0)
299 return 0;
300
301 while (ttl-- > 0) {
302 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
303 return pos;
304
305 pos = PCI_EXT_CAP_NEXT(header);
306 if (pos < PCI_CFG_SPACE_SIZE)
307 break;
308
309 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
310 break;
311 }
312
313 return 0;
314}
315EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
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330
331int pci_find_ext_capability(struct pci_dev *dev, int cap)
332{
333 return pci_find_next_ext_capability(dev, 0, cap);
334}
335EXPORT_SYMBOL_GPL(pci_find_ext_capability);
336
337static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
338{
339 int rc, ttl = PCI_FIND_CAP_TTL;
340 u8 cap, mask;
341
342 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
343 mask = HT_3BIT_CAP_MASK;
344 else
345 mask = HT_5BIT_CAP_MASK;
346
347 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
348 PCI_CAP_ID_HT, &ttl);
349 while (pos) {
350 rc = pci_read_config_byte(dev, pos + 3, &cap);
351 if (rc != PCIBIOS_SUCCESSFUL)
352 return 0;
353
354 if ((cap & mask) == ht_cap)
355 return pos;
356
357 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
358 pos + PCI_CAP_LIST_NEXT,
359 PCI_CAP_ID_HT, &ttl);
360 }
361
362 return 0;
363}
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375
376
377int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
378{
379 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
380}
381EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
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392
393
394int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
395{
396 int pos;
397
398 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
399 if (pos)
400 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
401
402 return pos;
403}
404EXPORT_SYMBOL_GPL(pci_find_ht_capability);
405
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411
412
413
414struct resource *pci_find_parent_resource(const struct pci_dev *dev,
415 struct resource *res)
416{
417 const struct pci_bus *bus = dev->bus;
418 struct resource *r;
419 int i;
420
421 pci_bus_for_each_resource(bus, r, i) {
422 if (!r)
423 continue;
424 if (res->start && resource_contains(r, res)) {
425
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428
429
430 if (r->flags & IORESOURCE_PREFETCH &&
431 !(res->flags & IORESOURCE_PREFETCH))
432 return NULL;
433
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441
442 return r;
443 }
444 }
445 return NULL;
446}
447EXPORT_SYMBOL(pci_find_parent_resource);
448
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456
457int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
458{
459 int i;
460
461
462 for (i = 0; i < 4; i++) {
463 u16 status;
464 if (i)
465 msleep((1 << (i - 1)) * 100);
466
467 pci_read_config_word(dev, pos, &status);
468 if (!(status & mask))
469 return 1;
470 }
471
472 return 0;
473}
474
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480
481
482static void pci_restore_bars(struct pci_dev *dev)
483{
484 int i;
485
486 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
487 pci_update_resource(dev, i);
488}
489
490static struct pci_platform_pm_ops *pci_platform_pm;
491
492int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
493{
494 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
495 || !ops->sleep_wake)
496 return -EINVAL;
497 pci_platform_pm = ops;
498 return 0;
499}
500
501static inline bool platform_pci_power_manageable(struct pci_dev *dev)
502{
503 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
504}
505
506static inline int platform_pci_set_power_state(struct pci_dev *dev,
507 pci_power_t t)
508{
509 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
510}
511
512static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
513{
514 return pci_platform_pm ?
515 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
516}
517
518static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
519{
520 return pci_platform_pm ?
521 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
522}
523
524static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
525{
526 return pci_platform_pm ?
527 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
528}
529
530static inline bool platform_pci_need_resume(struct pci_dev *dev)
531{
532 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
533}
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547
548static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
549{
550 u16 pmcsr;
551 bool need_restore = false;
552
553
554 if (dev->current_state == state)
555 return 0;
556
557 if (!dev->pm_cap)
558 return -EIO;
559
560 if (state < PCI_D0 || state > PCI_D3hot)
561 return -EINVAL;
562
563
564
565
566
567 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
568 && dev->current_state > state) {
569 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
570 dev->current_state, state);
571 return -EINVAL;
572 }
573
574
575 if ((state == PCI_D1 && !dev->d1_support)
576 || (state == PCI_D2 && !dev->d2_support))
577 return -EIO;
578
579 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
580
581
582
583
584
585 switch (dev->current_state) {
586 case PCI_D0:
587 case PCI_D1:
588 case PCI_D2:
589 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
590 pmcsr |= state;
591 break;
592 case PCI_D3hot:
593 case PCI_D3cold:
594 case PCI_UNKNOWN:
595 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
596 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
597 need_restore = true;
598
599 default:
600 pmcsr = 0;
601 break;
602 }
603
604
605 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
606
607
608
609 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
610 pci_dev_d3_sleep(dev);
611 else if (state == PCI_D2 || dev->current_state == PCI_D2)
612 udelay(PCI_PM_D2_DELAY);
613
614 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
615 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
616 if (dev->current_state != state && printk_ratelimit())
617 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
618 dev->current_state);
619
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631
632
633 if (need_restore)
634 pci_restore_bars(dev);
635
636 if (dev->bus->self)
637 pcie_aspm_pm_state_change(dev->bus->self);
638
639 return 0;
640}
641
642
643
644
645
646
647
648void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
649{
650 if (dev->pm_cap) {
651 u16 pmcsr;
652
653
654
655
656
657 if (dev->current_state == PCI_D3cold)
658 return;
659 if (state == PCI_D3cold) {
660 dev->current_state = PCI_D3cold;
661 return;
662 }
663 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
664 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
665 } else {
666 dev->current_state = state;
667 }
668}
669
670
671
672
673
674void pci_power_up(struct pci_dev *dev)
675{
676 if (platform_pci_power_manageable(dev))
677 platform_pci_set_power_state(dev, PCI_D0);
678
679 pci_raw_set_power_state(dev, PCI_D0);
680 pci_update_current_state(dev, PCI_D0);
681}
682
683
684
685
686
687
688static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
689{
690 int error;
691
692 if (platform_pci_power_manageable(dev)) {
693 error = platform_pci_set_power_state(dev, state);
694 if (!error)
695 pci_update_current_state(dev, state);
696 } else
697 error = -ENODEV;
698
699 if (error && !dev->pm_cap)
700 dev->current_state = PCI_D0;
701
702 return error;
703}
704
705
706
707
708
709
710static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
711{
712 pci_wakeup_event(pci_dev);
713 pm_request_resume(&pci_dev->dev);
714 return 0;
715}
716
717
718
719
720
721static void pci_wakeup_bus(struct pci_bus *bus)
722{
723 if (bus)
724 pci_walk_bus(bus, pci_wakeup, NULL);
725}
726
727
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729
730
731
732static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
733{
734 if (state == PCI_D0) {
735 pci_platform_power_transition(dev, PCI_D0);
736
737
738
739
740
741
742
743 if (dev->runtime_d3cold) {
744 msleep(dev->d3cold_delay);
745
746
747
748
749
750
751 pci_wakeup_bus(dev->subordinate);
752 }
753 }
754}
755
756
757
758
759
760
761static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
762{
763 pci_power_t state = *(pci_power_t *)data;
764
765 dev->current_state = state;
766 return 0;
767}
768
769
770
771
772
773
774static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
775{
776 if (bus)
777 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
778}
779
780
781
782
783
784
785
786
787int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
788{
789 int ret;
790
791 if (state <= PCI_D0)
792 return -EINVAL;
793 ret = pci_platform_power_transition(dev, state);
794
795 if (!ret && state == PCI_D3cold)
796 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
797 return ret;
798}
799EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
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814
815
816int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
817{
818 int error;
819
820
821 if (state > PCI_D3cold)
822 state = PCI_D3cold;
823 else if (state < PCI_D0)
824 state = PCI_D0;
825 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
826
827
828
829
830
831 return 0;
832
833
834 if (dev->current_state == state)
835 return 0;
836
837 __pci_start_power_transition(dev, state);
838
839
840
841 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
842 return 0;
843
844
845
846
847
848 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
849 PCI_D3hot : state);
850
851 if (!__pci_complete_power_transition(dev, state))
852 error = 0;
853
854 return error;
855}
856EXPORT_SYMBOL(pci_set_power_state);
857
858
859
860
861
862
863
864
865
866
867
868pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
869{
870 pci_power_t ret;
871
872 if (!dev->pm_cap)
873 return PCI_D0;
874
875 ret = platform_pci_choose_state(dev);
876 if (ret != PCI_POWER_ERROR)
877 return ret;
878
879 switch (state.event) {
880 case PM_EVENT_ON:
881 return PCI_D0;
882 case PM_EVENT_FREEZE:
883 case PM_EVENT_PRETHAW:
884
885 case PM_EVENT_SUSPEND:
886 case PM_EVENT_HIBERNATE:
887 return PCI_D3hot;
888 default:
889 dev_info(&dev->dev, "unrecognized suspend event %d\n",
890 state.event);
891 BUG();
892 }
893 return PCI_D0;
894}
895EXPORT_SYMBOL(pci_choose_state);
896
897#define PCI_EXP_SAVE_REGS 7
898
899static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
900 u16 cap, bool extended)
901{
902 struct pci_cap_saved_state *tmp;
903
904 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
905 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
906 return tmp;
907 }
908 return NULL;
909}
910
911struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
912{
913 return _pci_find_saved_cap(dev, cap, false);
914}
915
916struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
917{
918 return _pci_find_saved_cap(dev, cap, true);
919}
920
921static int pci_save_pcie_state(struct pci_dev *dev)
922{
923 int i = 0;
924 struct pci_cap_saved_state *save_state;
925 u16 *cap;
926
927 if (!pci_is_pcie(dev))
928 return 0;
929
930 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
931 if (!save_state) {
932 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
933 return -ENOMEM;
934 }
935
936 cap = (u16 *)&save_state->cap.data[0];
937 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
938 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
939 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
940 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
941 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
942 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
943 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
944
945 return 0;
946}
947
948static void pci_restore_pcie_state(struct pci_dev *dev)
949{
950 int i = 0;
951 struct pci_cap_saved_state *save_state;
952 u16 *cap;
953
954 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
955 if (!save_state)
956 return;
957
958 cap = (u16 *)&save_state->cap.data[0];
959 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
960 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
961 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
962 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
963 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
964 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
965 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
966}
967
968
969static int pci_save_pcix_state(struct pci_dev *dev)
970{
971 int pos;
972 struct pci_cap_saved_state *save_state;
973
974 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
975 if (pos <= 0)
976 return 0;
977
978 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
979 if (!save_state) {
980 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
981 return -ENOMEM;
982 }
983
984 pci_read_config_word(dev, pos + PCI_X_CMD,
985 (u16 *)save_state->cap.data);
986
987 return 0;
988}
989
990static void pci_restore_pcix_state(struct pci_dev *dev)
991{
992 int i = 0, pos;
993 struct pci_cap_saved_state *save_state;
994 u16 *cap;
995
996 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
997 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
998 if (!save_state || pos <= 0)
999 return;
1000 cap = (u16 *)&save_state->cap.data[0];
1001
1002 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1003}
1004
1005
1006
1007
1008
1009
1010int pci_save_state(struct pci_dev *dev)
1011{
1012 int i;
1013
1014 for (i = 0; i < 16; i++)
1015 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1016 dev->state_saved = true;
1017
1018 i = pci_save_pcie_state(dev);
1019 if (i != 0)
1020 return i;
1021
1022 i = pci_save_pcix_state(dev);
1023 if (i != 0)
1024 return i;
1025
1026 return pci_save_vc_state(dev);
1027}
1028EXPORT_SYMBOL(pci_save_state);
1029
1030static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1031 u32 saved_val, int retry)
1032{
1033 u32 val;
1034
1035 pci_read_config_dword(pdev, offset, &val);
1036 if (val == saved_val)
1037 return;
1038
1039 for (;;) {
1040 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1041 offset, val, saved_val);
1042 pci_write_config_dword(pdev, offset, saved_val);
1043 if (retry-- <= 0)
1044 return;
1045
1046 pci_read_config_dword(pdev, offset, &val);
1047 if (val == saved_val)
1048 return;
1049
1050 mdelay(1);
1051 }
1052}
1053
1054static void pci_restore_config_space_range(struct pci_dev *pdev,
1055 int start, int end, int retry)
1056{
1057 int index;
1058
1059 for (index = end; index >= start; index--)
1060 pci_restore_config_dword(pdev, 4 * index,
1061 pdev->saved_config_space[index],
1062 retry);
1063}
1064
1065static void pci_restore_config_space(struct pci_dev *pdev)
1066{
1067 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1068 pci_restore_config_space_range(pdev, 10, 15, 0);
1069
1070 pci_restore_config_space_range(pdev, 4, 9, 10);
1071 pci_restore_config_space_range(pdev, 0, 3, 0);
1072 } else {
1073 pci_restore_config_space_range(pdev, 0, 15, 0);
1074 }
1075}
1076
1077
1078
1079
1080
1081void pci_restore_state(struct pci_dev *dev)
1082{
1083 if (!dev->state_saved)
1084 return;
1085
1086
1087 pci_restore_pcie_state(dev);
1088 pci_restore_ats_state(dev);
1089 pci_restore_vc_state(dev);
1090
1091 pci_restore_config_space(dev);
1092
1093 pci_restore_pcix_state(dev);
1094 pci_restore_msi_state(dev);
1095 pci_restore_iov_state(dev);
1096
1097 dev->state_saved = false;
1098}
1099EXPORT_SYMBOL(pci_restore_state);
1100
1101struct pci_saved_state {
1102 u32 config_space[16];
1103 struct pci_cap_saved_data cap[0];
1104};
1105
1106
1107
1108
1109
1110
1111
1112
1113struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1114{
1115 struct pci_saved_state *state;
1116 struct pci_cap_saved_state *tmp;
1117 struct pci_cap_saved_data *cap;
1118 size_t size;
1119
1120 if (!dev->state_saved)
1121 return NULL;
1122
1123 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1124
1125 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1126 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1127
1128 state = kzalloc(size, GFP_KERNEL);
1129 if (!state)
1130 return NULL;
1131
1132 memcpy(state->config_space, dev->saved_config_space,
1133 sizeof(state->config_space));
1134
1135 cap = state->cap;
1136 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1137 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1138 memcpy(cap, &tmp->cap, len);
1139 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1140 }
1141
1142
1143 return state;
1144}
1145EXPORT_SYMBOL_GPL(pci_store_saved_state);
1146
1147
1148
1149
1150
1151
1152int pci_load_saved_state(struct pci_dev *dev,
1153 struct pci_saved_state *state)
1154{
1155 struct pci_cap_saved_data *cap;
1156
1157 dev->state_saved = false;
1158
1159 if (!state)
1160 return 0;
1161
1162 memcpy(dev->saved_config_space, state->config_space,
1163 sizeof(state->config_space));
1164
1165 cap = state->cap;
1166 while (cap->size) {
1167 struct pci_cap_saved_state *tmp;
1168
1169 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1170 if (!tmp || tmp->cap.size != cap->size)
1171 return -EINVAL;
1172
1173 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1174 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1175 sizeof(struct pci_cap_saved_data) + cap->size);
1176 }
1177
1178 dev->state_saved = true;
1179 return 0;
1180}
1181EXPORT_SYMBOL_GPL(pci_load_saved_state);
1182
1183
1184
1185
1186
1187
1188
1189int pci_load_and_free_saved_state(struct pci_dev *dev,
1190 struct pci_saved_state **state)
1191{
1192 int ret = pci_load_saved_state(dev, *state);
1193 kfree(*state);
1194 *state = NULL;
1195 return ret;
1196}
1197EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1198
1199int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1200{
1201 return pci_enable_resources(dev, bars);
1202}
1203
1204static int do_pci_enable_device(struct pci_dev *dev, int bars)
1205{
1206 int err;
1207 struct pci_dev *bridge;
1208 u16 cmd;
1209 u8 pin;
1210
1211 err = pci_set_power_state(dev, PCI_D0);
1212 if (err < 0 && err != -EIO)
1213 return err;
1214
1215 bridge = pci_upstream_bridge(dev);
1216 if (bridge)
1217 pcie_aspm_powersave_config_link(bridge);
1218
1219 err = pcibios_enable_device(dev, bars);
1220 if (err < 0)
1221 return err;
1222 pci_fixup_device(pci_fixup_enable, dev);
1223
1224 if (dev->msi_enabled || dev->msix_enabled)
1225 return 0;
1226
1227 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1228 if (pin) {
1229 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1230 if (cmd & PCI_COMMAND_INTX_DISABLE)
1231 pci_write_config_word(dev, PCI_COMMAND,
1232 cmd & ~PCI_COMMAND_INTX_DISABLE);
1233 }
1234
1235 return 0;
1236}
1237
1238
1239
1240
1241
1242
1243
1244
1245int pci_reenable_device(struct pci_dev *dev)
1246{
1247 if (pci_is_enabled(dev))
1248 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1249 return 0;
1250}
1251EXPORT_SYMBOL(pci_reenable_device);
1252
1253static void pci_enable_bridge(struct pci_dev *dev)
1254{
1255 struct pci_dev *bridge;
1256 int retval;
1257
1258 bridge = pci_upstream_bridge(dev);
1259 if (bridge)
1260 pci_enable_bridge(bridge);
1261
1262 if (pci_is_enabled(dev)) {
1263 if (!dev->is_busmaster)
1264 pci_set_master(dev);
1265 return;
1266 }
1267
1268 retval = pci_enable_device(dev);
1269 if (retval)
1270 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1271 retval);
1272 pci_set_master(dev);
1273}
1274
1275static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1276{
1277 struct pci_dev *bridge;
1278 int err;
1279 int i, bars = 0;
1280
1281
1282
1283
1284
1285
1286
1287 if (dev->pm_cap) {
1288 u16 pmcsr;
1289 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1290 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1291 }
1292
1293 if (atomic_inc_return(&dev->enable_cnt) > 1)
1294 return 0;
1295
1296 bridge = pci_upstream_bridge(dev);
1297 if (bridge)
1298 pci_enable_bridge(bridge);
1299
1300
1301 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1302 if (dev->resource[i].flags & flags)
1303 bars |= (1 << i);
1304 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1305 if (dev->resource[i].flags & flags)
1306 bars |= (1 << i);
1307
1308 err = do_pci_enable_device(dev, bars);
1309 if (err < 0)
1310 atomic_dec(&dev->enable_cnt);
1311 return err;
1312}
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322int pci_enable_device_io(struct pci_dev *dev)
1323{
1324 return pci_enable_device_flags(dev, IORESOURCE_IO);
1325}
1326EXPORT_SYMBOL(pci_enable_device_io);
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336int pci_enable_device_mem(struct pci_dev *dev)
1337{
1338 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1339}
1340EXPORT_SYMBOL(pci_enable_device_mem);
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353int pci_enable_device(struct pci_dev *dev)
1354{
1355 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1356}
1357EXPORT_SYMBOL(pci_enable_device);
1358
1359
1360
1361
1362
1363
1364
1365struct pci_devres {
1366 unsigned int enabled:1;
1367 unsigned int pinned:1;
1368 unsigned int orig_intx:1;
1369 unsigned int restore_intx:1;
1370 u32 region_mask;
1371};
1372
1373static void pcim_release(struct device *gendev, void *res)
1374{
1375 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1376 struct pci_devres *this = res;
1377 int i;
1378
1379 if (dev->msi_enabled)
1380 pci_disable_msi(dev);
1381 if (dev->msix_enabled)
1382 pci_disable_msix(dev);
1383
1384 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1385 if (this->region_mask & (1 << i))
1386 pci_release_region(dev, i);
1387
1388 if (this->restore_intx)
1389 pci_intx(dev, this->orig_intx);
1390
1391 if (this->enabled && !this->pinned)
1392 pci_disable_device(dev);
1393}
1394
1395static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1396{
1397 struct pci_devres *dr, *new_dr;
1398
1399 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1400 if (dr)
1401 return dr;
1402
1403 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1404 if (!new_dr)
1405 return NULL;
1406 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1407}
1408
1409static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1410{
1411 if (pci_is_managed(pdev))
1412 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1413 return NULL;
1414}
1415
1416
1417
1418
1419
1420
1421
1422int pcim_enable_device(struct pci_dev *pdev)
1423{
1424 struct pci_devres *dr;
1425 int rc;
1426
1427 dr = get_pci_dr(pdev);
1428 if (unlikely(!dr))
1429 return -ENOMEM;
1430 if (dr->enabled)
1431 return 0;
1432
1433 rc = pci_enable_device(pdev);
1434 if (!rc) {
1435 pdev->is_managed = 1;
1436 dr->enabled = 1;
1437 }
1438 return rc;
1439}
1440EXPORT_SYMBOL(pcim_enable_device);
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450void pcim_pin_device(struct pci_dev *pdev)
1451{
1452 struct pci_devres *dr;
1453
1454 dr = find_pci_dr(pdev);
1455 WARN_ON(!dr || !dr->enabled);
1456 if (dr)
1457 dr->pinned = 1;
1458}
1459EXPORT_SYMBOL(pcim_pin_device);
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469int __weak pcibios_add_device(struct pci_dev *dev)
1470{
1471 return 0;
1472}
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482void __weak pcibios_release_device(struct pci_dev *dev) {}
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492void __weak pcibios_disable_device (struct pci_dev *dev) {}
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1504
1505static void do_pci_disable_device(struct pci_dev *dev)
1506{
1507 u16 pci_command;
1508
1509 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1510 if (pci_command & PCI_COMMAND_MASTER) {
1511 pci_command &= ~PCI_COMMAND_MASTER;
1512 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1513 }
1514
1515 pcibios_disable_device(dev);
1516}
1517
1518
1519
1520
1521
1522
1523
1524
1525void pci_disable_enabled_device(struct pci_dev *dev)
1526{
1527 if (pci_is_enabled(dev))
1528 do_pci_disable_device(dev);
1529}
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541void pci_disable_device(struct pci_dev *dev)
1542{
1543 struct pci_devres *dr;
1544
1545 dr = find_pci_dr(dev);
1546 if (dr)
1547 dr->enabled = 0;
1548
1549 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1550 "disabling already-disabled device");
1551
1552 if (atomic_dec_return(&dev->enable_cnt) != 0)
1553 return;
1554
1555 do_pci_disable_device(dev);
1556
1557 dev->is_busmaster = 0;
1558}
1559EXPORT_SYMBOL(pci_disable_device);
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1571 enum pcie_reset_state state)
1572{
1573 return -EINVAL;
1574}
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1585{
1586 return pcibios_set_pcie_reset_state(dev, state);
1587}
1588EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598bool pci_check_pme_status(struct pci_dev *dev)
1599{
1600 int pmcsr_pos;
1601 u16 pmcsr;
1602 bool ret = false;
1603
1604 if (!dev->pm_cap)
1605 return false;
1606
1607 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1608 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1609 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1610 return false;
1611
1612
1613 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1614 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1615
1616 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1617 ret = true;
1618 }
1619
1620 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1621
1622 return ret;
1623}
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1634{
1635 if (pme_poll_reset && dev->pme_poll)
1636 dev->pme_poll = false;
1637
1638 if (pci_check_pme_status(dev)) {
1639 pci_wakeup_event(dev);
1640 pm_request_resume(&dev->dev);
1641 }
1642 return 0;
1643}
1644
1645
1646
1647
1648
1649void pci_pme_wakeup_bus(struct pci_bus *bus)
1650{
1651 if (bus)
1652 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1653}
1654
1655
1656
1657
1658
1659
1660
1661bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1662{
1663 if (!dev->pm_cap)
1664 return false;
1665
1666 return !!(dev->pme_support & (1 << state));
1667}
1668EXPORT_SYMBOL(pci_pme_capable);
1669
1670static void pci_pme_list_scan(struct work_struct *work)
1671{
1672 struct pci_pme_device *pme_dev, *n;
1673
1674 mutex_lock(&pci_pme_list_mutex);
1675 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1676 if (pme_dev->dev->pme_poll) {
1677 struct pci_dev *bridge;
1678
1679 bridge = pme_dev->dev->bus->self;
1680
1681
1682
1683
1684
1685 if (bridge && bridge->current_state != PCI_D0)
1686 continue;
1687 pci_pme_wakeup(pme_dev->dev, NULL);
1688 } else {
1689 list_del(&pme_dev->list);
1690 kfree(pme_dev);
1691 }
1692 }
1693 if (!list_empty(&pci_pme_list))
1694 schedule_delayed_work(&pci_pme_work,
1695 msecs_to_jiffies(PME_TIMEOUT));
1696 mutex_unlock(&pci_pme_list_mutex);
1697}
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707void pci_pme_active(struct pci_dev *dev, bool enable)
1708{
1709 u16 pmcsr;
1710
1711 if (!dev->pme_support)
1712 return;
1713
1714 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1715
1716 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1717 if (!enable)
1718 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1719
1720 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742 if (dev->pme_poll) {
1743 struct pci_pme_device *pme_dev;
1744 if (enable) {
1745 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1746 GFP_KERNEL);
1747 if (!pme_dev) {
1748 dev_warn(&dev->dev, "can't enable PME#\n");
1749 return;
1750 }
1751 pme_dev->dev = dev;
1752 mutex_lock(&pci_pme_list_mutex);
1753 list_add(&pme_dev->list, &pci_pme_list);
1754 if (list_is_singular(&pci_pme_list))
1755 schedule_delayed_work(&pci_pme_work,
1756 msecs_to_jiffies(PME_TIMEOUT));
1757 mutex_unlock(&pci_pme_list_mutex);
1758 } else {
1759 mutex_lock(&pci_pme_list_mutex);
1760 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1761 if (pme_dev->dev == dev) {
1762 list_del(&pme_dev->list);
1763 kfree(pme_dev);
1764 break;
1765 }
1766 }
1767 mutex_unlock(&pci_pme_list_mutex);
1768 }
1769 }
1770
1771 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1772}
1773EXPORT_SYMBOL(pci_pme_active);
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1796 bool runtime, bool enable)
1797{
1798 int ret = 0;
1799
1800 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1801 return -EINVAL;
1802
1803
1804 if (!!enable == !!dev->wakeup_prepared)
1805 return 0;
1806
1807
1808
1809
1810
1811
1812
1813 if (enable) {
1814 int error;
1815
1816 if (pci_pme_capable(dev, state))
1817 pci_pme_active(dev, true);
1818 else
1819 ret = 1;
1820 error = runtime ? platform_pci_run_wake(dev, true) :
1821 platform_pci_sleep_wake(dev, true);
1822 if (ret)
1823 ret = error;
1824 if (!ret)
1825 dev->wakeup_prepared = true;
1826 } else {
1827 if (runtime)
1828 platform_pci_run_wake(dev, false);
1829 else
1830 platform_pci_sleep_wake(dev, false);
1831 pci_pme_active(dev, false);
1832 dev->wakeup_prepared = false;
1833 }
1834
1835 return ret;
1836}
1837EXPORT_SYMBOL(__pci_enable_wake);
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1854{
1855 return pci_pme_capable(dev, PCI_D3cold) ?
1856 pci_enable_wake(dev, PCI_D3cold, enable) :
1857 pci_enable_wake(dev, PCI_D3hot, enable);
1858}
1859EXPORT_SYMBOL(pci_wake_from_d3);
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869static pci_power_t pci_target_state(struct pci_dev *dev)
1870{
1871 pci_power_t target_state = PCI_D3hot;
1872
1873 if (platform_pci_power_manageable(dev)) {
1874
1875
1876
1877
1878 pci_power_t state = platform_pci_choose_state(dev);
1879
1880 switch (state) {
1881 case PCI_POWER_ERROR:
1882 case PCI_UNKNOWN:
1883 break;
1884 case PCI_D1:
1885 case PCI_D2:
1886 if (pci_no_d1d2(dev))
1887 break;
1888 default:
1889 target_state = state;
1890 }
1891 } else if (!dev->pm_cap) {
1892 target_state = PCI_D0;
1893 } else if (device_may_wakeup(&dev->dev)) {
1894
1895
1896
1897
1898
1899 if (dev->pme_support) {
1900 while (target_state
1901 && !(dev->pme_support & (1 << target_state)))
1902 target_state--;
1903 }
1904 }
1905
1906 return target_state;
1907}
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917int pci_prepare_to_sleep(struct pci_dev *dev)
1918{
1919 pci_power_t target_state = pci_target_state(dev);
1920 int error;
1921
1922 if (target_state == PCI_POWER_ERROR)
1923 return -EIO;
1924
1925 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1926
1927 error = pci_set_power_state(dev, target_state);
1928
1929 if (error)
1930 pci_enable_wake(dev, target_state, false);
1931
1932 return error;
1933}
1934EXPORT_SYMBOL(pci_prepare_to_sleep);
1935
1936
1937
1938
1939
1940
1941
1942int pci_back_from_sleep(struct pci_dev *dev)
1943{
1944 pci_enable_wake(dev, PCI_D0, false);
1945 return pci_set_power_state(dev, PCI_D0);
1946}
1947EXPORT_SYMBOL(pci_back_from_sleep);
1948
1949
1950
1951
1952
1953
1954
1955
1956int pci_finish_runtime_suspend(struct pci_dev *dev)
1957{
1958 pci_power_t target_state = pci_target_state(dev);
1959 int error;
1960
1961 if (target_state == PCI_POWER_ERROR)
1962 return -EIO;
1963
1964 dev->runtime_d3cold = target_state == PCI_D3cold;
1965
1966 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1967
1968 error = pci_set_power_state(dev, target_state);
1969
1970 if (error) {
1971 __pci_enable_wake(dev, target_state, true, false);
1972 dev->runtime_d3cold = false;
1973 }
1974
1975 return error;
1976}
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986bool pci_dev_run_wake(struct pci_dev *dev)
1987{
1988 struct pci_bus *bus = dev->bus;
1989
1990 if (device_run_wake(&dev->dev))
1991 return true;
1992
1993 if (!dev->pme_support)
1994 return false;
1995
1996 while (bus->parent) {
1997 struct pci_dev *bridge = bus->self;
1998
1999 if (device_run_wake(&bridge->dev))
2000 return true;
2001
2002 bus = bus->parent;
2003 }
2004
2005
2006 if (bus->bridge)
2007 return device_run_wake(bus->bridge);
2008
2009 return false;
2010}
2011EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2023{
2024 struct device *dev = &pci_dev->dev;
2025
2026 if (!pm_runtime_suspended(dev)
2027 || (device_can_wakeup(dev) && !device_may_wakeup(dev))
2028 || platform_pci_need_resume(pci_dev))
2029 return false;
2030
2031 return pci_target_state(pci_dev) == pci_dev->current_state;
2032}
2033
2034void pci_config_pm_runtime_get(struct pci_dev *pdev)
2035{
2036 struct device *dev = &pdev->dev;
2037 struct device *parent = dev->parent;
2038
2039 if (parent)
2040 pm_runtime_get_sync(parent);
2041 pm_runtime_get_noresume(dev);
2042
2043
2044
2045
2046 pm_runtime_barrier(dev);
2047
2048
2049
2050
2051
2052 if (pdev->current_state == PCI_D3cold)
2053 pm_runtime_resume(dev);
2054}
2055
2056void pci_config_pm_runtime_put(struct pci_dev *pdev)
2057{
2058 struct device *dev = &pdev->dev;
2059 struct device *parent = dev->parent;
2060
2061 pm_runtime_put(dev);
2062 if (parent)
2063 pm_runtime_put_sync(parent);
2064}
2065
2066
2067
2068
2069
2070void pci_pm_init(struct pci_dev *dev)
2071{
2072 int pm;
2073 u16 pmc;
2074
2075 pm_runtime_forbid(&dev->dev);
2076 pm_runtime_set_active(&dev->dev);
2077 pm_runtime_enable(&dev->dev);
2078 device_enable_async_suspend(&dev->dev);
2079 dev->wakeup_prepared = false;
2080
2081 dev->pm_cap = 0;
2082 dev->pme_support = 0;
2083
2084
2085 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2086 if (!pm)
2087 return;
2088
2089 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2090
2091 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2092 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2093 pmc & PCI_PM_CAP_VER_MASK);
2094 return;
2095 }
2096
2097 dev->pm_cap = pm;
2098 dev->d3_delay = PCI_PM_D3_WAIT;
2099 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2100 dev->d3cold_allowed = true;
2101
2102 dev->d1_support = false;
2103 dev->d2_support = false;
2104 if (!pci_no_d1d2(dev)) {
2105 if (pmc & PCI_PM_CAP_D1)
2106 dev->d1_support = true;
2107 if (pmc & PCI_PM_CAP_D2)
2108 dev->d2_support = true;
2109
2110 if (dev->d1_support || dev->d2_support)
2111 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2112 dev->d1_support ? " D1" : "",
2113 dev->d2_support ? " D2" : "");
2114 }
2115
2116 pmc &= PCI_PM_CAP_PME_MASK;
2117 if (pmc) {
2118 dev_printk(KERN_DEBUG, &dev->dev,
2119 "PME# supported from%s%s%s%s%s\n",
2120 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2121 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2122 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2123 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2124 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2125 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2126 dev->pme_poll = true;
2127
2128
2129
2130
2131 device_set_wakeup_capable(&dev->dev, true);
2132
2133 pci_pme_active(dev, false);
2134 }
2135}
2136
2137static void pci_add_saved_cap(struct pci_dev *pci_dev,
2138 struct pci_cap_saved_state *new_cap)
2139{
2140 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2141}
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2152 bool extended, unsigned int size)
2153{
2154 int pos;
2155 struct pci_cap_saved_state *save_state;
2156
2157 if (extended)
2158 pos = pci_find_ext_capability(dev, cap);
2159 else
2160 pos = pci_find_capability(dev, cap);
2161
2162 if (pos <= 0)
2163 return 0;
2164
2165 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2166 if (!save_state)
2167 return -ENOMEM;
2168
2169 save_state->cap.cap_nr = cap;
2170 save_state->cap.cap_extended = extended;
2171 save_state->cap.size = size;
2172 pci_add_saved_cap(dev, save_state);
2173
2174 return 0;
2175}
2176
2177int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2178{
2179 return _pci_add_cap_save_buffer(dev, cap, false, size);
2180}
2181
2182int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2183{
2184 return _pci_add_cap_save_buffer(dev, cap, true, size);
2185}
2186
2187
2188
2189
2190
2191void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2192{
2193 int error;
2194
2195 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2196 PCI_EXP_SAVE_REGS * sizeof(u16));
2197 if (error)
2198 dev_err(&dev->dev,
2199 "unable to preallocate PCI Express save buffer\n");
2200
2201 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2202 if (error)
2203 dev_err(&dev->dev,
2204 "unable to preallocate PCI-X save buffer\n");
2205
2206 pci_allocate_vc_save_buffers(dev);
2207}
2208
2209void pci_free_cap_save_buffers(struct pci_dev *dev)
2210{
2211 struct pci_cap_saved_state *tmp;
2212 struct hlist_node *n;
2213
2214 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2215 kfree(tmp);
2216}
2217
2218
2219
2220
2221
2222
2223
2224
2225void pci_configure_ari(struct pci_dev *dev)
2226{
2227 u32 cap;
2228 struct pci_dev *bridge;
2229
2230 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2231 return;
2232
2233 bridge = dev->bus->self;
2234 if (!bridge)
2235 return;
2236
2237 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2238 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2239 return;
2240
2241 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2242 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2243 PCI_EXP_DEVCTL2_ARI);
2244 bridge->ari_enabled = 1;
2245 } else {
2246 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2247 PCI_EXP_DEVCTL2_ARI);
2248 bridge->ari_enabled = 0;
2249 }
2250}
2251
2252static int pci_acs_enable;
2253
2254
2255
2256
2257void pci_request_acs(void)
2258{
2259 pci_acs_enable = 1;
2260}
2261
2262
2263
2264
2265
2266static int pci_std_enable_acs(struct pci_dev *dev)
2267{
2268 int pos;
2269 u16 cap;
2270 u16 ctrl;
2271
2272 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2273 if (!pos)
2274 return -ENODEV;
2275
2276 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2277 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2278
2279
2280 ctrl |= (cap & PCI_ACS_SV);
2281
2282
2283 ctrl |= (cap & PCI_ACS_RR);
2284
2285
2286 ctrl |= (cap & PCI_ACS_CR);
2287
2288
2289 ctrl |= (cap & PCI_ACS_UF);
2290
2291 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2292
2293 return 0;
2294}
2295
2296
2297
2298
2299
2300void pci_enable_acs(struct pci_dev *dev)
2301{
2302 if (!pci_acs_enable)
2303 return;
2304
2305 if (!pci_std_enable_acs(dev))
2306 return;
2307
2308 pci_dev_specific_enable_acs(dev);
2309}
2310
2311static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2312{
2313 int pos;
2314 u16 cap, ctrl;
2315
2316 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2317 if (!pos)
2318 return false;
2319
2320
2321
2322
2323
2324
2325 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2326 acs_flags &= (cap | PCI_ACS_EC);
2327
2328 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2329 return (ctrl & acs_flags) == acs_flags;
2330}
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2349{
2350 int ret;
2351
2352 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2353 if (ret >= 0)
2354 return ret > 0;
2355
2356
2357
2358
2359
2360
2361 if (!pci_is_pcie(pdev))
2362 return false;
2363
2364 switch (pci_pcie_type(pdev)) {
2365
2366
2367
2368
2369
2370 case PCI_EXP_TYPE_PCIE_BRIDGE:
2371
2372
2373
2374
2375
2376
2377 case PCI_EXP_TYPE_PCI_BRIDGE:
2378 case PCI_EXP_TYPE_RC_EC:
2379 return false;
2380
2381
2382
2383
2384
2385 case PCI_EXP_TYPE_DOWNSTREAM:
2386 case PCI_EXP_TYPE_ROOT_PORT:
2387 return pci_acs_flags_enabled(pdev, acs_flags);
2388
2389
2390
2391
2392
2393
2394
2395 case PCI_EXP_TYPE_ENDPOINT:
2396 case PCI_EXP_TYPE_UPSTREAM:
2397 case PCI_EXP_TYPE_LEG_END:
2398 case PCI_EXP_TYPE_RC_END:
2399 if (!pdev->multifunction)
2400 break;
2401
2402 return pci_acs_flags_enabled(pdev, acs_flags);
2403 }
2404
2405
2406
2407
2408
2409 return true;
2410}
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421bool pci_acs_path_enabled(struct pci_dev *start,
2422 struct pci_dev *end, u16 acs_flags)
2423{
2424 struct pci_dev *pdev, *parent = start;
2425
2426 do {
2427 pdev = parent;
2428
2429 if (!pci_acs_enabled(pdev, acs_flags))
2430 return false;
2431
2432 if (pci_is_root_bus(pdev->bus))
2433 return (end == NULL);
2434
2435 parent = pdev->bus->self;
2436 } while (pdev != end);
2437
2438 return true;
2439}
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2453{
2454 int slot;
2455
2456 if (pci_ari_enabled(dev->bus))
2457 slot = 0;
2458 else
2459 slot = PCI_SLOT(dev->devfn);
2460
2461 return (((pin - 1) + slot) % 4) + 1;
2462}
2463
2464int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2465{
2466 u8 pin;
2467
2468 pin = dev->pin;
2469 if (!pin)
2470 return -1;
2471
2472 while (!pci_is_root_bus(dev->bus)) {
2473 pin = pci_swizzle_interrupt_pin(dev, pin);
2474 dev = dev->bus->self;
2475 }
2476 *bridge = dev;
2477 return pin;
2478}
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2489{
2490 u8 pin = *pinp;
2491
2492 while (!pci_is_root_bus(dev->bus)) {
2493 pin = pci_swizzle_interrupt_pin(dev, pin);
2494 dev = dev->bus->self;
2495 }
2496 *pinp = pin;
2497 return PCI_SLOT(dev->devfn);
2498}
2499EXPORT_SYMBOL_GPL(pci_common_swizzle);
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510void pci_release_region(struct pci_dev *pdev, int bar)
2511{
2512 struct pci_devres *dr;
2513
2514 if (pci_resource_len(pdev, bar) == 0)
2515 return;
2516 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2517 release_region(pci_resource_start(pdev, bar),
2518 pci_resource_len(pdev, bar));
2519 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2520 release_mem_region(pci_resource_start(pdev, bar),
2521 pci_resource_len(pdev, bar));
2522
2523 dr = find_pci_dr(pdev);
2524 if (dr)
2525 dr->region_mask &= ~(1 << bar);
2526}
2527EXPORT_SYMBOL(pci_release_region);
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548static int __pci_request_region(struct pci_dev *pdev, int bar,
2549 const char *res_name, int exclusive)
2550{
2551 struct pci_devres *dr;
2552
2553 if (pci_resource_len(pdev, bar) == 0)
2554 return 0;
2555
2556 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2557 if (!request_region(pci_resource_start(pdev, bar),
2558 pci_resource_len(pdev, bar), res_name))
2559 goto err_out;
2560 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2561 if (!__request_mem_region(pci_resource_start(pdev, bar),
2562 pci_resource_len(pdev, bar), res_name,
2563 exclusive))
2564 goto err_out;
2565 }
2566
2567 dr = find_pci_dr(pdev);
2568 if (dr)
2569 dr->region_mask |= 1 << bar;
2570
2571 return 0;
2572
2573err_out:
2574 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2575 &pdev->resource[bar]);
2576 return -EBUSY;
2577}
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2594{
2595 return __pci_request_region(pdev, bar, res_name, 0);
2596}
2597EXPORT_SYMBOL(pci_request_region);
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
2618 const char *res_name)
2619{
2620 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2621}
2622EXPORT_SYMBOL(pci_request_region_exclusive);
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2633{
2634 int i;
2635
2636 for (i = 0; i < 6; i++)
2637 if (bars & (1 << i))
2638 pci_release_region(pdev, i);
2639}
2640EXPORT_SYMBOL(pci_release_selected_regions);
2641
2642static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2643 const char *res_name, int excl)
2644{
2645 int i;
2646
2647 for (i = 0; i < 6; i++)
2648 if (bars & (1 << i))
2649 if (__pci_request_region(pdev, i, res_name, excl))
2650 goto err_out;
2651 return 0;
2652
2653err_out:
2654 while (--i >= 0)
2655 if (bars & (1 << i))
2656 pci_release_region(pdev, i);
2657
2658 return -EBUSY;
2659}
2660
2661
2662
2663
2664
2665
2666
2667
2668int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2669 const char *res_name)
2670{
2671 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2672}
2673EXPORT_SYMBOL(pci_request_selected_regions);
2674
2675int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
2676 const char *res_name)
2677{
2678 return __pci_request_selected_regions(pdev, bars, res_name,
2679 IORESOURCE_EXCLUSIVE);
2680}
2681EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692void pci_release_regions(struct pci_dev *pdev)
2693{
2694 pci_release_selected_regions(pdev, (1 << 6) - 1);
2695}
2696EXPORT_SYMBOL(pci_release_regions);
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2712{
2713 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2714}
2715EXPORT_SYMBOL(pci_request_regions);
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2734{
2735 return pci_request_selected_regions_exclusive(pdev,
2736 ((1 << 6) - 1), res_name);
2737}
2738EXPORT_SYMBOL(pci_request_regions_exclusive);
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
2751{
2752#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
2753 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
2754
2755 if (!(res->flags & IORESOURCE_IO))
2756 return -EINVAL;
2757
2758 if (res->end > IO_SPACE_LIMIT)
2759 return -EINVAL;
2760
2761 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
2762 pgprot_device(PAGE_KERNEL));
2763#else
2764
2765
2766 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
2767 return -ENODEV;
2768#endif
2769}
2770
2771static void __pci_set_master(struct pci_dev *dev, bool enable)
2772{
2773 u16 old_cmd, cmd;
2774
2775 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2776 if (enable)
2777 cmd = old_cmd | PCI_COMMAND_MASTER;
2778 else
2779 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2780 if (cmd != old_cmd) {
2781 dev_dbg(&dev->dev, "%s bus mastering\n",
2782 enable ? "enabling" : "disabling");
2783 pci_write_config_word(dev, PCI_COMMAND, cmd);
2784 }
2785 dev->is_busmaster = enable;
2786}
2787
2788
2789
2790
2791
2792
2793
2794
2795char * __weak __init pcibios_setup(char *str)
2796{
2797 return str;
2798}
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808void __weak pcibios_set_master(struct pci_dev *dev)
2809{
2810 u8 lat;
2811
2812
2813 if (pci_is_pcie(dev))
2814 return;
2815
2816 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2817 if (lat < 16)
2818 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2819 else if (lat > pcibios_max_latency)
2820 lat = pcibios_max_latency;
2821 else
2822 return;
2823
2824 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2825}
2826
2827
2828
2829
2830
2831
2832
2833
2834void pci_set_master(struct pci_dev *dev)
2835{
2836 __pci_set_master(dev, true);
2837 pcibios_set_master(dev);
2838}
2839EXPORT_SYMBOL(pci_set_master);
2840
2841
2842
2843
2844
2845void pci_clear_master(struct pci_dev *dev)
2846{
2847 __pci_set_master(dev, false);
2848}
2849EXPORT_SYMBOL(pci_clear_master);
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861int pci_set_cacheline_size(struct pci_dev *dev)
2862{
2863 u8 cacheline_size;
2864
2865 if (!pci_cache_line_size)
2866 return -EINVAL;
2867
2868
2869
2870 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2871 if (cacheline_size >= pci_cache_line_size &&
2872 (cacheline_size % pci_cache_line_size) == 0)
2873 return 0;
2874
2875
2876 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2877
2878 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2879 if (cacheline_size == pci_cache_line_size)
2880 return 0;
2881
2882 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
2883 pci_cache_line_size << 2);
2884
2885 return -EINVAL;
2886}
2887EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897int pci_set_mwi(struct pci_dev *dev)
2898{
2899#ifdef PCI_DISABLE_MWI
2900 return 0;
2901#else
2902 int rc;
2903 u16 cmd;
2904
2905 rc = pci_set_cacheline_size(dev);
2906 if (rc)
2907 return rc;
2908
2909 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2910 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
2911 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2912 cmd |= PCI_COMMAND_INVALIDATE;
2913 pci_write_config_word(dev, PCI_COMMAND, cmd);
2914 }
2915 return 0;
2916#endif
2917}
2918EXPORT_SYMBOL(pci_set_mwi);
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929int pci_try_set_mwi(struct pci_dev *dev)
2930{
2931#ifdef PCI_DISABLE_MWI
2932 return 0;
2933#else
2934 return pci_set_mwi(dev);
2935#endif
2936}
2937EXPORT_SYMBOL(pci_try_set_mwi);
2938
2939
2940
2941
2942
2943
2944
2945void pci_clear_mwi(struct pci_dev *dev)
2946{
2947#ifndef PCI_DISABLE_MWI
2948 u16 cmd;
2949
2950 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2951 if (cmd & PCI_COMMAND_INVALIDATE) {
2952 cmd &= ~PCI_COMMAND_INVALIDATE;
2953 pci_write_config_word(dev, PCI_COMMAND, cmd);
2954 }
2955#endif
2956}
2957EXPORT_SYMBOL(pci_clear_mwi);
2958
2959
2960
2961
2962
2963
2964
2965
2966void pci_intx(struct pci_dev *pdev, int enable)
2967{
2968 u16 pci_command, new;
2969
2970 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2971
2972 if (enable)
2973 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2974 else
2975 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2976
2977 if (new != pci_command) {
2978 struct pci_devres *dr;
2979
2980 pci_write_config_word(pdev, PCI_COMMAND, new);
2981
2982 dr = find_pci_dr(pdev);
2983 if (dr && !dr->restore_intx) {
2984 dr->restore_intx = 1;
2985 dr->orig_intx = !enable;
2986 }
2987 }
2988}
2989EXPORT_SYMBOL_GPL(pci_intx);
2990
2991
2992
2993
2994
2995
2996
2997
2998bool pci_intx_mask_supported(struct pci_dev *dev)
2999{
3000 bool mask_supported = false;
3001 u16 orig, new;
3002
3003 if (dev->broken_intx_masking)
3004 return false;
3005
3006 pci_cfg_access_lock(dev);
3007
3008 pci_read_config_word(dev, PCI_COMMAND, &orig);
3009 pci_write_config_word(dev, PCI_COMMAND,
3010 orig ^ PCI_COMMAND_INTX_DISABLE);
3011 pci_read_config_word(dev, PCI_COMMAND, &new);
3012
3013
3014
3015
3016
3017
3018 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3019 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3020 orig, new);
3021 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3022 mask_supported = true;
3023 pci_write_config_word(dev, PCI_COMMAND, orig);
3024 }
3025
3026 pci_cfg_access_unlock(dev);
3027 return mask_supported;
3028}
3029EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3030
3031static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3032{
3033 struct pci_bus *bus = dev->bus;
3034 bool mask_updated = true;
3035 u32 cmd_status_dword;
3036 u16 origcmd, newcmd;
3037 unsigned long flags;
3038 bool irq_pending;
3039
3040
3041
3042
3043
3044 BUILD_BUG_ON(PCI_COMMAND % 4);
3045 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3046
3047 raw_spin_lock_irqsave(&pci_lock, flags);
3048
3049 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3050
3051 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3052
3053
3054
3055
3056
3057
3058 if (mask != irq_pending) {
3059 mask_updated = false;
3060 goto done;
3061 }
3062
3063 origcmd = cmd_status_dword;
3064 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3065 if (mask)
3066 newcmd |= PCI_COMMAND_INTX_DISABLE;
3067 if (newcmd != origcmd)
3068 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3069
3070done:
3071 raw_spin_unlock_irqrestore(&pci_lock, flags);
3072
3073 return mask_updated;
3074}
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084bool pci_check_and_mask_intx(struct pci_dev *dev)
3085{
3086 return pci_check_and_set_intx_mask(dev, true);
3087}
3088EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098bool pci_check_and_unmask_intx(struct pci_dev *dev)
3099{
3100 return pci_check_and_set_intx_mask(dev, false);
3101}
3102EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112void pci_msi_off(struct pci_dev *dev)
3113{
3114 int pos;
3115 u16 control;
3116
3117
3118
3119
3120
3121
3122 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3123 if (pos) {
3124 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3125 control &= ~PCI_MSI_FLAGS_ENABLE;
3126 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3127 }
3128 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3129 if (pos) {
3130 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3131 control &= ~PCI_MSIX_FLAGS_ENABLE;
3132 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3133 }
3134}
3135EXPORT_SYMBOL_GPL(pci_msi_off);
3136
3137int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3138{
3139 return dma_set_max_seg_size(&dev->dev, size);
3140}
3141EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3142
3143int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3144{
3145 return dma_set_seg_boundary(&dev->dev, mask);
3146}
3147EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3148
3149
3150
3151
3152
3153
3154
3155int pci_wait_for_pending_transaction(struct pci_dev *dev)
3156{
3157 if (!pci_is_pcie(dev))
3158 return 1;
3159
3160 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3161 PCI_EXP_DEVSTA_TRPND);
3162}
3163EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3164
3165static int pcie_flr(struct pci_dev *dev, int probe)
3166{
3167 u32 cap;
3168
3169 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3170 if (!(cap & PCI_EXP_DEVCAP_FLR))
3171 return -ENOTTY;
3172
3173 if (probe)
3174 return 0;
3175
3176 if (!pci_wait_for_pending_transaction(dev))
3177 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3178
3179 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3180 msleep(100);
3181 return 0;
3182}
3183
3184static int pci_af_flr(struct pci_dev *dev, int probe)
3185{
3186 int pos;
3187 u8 cap;
3188
3189 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3190 if (!pos)
3191 return -ENOTTY;
3192
3193 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3194 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3195 return -ENOTTY;
3196
3197 if (probe)
3198 return 0;
3199
3200
3201
3202
3203
3204
3205 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3206 PCI_AF_STATUS_TP << 8))
3207 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3208
3209 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3210 msleep(100);
3211 return 0;
3212}
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229static int pci_pm_reset(struct pci_dev *dev, int probe)
3230{
3231 u16 csr;
3232
3233 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3234 return -ENOTTY;
3235
3236 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3237 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3238 return -ENOTTY;
3239
3240 if (probe)
3241 return 0;
3242
3243 if (dev->current_state != PCI_D0)
3244 return -EINVAL;
3245
3246 csr &= ~PCI_PM_CTRL_STATE_MASK;
3247 csr |= PCI_D3hot;
3248 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3249 pci_dev_d3_sleep(dev);
3250
3251 csr &= ~PCI_PM_CTRL_STATE_MASK;
3252 csr |= PCI_D0;
3253 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3254 pci_dev_d3_sleep(dev);
3255
3256 return 0;
3257}
3258
3259void pci_reset_secondary_bus(struct pci_dev *dev)
3260{
3261 u16 ctrl;
3262
3263 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3264 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3265 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3266
3267
3268
3269
3270 msleep(2);
3271
3272 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3273 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3274
3275
3276
3277
3278
3279
3280
3281
3282 ssleep(1);
3283}
3284
3285void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3286{
3287 pci_reset_secondary_bus(dev);
3288}
3289
3290
3291
3292
3293
3294
3295
3296
3297void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3298{
3299 pcibios_reset_secondary_bus(dev);
3300}
3301EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3302
3303static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3304{
3305 struct pci_dev *pdev;
3306
3307 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3308 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3309 return -ENOTTY;
3310
3311 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3312 if (pdev != dev)
3313 return -ENOTTY;
3314
3315 if (probe)
3316 return 0;
3317
3318 pci_reset_bridge_secondary_bus(dev->bus->self);
3319
3320 return 0;
3321}
3322
3323static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3324{
3325 int rc = -ENOTTY;
3326
3327 if (!hotplug || !try_module_get(hotplug->ops->owner))
3328 return rc;
3329
3330 if (hotplug->ops->reset_slot)
3331 rc = hotplug->ops->reset_slot(hotplug, probe);
3332
3333 module_put(hotplug->ops->owner);
3334
3335 return rc;
3336}
3337
3338static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3339{
3340 struct pci_dev *pdev;
3341
3342 if (dev->subordinate || !dev->slot ||
3343 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3344 return -ENOTTY;
3345
3346 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3347 if (pdev != dev && pdev->slot == dev->slot)
3348 return -ENOTTY;
3349
3350 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3351}
3352
3353static int __pci_dev_reset(struct pci_dev *dev, int probe)
3354{
3355 int rc;
3356
3357 might_sleep();
3358
3359 rc = pci_dev_specific_reset(dev, probe);
3360 if (rc != -ENOTTY)
3361 goto done;
3362
3363 rc = pcie_flr(dev, probe);
3364 if (rc != -ENOTTY)
3365 goto done;
3366
3367 rc = pci_af_flr(dev, probe);
3368 if (rc != -ENOTTY)
3369 goto done;
3370
3371 rc = pci_pm_reset(dev, probe);
3372 if (rc != -ENOTTY)
3373 goto done;
3374
3375 rc = pci_dev_reset_slot_function(dev, probe);
3376 if (rc != -ENOTTY)
3377 goto done;
3378
3379 rc = pci_parent_bus_reset(dev, probe);
3380done:
3381 return rc;
3382}
3383
3384static void pci_dev_lock(struct pci_dev *dev)
3385{
3386 pci_cfg_access_lock(dev);
3387
3388 device_lock(&dev->dev);
3389}
3390
3391
3392static int pci_dev_trylock(struct pci_dev *dev)
3393{
3394 if (pci_cfg_access_trylock(dev)) {
3395 if (device_trylock(&dev->dev))
3396 return 1;
3397 pci_cfg_access_unlock(dev);
3398 }
3399
3400 return 0;
3401}
3402
3403static void pci_dev_unlock(struct pci_dev *dev)
3404{
3405 device_unlock(&dev->dev);
3406 pci_cfg_access_unlock(dev);
3407}
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418static void pci_reset_notify(struct pci_dev *dev, bool prepare)
3419{
3420 const struct pci_error_handlers *err_handler =
3421 dev->driver ? dev->driver->err_handler : NULL;
3422 if (err_handler && err_handler->reset_notify)
3423 err_handler->reset_notify(dev, prepare);
3424}
3425
3426static void pci_dev_save_and_disable(struct pci_dev *dev)
3427{
3428 pci_reset_notify(dev, true);
3429
3430
3431
3432
3433
3434
3435 pci_set_power_state(dev, PCI_D0);
3436
3437 pci_save_state(dev);
3438
3439
3440
3441
3442
3443
3444
3445 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3446}
3447
3448static void pci_dev_restore(struct pci_dev *dev)
3449{
3450 pci_restore_state(dev);
3451 pci_reset_notify(dev, false);
3452}
3453
3454static int pci_dev_reset(struct pci_dev *dev, int probe)
3455{
3456 int rc;
3457
3458 if (!probe)
3459 pci_dev_lock(dev);
3460
3461 rc = __pci_dev_reset(dev, probe);
3462
3463 if (!probe)
3464 pci_dev_unlock(dev);
3465
3466 return rc;
3467}
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486int __pci_reset_function(struct pci_dev *dev)
3487{
3488 return pci_dev_reset(dev, 0);
3489}
3490EXPORT_SYMBOL_GPL(__pci_reset_function);
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511int __pci_reset_function_locked(struct pci_dev *dev)
3512{
3513 return __pci_dev_reset(dev, 0);
3514}
3515EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528int pci_probe_reset_function(struct pci_dev *dev)
3529{
3530 return pci_dev_reset(dev, 1);
3531}
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549int pci_reset_function(struct pci_dev *dev)
3550{
3551 int rc;
3552
3553 rc = pci_dev_reset(dev, 1);
3554 if (rc)
3555 return rc;
3556
3557 pci_dev_save_and_disable(dev);
3558
3559 rc = pci_dev_reset(dev, 0);
3560
3561 pci_dev_restore(dev);
3562
3563 return rc;
3564}
3565EXPORT_SYMBOL_GPL(pci_reset_function);
3566
3567
3568
3569
3570
3571
3572
3573int pci_try_reset_function(struct pci_dev *dev)
3574{
3575 int rc;
3576
3577 rc = pci_dev_reset(dev, 1);
3578 if (rc)
3579 return rc;
3580
3581 pci_dev_save_and_disable(dev);
3582
3583 if (pci_dev_trylock(dev)) {
3584 rc = __pci_dev_reset(dev, 0);
3585 pci_dev_unlock(dev);
3586 } else
3587 rc = -EAGAIN;
3588
3589 pci_dev_restore(dev);
3590
3591 return rc;
3592}
3593EXPORT_SYMBOL_GPL(pci_try_reset_function);
3594
3595
3596static bool pci_bus_resetable(struct pci_bus *bus)
3597{
3598 struct pci_dev *dev;
3599
3600 list_for_each_entry(dev, &bus->devices, bus_list) {
3601 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
3602 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
3603 return false;
3604 }
3605
3606 return true;
3607}
3608
3609
3610static void pci_bus_lock(struct pci_bus *bus)
3611{
3612 struct pci_dev *dev;
3613
3614 list_for_each_entry(dev, &bus->devices, bus_list) {
3615 pci_dev_lock(dev);
3616 if (dev->subordinate)
3617 pci_bus_lock(dev->subordinate);
3618 }
3619}
3620
3621
3622static void pci_bus_unlock(struct pci_bus *bus)
3623{
3624 struct pci_dev *dev;
3625
3626 list_for_each_entry(dev, &bus->devices, bus_list) {
3627 if (dev->subordinate)
3628 pci_bus_unlock(dev->subordinate);
3629 pci_dev_unlock(dev);
3630 }
3631}
3632
3633
3634static int pci_bus_trylock(struct pci_bus *bus)
3635{
3636 struct pci_dev *dev;
3637
3638 list_for_each_entry(dev, &bus->devices, bus_list) {
3639 if (!pci_dev_trylock(dev))
3640 goto unlock;
3641 if (dev->subordinate) {
3642 if (!pci_bus_trylock(dev->subordinate)) {
3643 pci_dev_unlock(dev);
3644 goto unlock;
3645 }
3646 }
3647 }
3648 return 1;
3649
3650unlock:
3651 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
3652 if (dev->subordinate)
3653 pci_bus_unlock(dev->subordinate);
3654 pci_dev_unlock(dev);
3655 }
3656 return 0;
3657}
3658
3659
3660static bool pci_slot_resetable(struct pci_slot *slot)
3661{
3662 struct pci_dev *dev;
3663
3664 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3665 if (!dev->slot || dev->slot != slot)
3666 continue;
3667 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
3668 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
3669 return false;
3670 }
3671
3672 return true;
3673}
3674
3675
3676static void pci_slot_lock(struct pci_slot *slot)
3677{
3678 struct pci_dev *dev;
3679
3680 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3681 if (!dev->slot || dev->slot != slot)
3682 continue;
3683 pci_dev_lock(dev);
3684 if (dev->subordinate)
3685 pci_bus_lock(dev->subordinate);
3686 }
3687}
3688
3689
3690static void pci_slot_unlock(struct pci_slot *slot)
3691{
3692 struct pci_dev *dev;
3693
3694 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3695 if (!dev->slot || dev->slot != slot)
3696 continue;
3697 if (dev->subordinate)
3698 pci_bus_unlock(dev->subordinate);
3699 pci_dev_unlock(dev);
3700 }
3701}
3702
3703
3704static int pci_slot_trylock(struct pci_slot *slot)
3705{
3706 struct pci_dev *dev;
3707
3708 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3709 if (!dev->slot || dev->slot != slot)
3710 continue;
3711 if (!pci_dev_trylock(dev))
3712 goto unlock;
3713 if (dev->subordinate) {
3714 if (!pci_bus_trylock(dev->subordinate)) {
3715 pci_dev_unlock(dev);
3716 goto unlock;
3717 }
3718 }
3719 }
3720 return 1;
3721
3722unlock:
3723 list_for_each_entry_continue_reverse(dev,
3724 &slot->bus->devices, bus_list) {
3725 if (!dev->slot || dev->slot != slot)
3726 continue;
3727 if (dev->subordinate)
3728 pci_bus_unlock(dev->subordinate);
3729 pci_dev_unlock(dev);
3730 }
3731 return 0;
3732}
3733
3734
3735static void pci_bus_save_and_disable(struct pci_bus *bus)
3736{
3737 struct pci_dev *dev;
3738
3739 list_for_each_entry(dev, &bus->devices, bus_list) {
3740 pci_dev_save_and_disable(dev);
3741 if (dev->subordinate)
3742 pci_bus_save_and_disable(dev->subordinate);
3743 }
3744}
3745
3746
3747
3748
3749
3750static void pci_bus_restore(struct pci_bus *bus)
3751{
3752 struct pci_dev *dev;
3753
3754 list_for_each_entry(dev, &bus->devices, bus_list) {
3755 pci_dev_restore(dev);
3756 if (dev->subordinate)
3757 pci_bus_restore(dev->subordinate);
3758 }
3759}
3760
3761
3762static void pci_slot_save_and_disable(struct pci_slot *slot)
3763{
3764 struct pci_dev *dev;
3765
3766 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3767 if (!dev->slot || dev->slot != slot)
3768 continue;
3769 pci_dev_save_and_disable(dev);
3770 if (dev->subordinate)
3771 pci_bus_save_and_disable(dev->subordinate);
3772 }
3773}
3774
3775
3776
3777
3778
3779static void pci_slot_restore(struct pci_slot *slot)
3780{
3781 struct pci_dev *dev;
3782
3783 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3784 if (!dev->slot || dev->slot != slot)
3785 continue;
3786 pci_dev_restore(dev);
3787 if (dev->subordinate)
3788 pci_bus_restore(dev->subordinate);
3789 }
3790}
3791
3792static int pci_slot_reset(struct pci_slot *slot, int probe)
3793{
3794 int rc;
3795
3796 if (!slot || !pci_slot_resetable(slot))
3797 return -ENOTTY;
3798
3799 if (!probe)
3800 pci_slot_lock(slot);
3801
3802 might_sleep();
3803
3804 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3805
3806 if (!probe)
3807 pci_slot_unlock(slot);
3808
3809 return rc;
3810}
3811
3812
3813
3814
3815
3816
3817
3818int pci_probe_reset_slot(struct pci_slot *slot)
3819{
3820 return pci_slot_reset(slot, 1);
3821}
3822EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839int pci_reset_slot(struct pci_slot *slot)
3840{
3841 int rc;
3842
3843 rc = pci_slot_reset(slot, 1);
3844 if (rc)
3845 return rc;
3846
3847 pci_slot_save_and_disable(slot);
3848
3849 rc = pci_slot_reset(slot, 0);
3850
3851 pci_slot_restore(slot);
3852
3853 return rc;
3854}
3855EXPORT_SYMBOL_GPL(pci_reset_slot);
3856
3857
3858
3859
3860
3861
3862
3863int pci_try_reset_slot(struct pci_slot *slot)
3864{
3865 int rc;
3866
3867 rc = pci_slot_reset(slot, 1);
3868 if (rc)
3869 return rc;
3870
3871 pci_slot_save_and_disable(slot);
3872
3873 if (pci_slot_trylock(slot)) {
3874 might_sleep();
3875 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
3876 pci_slot_unlock(slot);
3877 } else
3878 rc = -EAGAIN;
3879
3880 pci_slot_restore(slot);
3881
3882 return rc;
3883}
3884EXPORT_SYMBOL_GPL(pci_try_reset_slot);
3885
3886static int pci_bus_reset(struct pci_bus *bus, int probe)
3887{
3888 if (!bus->self || !pci_bus_resetable(bus))
3889 return -ENOTTY;
3890
3891 if (probe)
3892 return 0;
3893
3894 pci_bus_lock(bus);
3895
3896 might_sleep();
3897
3898 pci_reset_bridge_secondary_bus(bus->self);
3899
3900 pci_bus_unlock(bus);
3901
3902 return 0;
3903}
3904
3905
3906
3907
3908
3909
3910
3911int pci_probe_reset_bus(struct pci_bus *bus)
3912{
3913 return pci_bus_reset(bus, 1);
3914}
3915EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926int pci_reset_bus(struct pci_bus *bus)
3927{
3928 int rc;
3929
3930 rc = pci_bus_reset(bus, 1);
3931 if (rc)
3932 return rc;
3933
3934 pci_bus_save_and_disable(bus);
3935
3936 rc = pci_bus_reset(bus, 0);
3937
3938 pci_bus_restore(bus);
3939
3940 return rc;
3941}
3942EXPORT_SYMBOL_GPL(pci_reset_bus);
3943
3944
3945
3946
3947
3948
3949
3950int pci_try_reset_bus(struct pci_bus *bus)
3951{
3952 int rc;
3953
3954 rc = pci_bus_reset(bus, 1);
3955 if (rc)
3956 return rc;
3957
3958 pci_bus_save_and_disable(bus);
3959
3960 if (pci_bus_trylock(bus)) {
3961 might_sleep();
3962 pci_reset_bridge_secondary_bus(bus->self);
3963 pci_bus_unlock(bus);
3964 } else
3965 rc = -EAGAIN;
3966
3967 pci_bus_restore(bus);
3968
3969 return rc;
3970}
3971EXPORT_SYMBOL_GPL(pci_try_reset_bus);
3972
3973
3974
3975
3976
3977
3978
3979
3980int pcix_get_max_mmrbc(struct pci_dev *dev)
3981{
3982 int cap;
3983 u32 stat;
3984
3985 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3986 if (!cap)
3987 return -EINVAL;
3988
3989 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3990 return -EINVAL;
3991
3992 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3993}
3994EXPORT_SYMBOL(pcix_get_max_mmrbc);
3995
3996
3997
3998
3999
4000
4001
4002
4003int pcix_get_mmrbc(struct pci_dev *dev)
4004{
4005 int cap;
4006 u16 cmd;
4007
4008 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4009 if (!cap)
4010 return -EINVAL;
4011
4012 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4013 return -EINVAL;
4014
4015 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4016}
4017EXPORT_SYMBOL(pcix_get_mmrbc);
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4029{
4030 int cap;
4031 u32 stat, v, o;
4032 u16 cmd;
4033
4034 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4035 return -EINVAL;
4036
4037 v = ffs(mmrbc) - 10;
4038
4039 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4040 if (!cap)
4041 return -EINVAL;
4042
4043 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4044 return -EINVAL;
4045
4046 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4047 return -E2BIG;
4048
4049 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4050 return -EINVAL;
4051
4052 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4053 if (o != v) {
4054 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4055 return -EIO;
4056
4057 cmd &= ~PCI_X_CMD_MAX_READ;
4058 cmd |= v << 2;
4059 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4060 return -EIO;
4061 }
4062 return 0;
4063}
4064EXPORT_SYMBOL(pcix_set_mmrbc);
4065
4066
4067
4068
4069
4070
4071
4072
4073int pcie_get_readrq(struct pci_dev *dev)
4074{
4075 u16 ctl;
4076
4077 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4078
4079 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4080}
4081EXPORT_SYMBOL(pcie_get_readrq);
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091int pcie_set_readrq(struct pci_dev *dev, int rq)
4092{
4093 u16 v;
4094
4095 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4096 return -EINVAL;
4097
4098
4099
4100
4101
4102
4103
4104 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4105 int mps = pcie_get_mps(dev);
4106
4107 if (mps < rq)
4108 rq = mps;
4109 }
4110
4111 v = (ffs(rq) - 8) << 12;
4112
4113 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4114 PCI_EXP_DEVCTL_READRQ, v);
4115}
4116EXPORT_SYMBOL(pcie_set_readrq);
4117
4118
4119
4120
4121
4122
4123
4124int pcie_get_mps(struct pci_dev *dev)
4125{
4126 u16 ctl;
4127
4128 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4129
4130 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4131}
4132EXPORT_SYMBOL(pcie_get_mps);
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142int pcie_set_mps(struct pci_dev *dev, int mps)
4143{
4144 u16 v;
4145
4146 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4147 return -EINVAL;
4148
4149 v = ffs(mps) - 8;
4150 if (v > dev->pcie_mpss)
4151 return -EINVAL;
4152 v <<= 5;
4153
4154 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4155 PCI_EXP_DEVCTL_PAYLOAD, v);
4156}
4157EXPORT_SYMBOL(pcie_set_mps);
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4169 enum pcie_link_width *width)
4170{
4171 int ret;
4172
4173 *speed = PCI_SPEED_UNKNOWN;
4174 *width = PCIE_LNK_WIDTH_UNKNOWN;
4175
4176 while (dev) {
4177 u16 lnksta;
4178 enum pci_bus_speed next_speed;
4179 enum pcie_link_width next_width;
4180
4181 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4182 if (ret)
4183 return ret;
4184
4185 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4186 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4187 PCI_EXP_LNKSTA_NLW_SHIFT;
4188
4189 if (next_speed < *speed)
4190 *speed = next_speed;
4191
4192 if (next_width < *width)
4193 *width = next_width;
4194
4195 dev = dev->bus->self;
4196 }
4197
4198 return 0;
4199}
4200EXPORT_SYMBOL(pcie_get_minimum_link);
4201
4202
4203
4204
4205
4206
4207
4208
4209int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4210{
4211 int i, bars = 0;
4212 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4213 if (pci_resource_flags(dev, i) & flags)
4214 bars |= (1 << i);
4215 return bars;
4216}
4217EXPORT_SYMBOL(pci_select_bars);
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4228{
4229 int reg;
4230
4231 if (resno < PCI_ROM_RESOURCE) {
4232 *type = pci_bar_unknown;
4233 return PCI_BASE_ADDRESS_0 + 4 * resno;
4234 } else if (resno == PCI_ROM_RESOURCE) {
4235 *type = pci_bar_mem32;
4236 return dev->rom_base_reg;
4237 } else if (resno < PCI_BRIDGE_RESOURCES) {
4238
4239 *type = pci_bar_unknown;
4240 reg = pci_iov_resource_bar(dev, resno);
4241 if (reg)
4242 return reg;
4243 }
4244
4245 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4246 return 0;
4247}
4248
4249
4250static arch_set_vga_state_t arch_set_vga_state;
4251
4252void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4253{
4254 arch_set_vga_state = func;
4255}
4256
4257static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4258 unsigned int command_bits, u32 flags)
4259{
4260 if (arch_set_vga_state)
4261 return arch_set_vga_state(dev, decode, command_bits,
4262 flags);
4263 return 0;
4264}
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274int pci_set_vga_state(struct pci_dev *dev, bool decode,
4275 unsigned int command_bits, u32 flags)
4276{
4277 struct pci_bus *bus;
4278 struct pci_dev *bridge;
4279 u16 cmd;
4280 int rc;
4281
4282 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4283
4284
4285 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4286 if (rc)
4287 return rc;
4288
4289 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4290 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4291 if (decode == true)
4292 cmd |= command_bits;
4293 else
4294 cmd &= ~command_bits;
4295 pci_write_config_word(dev, PCI_COMMAND, cmd);
4296 }
4297
4298 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4299 return 0;
4300
4301 bus = dev->bus;
4302 while (bus) {
4303 bridge = bus->self;
4304 if (bridge) {
4305 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4306 &cmd);
4307 if (decode == true)
4308 cmd |= PCI_BRIDGE_CTL_VGA;
4309 else
4310 cmd &= ~PCI_BRIDGE_CTL_VGA;
4311 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4312 cmd);
4313 }
4314 bus = bus->parent;
4315 }
4316 return 0;
4317}
4318
4319bool pci_device_is_present(struct pci_dev *pdev)
4320{
4321 u32 v;
4322
4323 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4324}
4325EXPORT_SYMBOL_GPL(pci_device_is_present);
4326
4327#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4328static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4329static DEFINE_SPINLOCK(resource_alignment_lock);
4330
4331
4332
4333
4334
4335
4336
4337
4338static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4339{
4340 int seg, bus, slot, func, align_order, count;
4341 resource_size_t align = 0;
4342 char *p;
4343
4344 spin_lock(&resource_alignment_lock);
4345 p = resource_alignment_param;
4346 while (*p) {
4347 count = 0;
4348 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4349 p[count] == '@') {
4350 p += count + 1;
4351 } else {
4352 align_order = -1;
4353 }
4354 if (sscanf(p, "%x:%x:%x.%x%n",
4355 &seg, &bus, &slot, &func, &count) != 4) {
4356 seg = 0;
4357 if (sscanf(p, "%x:%x.%x%n",
4358 &bus, &slot, &func, &count) != 3) {
4359
4360 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4361 p);
4362 break;
4363 }
4364 }
4365 p += count;
4366 if (seg == pci_domain_nr(dev->bus) &&
4367 bus == dev->bus->number &&
4368 slot == PCI_SLOT(dev->devfn) &&
4369 func == PCI_FUNC(dev->devfn)) {
4370 if (align_order == -1)
4371 align = PAGE_SIZE;
4372 else
4373 align = 1 << align_order;
4374
4375 break;
4376 }
4377 if (*p != ';' && *p != ',') {
4378
4379 break;
4380 }
4381 p++;
4382 }
4383 spin_unlock(&resource_alignment_lock);
4384 return align;
4385}
4386
4387
4388
4389
4390
4391
4392
4393
4394void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4395{
4396 int i;
4397 struct resource *r;
4398 resource_size_t align, size;
4399 u16 command;
4400
4401
4402 align = pci_specified_resource_alignment(dev);
4403 if (!align)
4404 return;
4405
4406 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4407 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4408 dev_warn(&dev->dev,
4409 "Can't reassign resources to host bridge.\n");
4410 return;
4411 }
4412
4413 dev_info(&dev->dev,
4414 "Disabling memory decoding and releasing memory resources.\n");
4415 pci_read_config_word(dev, PCI_COMMAND, &command);
4416 command &= ~PCI_COMMAND_MEMORY;
4417 pci_write_config_word(dev, PCI_COMMAND, command);
4418
4419 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4420 r = &dev->resource[i];
4421 if (!(r->flags & IORESOURCE_MEM))
4422 continue;
4423 size = resource_size(r);
4424 if (size < align) {
4425 size = align;
4426 dev_info(&dev->dev,
4427 "Rounding up size of resource #%d to %#llx.\n",
4428 i, (unsigned long long)size);
4429 }
4430 r->flags |= IORESOURCE_UNSET;
4431 r->end = size - 1;
4432 r->start = 0;
4433 }
4434
4435
4436
4437
4438 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4439 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4440 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4441 r = &dev->resource[i];
4442 if (!(r->flags & IORESOURCE_MEM))
4443 continue;
4444 r->flags |= IORESOURCE_UNSET;
4445 r->end = resource_size(r) - 1;
4446 r->start = 0;
4447 }
4448 pci_disable_bridge_window(dev);
4449 }
4450}
4451
4452static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4453{
4454 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4455 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4456 spin_lock(&resource_alignment_lock);
4457 strncpy(resource_alignment_param, buf, count);
4458 resource_alignment_param[count] = '\0';
4459 spin_unlock(&resource_alignment_lock);
4460 return count;
4461}
4462
4463static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4464{
4465 size_t count;
4466 spin_lock(&resource_alignment_lock);
4467 count = snprintf(buf, size, "%s", resource_alignment_param);
4468 spin_unlock(&resource_alignment_lock);
4469 return count;
4470}
4471
4472static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4473{
4474 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4475}
4476
4477static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4478 const char *buf, size_t count)
4479{
4480 return pci_set_resource_alignment_param(buf, count);
4481}
4482
4483BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4484 pci_resource_alignment_store);
4485
4486static int __init pci_resource_alignment_sysfs_init(void)
4487{
4488 return bus_create_file(&pci_bus_type,
4489 &bus_attr_resource_alignment);
4490}
4491late_initcall(pci_resource_alignment_sysfs_init);
4492
4493static void pci_no_domains(void)
4494{
4495#ifdef CONFIG_PCI_DOMAINS
4496 pci_domains_supported = 0;
4497#endif
4498}
4499
4500#ifdef CONFIG_PCI_DOMAINS
4501static atomic_t __domain_nr = ATOMIC_INIT(-1);
4502
4503int pci_get_new_domain_nr(void)
4504{
4505 return atomic_inc_return(&__domain_nr);
4506}
4507
4508#ifdef CONFIG_PCI_DOMAINS_GENERIC
4509void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
4510{
4511 static int use_dt_domains = -1;
4512 int domain = of_get_pci_domain_nr(parent->of_node);
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540 if (domain >= 0 && use_dt_domains) {
4541 use_dt_domains = 1;
4542 } else if (domain < 0 && use_dt_domains != 1) {
4543 use_dt_domains = 0;
4544 domain = pci_get_new_domain_nr();
4545 } else {
4546 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
4547 parent->of_node->full_name);
4548 domain = -1;
4549 }
4550
4551 bus->domain_nr = domain;
4552}
4553#endif
4554#endif
4555
4556
4557
4558
4559
4560
4561
4562
4563int __weak pci_ext_cfg_avail(void)
4564{
4565 return 1;
4566}
4567
4568void __weak pci_fixup_cardbus(struct pci_bus *bus)
4569{
4570}
4571EXPORT_SYMBOL(pci_fixup_cardbus);
4572
4573static int __init pci_setup(char *str)
4574{
4575 while (str) {
4576 char *k = strchr(str, ',');
4577 if (k)
4578 *k++ = 0;
4579 if (*str && (str = pcibios_setup(str)) && *str) {
4580 if (!strcmp(str, "nomsi")) {
4581 pci_no_msi();
4582 } else if (!strcmp(str, "noaer")) {
4583 pci_no_aer();
4584 } else if (!strncmp(str, "realloc=", 8)) {
4585 pci_realloc_get_opt(str + 8);
4586 } else if (!strncmp(str, "realloc", 7)) {
4587 pci_realloc_get_opt("on");
4588 } else if (!strcmp(str, "nodomains")) {
4589 pci_no_domains();
4590 } else if (!strncmp(str, "noari", 5)) {
4591 pcie_ari_disabled = true;
4592 } else if (!strncmp(str, "cbiosize=", 9)) {
4593 pci_cardbus_io_size = memparse(str + 9, &str);
4594 } else if (!strncmp(str, "cbmemsize=", 10)) {
4595 pci_cardbus_mem_size = memparse(str + 10, &str);
4596 } else if (!strncmp(str, "resource_alignment=", 19)) {
4597 pci_set_resource_alignment_param(str + 19,
4598 strlen(str + 19));
4599 } else if (!strncmp(str, "ecrc=", 5)) {
4600 pcie_ecrc_get_policy(str + 5);
4601 } else if (!strncmp(str, "hpiosize=", 9)) {
4602 pci_hotplug_io_size = memparse(str + 9, &str);
4603 } else if (!strncmp(str, "hpmemsize=", 10)) {
4604 pci_hotplug_mem_size = memparse(str + 10, &str);
4605 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4606 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4607 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4608 pcie_bus_config = PCIE_BUS_SAFE;
4609 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4610 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4611 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4612 pcie_bus_config = PCIE_BUS_PEER2PEER;
4613 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4614 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4615 } else {
4616 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4617 str);
4618 }
4619 }
4620 str = k;
4621 }
4622 return 0;
4623}
4624early_param("pci", pci_setup);
4625