LXR linux/drivers/staging/rtl8192u/r8192U.h

   1/*
   2 * This is part of rtl8187 OpenSource driver.
   3 * Copyright (C) Andrea Merello 2004-2005  <andrea.merello@gmail.com>
   4 * Released under the terms of GPL (General Public Licence)
   5 *
   6 * Parts of this driver are based on the GPL part of the
   7 * official realtek driver
   8 *
   9 * Parts of this driver are based on the rtl8192 driver skeleton
  10 * from Patric Schenke & Andres Salomon
  11 *
  12 * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13 *
  14 * We want to thank the Authors of those projects and the Ndiswrapper
  15 * project Authors.
  16 */
  17
  18#ifndef R819xU_H
  19#define R819xU_H
  20
  21#include <linux/module.h>
  22#include <linux/kernel.h>
  23#include <linux/ioport.h>
  24#include <linux/sched.h>
  25#include <linux/types.h>
  26#include <linux/slab.h>
  27#include <linux/netdevice.h>
  28#include <linux/usb.h>
  29#include <linux/etherdevice.h>
  30#include <linux/delay.h>
  31#include <linux/rtnetlink.h>
  32#include <linux/wireless.h>
  33#include <linux/timer.h>
  34#include <linux/proc_fs.h>
  35#include <linux/if_arp.h>
  36#include <linux/random.h>
  37#include <asm/io.h>
  38#include "ieee80211/ieee80211.h"
  39
  40#define RTL8192U
  41#define RTL819xU_MODULE_NAME "rtl819xU"
  42/* HW security */
  43#define MAX_KEY_LEN     61
  44#define KEY_BUF_SIZE    5
  45
  46#define BIT0            0x00000001
  47#define BIT1            0x00000002
  48#define BIT2            0x00000004
  49#define BIT3            0x00000008
  50#define BIT4            0x00000010
  51#define BIT5            0x00000020
  52#define BIT6            0x00000040
  53#define BIT7            0x00000080
  54#define BIT8            0x00000100
  55#define BIT9            0x00000200
  56#define BIT10           0x00000400
  57#define BIT11           0x00000800
  58#define BIT12           0x00001000
  59#define BIT13           0x00002000
  60#define BIT14           0x00004000
  61#define BIT15           0x00008000
  62#define BIT16           0x00010000
  63#define BIT17           0x00020000
  64#define BIT18           0x00040000
  65#define BIT19           0x00080000
  66#define BIT20           0x00100000
  67#define BIT21           0x00200000
  68#define BIT22           0x00400000
  69#define BIT23           0x00800000
  70#define BIT24           0x01000000
  71#define BIT25           0x02000000
  72#define BIT26           0x04000000
  73#define BIT27           0x08000000
  74#define BIT28           0x10000000
  75#define BIT29           0x20000000
  76#define BIT30           0x40000000
  77#define BIT31           0x80000000
  78
  79#define Rx_Smooth_Factor                20
  80#define DMESG(x, a...)
  81#define DMESGW(x, a...)
  82#define DMESGE(x, a...)
  83extern u32 rt_global_debug_component;
  84#define RT_TRACE(component, x, args...) \
  85        do {                                                    \
  86                if (rt_global_debug_component & component)      \
  87                        pr_debug("RTL8192U: " x "\n", ##args);  \
  88        } while (0)
  89
  90#define COMP_TRACE              BIT0  /* Function call tracing. */
  91#define COMP_DBG                BIT1
  92#define COMP_INIT               BIT2  /* Driver initialization/halt/reset. */
  93
  94
  95#define COMP_RECV               BIT3  /* Receive data path. */
  96#define COMP_SEND               BIT4  /* Send data path. */
  97#define COMP_IO                 BIT5
  98/* 802.11 Power Save mode or System/Device Power state. */
  99#define COMP_POWER              BIT6
 100/* 802.11 link related: join/start BSS, leave BSS. */
 101#define COMP_EPROM              BIT7
 102#define COMP_SWBW               BIT8  /* Bandwidth switch. */
 103#define COMP_POWER_TRACKING     BIT9  /* 8190 TX Power Tracking */
 104#define COMP_TURBO              BIT10 /* Turbo Mode */
 105#define COMP_QOS                BIT11
 106#define COMP_RATE               BIT12 /* Rate Adaptive mechanism */
 107#define COMP_RM                 BIT13 /* Radio Measurement */
 108#define COMP_DIG                BIT14
 109#define COMP_PHY                BIT15
 110#define COMP_CH                 BIT16 /* Channel setting debug */
 111#define COMP_TXAGC              BIT17 /* Tx power */
 112#define COMP_HIPWR              BIT18 /* High Power Mechanism */
 113#define COMP_HALDM              BIT19 /* HW Dynamic Mechanism */
 114#define COMP_SEC                BIT20 /* Event handling */
 115#define COMP_LED                BIT21
 116#define COMP_RF                 BIT22
 117#define COMP_RXDESC             BIT23 /* Rx desc information for SD3 debug */
 118
 119/* 11n or 8190 specific code */
 120
 121#define COMP_FIRMWARE           BIT24 /* Firmware downloading */
 122#define COMP_HT                 BIT25 /* 802.11n HT related information */
 123#define COMP_AMSDU              BIT26 /* A-MSDU Debugging */
 124#define COMP_SCAN               BIT27
 125#define COMP_DOWN               BIT29 /* rm driver module */
 126#define COMP_RESET              BIT30 /* Silent reset */
 127#define COMP_ERR                BIT31 /* Error out, always on */
 128
 129#define RTL819x_DEBUG
 130#ifdef RTL819x_DEBUG
 131#define RTL8192U_ASSERT(expr) \
 132        do {                                                            \
 133                if (!(expr)) {                                          \
 134                        pr_debug("Assertion failed! %s, %s, %s, line = %d\n", \
 135                                 #expr, __FILE__, __func__, __LINE__);  \
 136                }                                                       \
 137        } while (0)
 138/*
 139 * Debug out data buf.
 140 * If you want to print DATA buffer related BA,
 141 * please set ieee80211_debug_level to DATA|BA
 142 */
 143#define RT_DEBUG_DATA(level, data, datalen) \
 144        do {                                                            \
 145                if ((rt_global_debug_component & (level)) == (level)) { \
 146                        int i;                                          \
 147                        u8 *pdata = (u8 *) data;                        \
 148                        pr_debug("RTL8192U: %s()\n", __func__);         \
 149                        for (i = 0; i < (int)(datalen); i++) {          \
 150                                printk("%2x ", pdata[i]);               \
 151                                if ((i+1)%16 == 0)                      \
 152                                        printk("\n");                   \
 153                        }                                               \
 154                        printk("\n");                                   \
 155                }                                                       \
 156        } while (0)
 157#else
 158#define RTL8192U_ASSERT(expr) do {} while (0)
 159#define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
 160#endif /* RTL8169_DEBUG */
 161
 162
 163/* Queue Select Value in TxDesc */
 164#define QSLT_BK                                 0x1
 165#define QSLT_BE                                 0x0
 166#define QSLT_VI                                 0x4
 167#define QSLT_VO                                 0x6
 168#define QSLT_BEACON                             0x10
 169#define QSLT_HIGH                               0x11
 170#define QSLT_MGNT                               0x12
 171#define QSLT_CMD                                0x13
 172
 173#define DESC90_RATE1M                           0x00
 174#define DESC90_RATE2M                           0x01
 175#define DESC90_RATE5_5M                         0x02
 176#define DESC90_RATE11M                          0x03
 177#define DESC90_RATE6M                           0x04
 178#define DESC90_RATE9M                           0x05
 179#define DESC90_RATE12M                          0x06
 180#define DESC90_RATE18M                          0x07
 181#define DESC90_RATE24M                          0x08
 182#define DESC90_RATE36M                          0x09
 183#define DESC90_RATE48M                          0x0a
 184#define DESC90_RATE54M                          0x0b
 185#define DESC90_RATEMCS0                         0x00
 186#define DESC90_RATEMCS1                         0x01
 187#define DESC90_RATEMCS2                         0x02
 188#define DESC90_RATEMCS3                         0x03
 189#define DESC90_RATEMCS4                         0x04
 190#define DESC90_RATEMCS5                         0x05
 191#define DESC90_RATEMCS6                         0x06
 192#define DESC90_RATEMCS7                         0x07
 193#define DESC90_RATEMCS8                         0x08
 194#define DESC90_RATEMCS9                         0x09
 195#define DESC90_RATEMCS10                        0x0a
 196#define DESC90_RATEMCS11                        0x0b
 197#define DESC90_RATEMCS12                        0x0c
 198#define DESC90_RATEMCS13                        0x0d
 199#define DESC90_RATEMCS14                        0x0e
 200#define DESC90_RATEMCS15                        0x0f
 201#define DESC90_RATEMCS32                        0x20
 202
 203#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 204
 205#define IEEE80211_WATCH_DOG_TIME    2000
 206#define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 207/* For Tx Power Tracking */
 208#define         OFDM_Table_Length       19
 209#define CCK_Table_length        12
 210
 211/* For rtl819x */
 212typedef struct _tx_desc_819x_usb {
 213        /* DWORD 0 */
 214        u16     PktSize;
 215        u8      Offset;
 216        u8      Reserved0:3;
 217        u8      CmdInit:1;
 218        u8      LastSeg:1;
 219        u8      FirstSeg:1;
 220        u8      LINIP:1;
 221        u8      OWN:1;
 222
 223        /* DWORD 1 */
 224        u8      TxFWInfoSize;
 225        u8      RATid:3;
 226        u8      DISFB:1;
 227        u8      USERATE:1;
 228        u8      MOREFRAG:1;
 229        u8      NoEnc:1;
 230        u8      PIFS:1;
 231        u8      QueueSelect:5;
 232        u8      NoACM:1;
 233        u8      Reserved1:2;
 234        u8      SecCAMID:5;
 235        u8      SecDescAssign:1;
 236        u8      SecType:2;
 237
 238        /* DWORD 2 */
 239        u16     TxBufferSize;
 240        u8      ResvForPaddingLen:7;
 241        u8      Reserved3:1;
 242        u8      Reserved4;
 243
 244        /* DWORD 3, 4, 5 */
 245        u32     Reserved5;
 246        u32     Reserved6;
 247        u32     Reserved7;
 248} tx_desc_819x_usb, *ptx_desc_819x_usb;
 249
 250#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 251typedef struct _tx_desc_819x_usb_aggr_subframe {
 252        /* DWORD 0 */
 253        u16     PktSize;
 254        u8      Offset;
 255        u8      TxFWInfoSize;
 256
 257        /* DWORD 1 */
 258        u8      RATid:3;
 259        u8      DISFB:1;
 260        u8      USERATE:1;
 261        u8      MOREFRAG:1;
 262        u8      NoEnc:1;
 263        u8      PIFS:1;
 264        u8      QueueSelect:5;
 265        u8      NoACM:1;
 266        u8      Reserved1:2;
 267        u8      SecCAMID:5;
 268        u8      SecDescAssign:1;
 269        u8      SecType:2;
 270        u8      PacketID:7;
 271        u8      OWN:1;
 272} tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
 273#endif
 274
 275
 276
 277typedef struct _tx_desc_cmd_819x_usb {
 278        /* DWORD 0 */
 279        u16     Reserved0;
 280        u8      Reserved1;
 281        u8      Reserved2:3;
 282        u8      CmdInit:1;
 283        u8      LastSeg:1;
 284        u8      FirstSeg:1;
 285        u8      LINIP:1;
 286        u8      OWN:1;
 287
 288        /* DOWRD 1 */
 289        u8      TxFWInfoSize;
 290        u8      Reserved3;
 291        u8      QueueSelect;
 292        u8      Reserved4;
 293
 294        /* DOWRD 2 */
 295        u16     TxBufferSize;
 296        u16     Reserved5;
 297
 298        /* DWORD 3, 4, 5 */
 299        u32     Reserved6;
 300        u32     Reserved7;
 301        u32     Reserved8;
 302} tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
 303
 304
 305typedef struct _tx_fwinfo_819x_usb {
 306        /* DOWRD 0 */
 307        u8      TxRate:7;
 308        u8      CtsEnable:1;
 309        u8      RtsRate:7;
 310        u8      RtsEnable:1;
 311        u8      TxHT:1;
 312        u8      Short:1;        /* Error out, always on */
 313        u8      TxBandwidth:1;  /* Used for HT MCS rate only */
 314        u8      TxSubCarrier:2; /* Used for legacy OFDM rate only */
 315        u8      STBC:2;
 316        u8      AllowAggregation:1;
 317        /* Interpret RtsRate field as high throughput data rate */
 318        u8      RtsHT:1;
 319        u8      RtsShort:1;     /* Short PLCP for CCK or short GI for 11n MCS */
 320        u8      RtsBandwidth:1; /* Used for HT MCS rate only */
 321        u8      RtsSubcarrier:2;/* Used for legacy OFDM rate only */
 322        u8      RtsSTBC:2;
 323        /* Enable firmware to recalculate and assign packet duration */
 324        u8      EnableCPUDur:1;
 325
 326        /* DWORD 1 */
 327        u32     RxMF:2;
 328        u32     RxAMD:3;
 329        /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */
 330        u32     TxPerPktInfoFeedback:1;
 331        u32     Reserved1:2;
 332        u32     TxAGCOffSet:4;
 333        u32     TxAGCSign:1;
 334        u32     Tx_INFO_RSVD:6;
 335        u32     PacketID:13;
 336} tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
 337
 338typedef struct rtl8192_rx_info {
 339        struct urb *urb;
 340        struct net_device *dev;
 341        u8 out_pipe;
 342} rtl8192_rx_info ;
 343
 344typedef struct rx_desc_819x_usb {
 345        /* DOWRD 0 */
 346        u16                 Length:14;
 347        u16                 CRC32:1;
 348        u16                 ICV:1;
 349        u8                  RxDrvInfoSize;
 350        u8                  Shift:2;
 351        u8                  PHYStatus:1;
 352        u8                  SWDec:1;
 353        u8                  Reserved1:4;
 354
 355        /* DWORD 1 */
 356        u32                 Reserved2;
 357} rx_desc_819x_usb, *prx_desc_819x_usb;
 358
 359#ifdef USB_RX_AGGREGATION_SUPPORT
 360typedef struct _rx_desc_819x_usb_aggr_subframe {
 361        /* DOWRD 0 */
 362        u16                     Length:14;
 363        u16                     CRC32:1;
 364        u16                     ICV:1;
 365        u8                      Offset;
 366        u8                      RxDrvInfoSize;
 367        /* DOWRD 1 */
 368        u8                      Shift:2;
 369        u8                      PHYStatus:1;
 370        u8                      SWDec:1;
 371        u8                      Reserved1:4;
 372        u8                      Reserved2;
 373        u16                     Reserved3;
 374} rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
 375#endif
 376
 377typedef struct rx_drvinfo_819x_usb {
 378        /* DWORD 0 */
 379        u16                 Reserved1:12;
 380        u16                 PartAggr:1;
 381        u16                 FirstAGGR:1;
 382        u16                 Reserved2:2;
 383
 384        u8                  RxRate:7;
 385        u8                  RxHT:1;
 386
 387        u8                  BW:1;
 388        u8                  SPLCP:1;
 389        u8                  Reserved3:2;
 390        u8                  PAM:1;
 391        u8                  Mcast:1;
 392        u8                  Bcast:1;
 393        u8                  Reserved4:1;
 394
 395        /* DWORD 1 */
 396        u32                  TSFL;
 397
 398} rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
 399
 400/* Support till 64 bit bus width OS */
 401#define MAX_DEV_ADDR_SIZE               8
 402/* For RTL8190 */
 403#define MAX_FIRMWARE_INFORMATION_SIZE   32
 404#define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 405#define ENCRYPTION_MAX_OVERHEAD         128
 406#define USB_HWDESC_HEADER_LEN           sizeof(tx_desc_819x_usb)
 407#define TX_PACKET_SHIFT_BYTES           (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
 408#define MAX_FRAGMENT_COUNT              8
 409#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 410#define MAX_TRANSMIT_BUFFER_SIZE                        32000
 411#else
 412#define MAX_TRANSMIT_BUFFER_SIZE                        8000
 413#endif
 414#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 415#define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
 416#endif
 417/* Octets for crc32 (FCS, ICV) */
 418#define scrclng                                 4
 419
 420typedef enum rf_optype {
 421        RF_OP_By_SW_3wire = 0,
 422        RF_OP_By_FW,
 423        RF_OP_MAX
 424} rf_op_type;
 425/* 8190 Loopback Mode definition */
 426typedef enum _rtl819xUsb_loopback {
 427        RTL819xU_NO_LOOPBACK = 0,
 428        RTL819xU_MAC_LOOPBACK = 1,
 429        RTL819xU_DMA_LOOPBACK = 2,
 430        RTL819xU_CCK_LOOPBACK = 3,
 431} rtl819xUsb_loopback_e;
 432
 433/* due to rtl8192 firmware */
 434typedef enum _desc_packet_type_e {
 435        DESC_PACKET_TYPE_INIT = 0,
 436        DESC_PACKET_TYPE_NORMAL = 1,
 437} desc_packet_type_e;
 438
 439typedef enum _firmware_status {
 440        FW_STATUS_0_INIT = 0,
 441        FW_STATUS_1_MOVE_BOOT_CODE = 1,
 442        FW_STATUS_2_MOVE_MAIN_CODE = 2,
 443        FW_STATUS_3_TURNON_CPU = 3,
 444        FW_STATUS_4_MOVE_DATA_CODE = 4,
 445        FW_STATUS_5_READY = 5,
 446} firmware_status_e;
 447
 448typedef struct _rt_firmare_seg_container {
 449        u16     seg_size;
 450        u8      *seg_ptr;
 451} fw_seg_container, *pfw_seg_container;
 452typedef struct _rt_firmware {
 453        firmware_status_e firmware_status;
 454        u16               cmdpacket_frag_thresold;
 455#define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000
 456        u8                firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
 457        u16               firmware_buf_size;
 458} rt_firmware, *prt_firmware;
 459
 460/* Add this to 9100 bytes to receive A-MSDU from RT-AP */
 461#define MAX_RECEIVE_BUFFER_SIZE 9100
 462
 463typedef struct _rt_firmware_info_819xUsb {
 464        u8              sz_info[16];
 465} rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
 466
 467/* Firmware Queue Layout */
 468#define NUM_OF_FIRMWARE_QUEUE           10
 469#define NUM_OF_PAGES_IN_FW              0x100
 470
 471#ifdef USE_ONE_PIPE
 472#define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x000
 473#define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x000
 474#define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x0ff
 475#define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x000
 476#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 477#define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x0
 478#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x00
 479#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 480#define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x0
 481#define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x00
 482#else
 483
 484#define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x020
 485#define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x020
 486#define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x040
 487#define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x040
 488#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 489#define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x4
 490#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
 491#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 492#define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 493#define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x18
 494
 495#endif
 496
 497#define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 498#define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 499#define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 500#define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 501#define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 502#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 503#define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 504#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 505#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 506
 507/*
 508 * =================================================================
 509 * =================================================================
 510 */
 511
 512#define EPROM_93c46 0
 513#define EPROM_93c56 1
 514
 515#define DEFAULT_FRAG_THRESHOLD 2342U
 516#define MIN_FRAG_THRESHOLD     256U
 517#define DEFAULT_BEACONINTERVAL 0x64U
 518#define DEFAULT_BEACON_ESSID "Rtl819xU"
 519
 520#define DEFAULT_SSID ""
 521#define DEFAULT_RETRY_RTS 7
 522#define DEFAULT_RETRY_DATA 7
 523#define PRISM_HDR_SIZE 64
 524
 525#define         PHY_RSSI_SLID_WIN_MAX                           100
 526
 527
 528typedef enum _WIRELESS_MODE {
 529        WIRELESS_MODE_UNKNOWN = 0x00,
 530        WIRELESS_MODE_A = 0x01,
 531        WIRELESS_MODE_B = 0x02,
 532        WIRELESS_MODE_G = 0x04,
 533        WIRELESS_MODE_AUTO = 0x08,
 534        WIRELESS_MODE_N_24G = 0x10,
 535        WIRELESS_MODE_N_5G = 0x20
 536} WIRELESS_MODE;
 537
 538
 539#define RTL_IOCTL_WPA_SUPPLICANT                (SIOCIWFIRSTPRIV + 30)
 540
 541typedef struct buffer {
 542        struct buffer *next;
 543        u32 *buf;
 544
 545} buffer;
 546
 547typedef struct rtl_reg_debug {
 548        unsigned int  cmd;
 549        struct {
 550                unsigned char type;
 551                unsigned char addr;
 552                unsigned char page;
 553                unsigned char length;
 554        } head;
 555        unsigned char buf[0xff];
 556} rtl_reg_debug;
 557
 558
 559
 560
 561
 562
 563typedef struct _rt_9x_tx_rate_history {
 564        u32             cck[4];
 565        u32             ofdm[8];
 566        u32             ht_mcs[4][16];
 567} rt_tx_rahis_t, *prt_tx_rahis_t;
 568typedef struct _RT_SMOOTH_DATA_4RF {
 569        char    elements[4][100]; /* array to store values */
 570        u32     index;            /* index to current array to store */
 571        u32     TotalNum;         /* num of valid elements */
 572        u32     TotalVal[4];      /* sum of valid elements */
 573} RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 574
 575/* This maybe changed for D-cut larger aggregation size */
 576#define MAX_8192U_RX_SIZE                       8192
 577/* Stats seems messed up, clean it ASAP */
 578typedef struct Stats {
 579        unsigned long txrdu;
 580        unsigned long rxok;
 581        unsigned long rxframgment;
 582        unsigned long rxurberr;
 583        unsigned long rxstaterr;
 584        /* 0: Total, 1: OK, 2: CRC, 3: ICV */
 585        unsigned long received_rate_histogram[4][32];
 586        /* 0: Long preamble/GI, 1: Short preamble/GI */
 587        unsigned long received_preamble_GI[2][32];
 588        /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */
 589        unsigned long rx_AMPDUsize_histogram[5];
 590        /* level: (<5), (5~10), (10~20), (20~40), (>40) */
 591        unsigned long rx_AMPDUnum_histogram[5];
 592        unsigned long numpacket_matchbssid;
 593        unsigned long numpacket_toself;
 594        unsigned long num_process_phyinfo;
 595        unsigned long numqry_phystatus;
 596        unsigned long numqry_phystatusCCK;
 597        unsigned long numqry_phystatusHT;
 598        /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */
 599        unsigned long received_bwtype[5];
 600        unsigned long txnperr;
 601        unsigned long txnpdrop;
 602        unsigned long txresumed;
 603        unsigned long txnpokint;
 604        unsigned long txoverflow;
 605        unsigned long txlpokint;
 606        unsigned long txlpdrop;
 607        unsigned long txlperr;
 608        unsigned long txbeokint;
 609        unsigned long txbedrop;
 610        unsigned long txbeerr;
 611        unsigned long txbkokint;
 612        unsigned long txbkdrop;
 613        unsigned long txbkerr;
 614        unsigned long txviokint;
 615        unsigned long txvidrop;
 616        unsigned long txvierr;
 617        unsigned long txvookint;
 618        unsigned long txvodrop;
 619        unsigned long txvoerr;
 620        unsigned long txbeaconokint;
 621        unsigned long txbeacondrop;
 622        unsigned long txbeaconerr;
 623        unsigned long txmanageokint;
 624        unsigned long txmanagedrop;
 625        unsigned long txmanageerr;
 626        unsigned long txdatapkt;
 627        unsigned long txfeedback;
 628        unsigned long txfeedbackok;
 629
 630        unsigned long txoktotal;
 631        unsigned long txokbytestotal;
 632        unsigned long txokinperiod;
 633        unsigned long txmulticast;
 634        unsigned long txbytesmulticast;
 635        unsigned long txbroadcast;
 636        unsigned long txbytesbroadcast;
 637        unsigned long txunicast;
 638        unsigned long txbytesunicast;
 639
 640        unsigned long rxoktotal;
 641        unsigned long rxbytesunicast;
 642        unsigned long txfeedbackfail;
 643        unsigned long txerrtotal;
 644        unsigned long txerrbytestotal;
 645        unsigned long txerrmulticast;
 646        unsigned long txerrbroadcast;
 647        unsigned long txerrunicast;
 648        unsigned long txretrycount;
 649        unsigned long txfeedbackretry;
 650        u8            last_packet_rate;
 651        unsigned long slide_signal_strength[100];
 652        unsigned long slide_evm[100];
 653        /* For recording sliding window's RSSI value */
 654        unsigned long slide_rssi_total;
 655        /* For recording sliding window's EVM value */
 656        unsigned long slide_evm_total;
 657        /* Transformed in dbm. Beautified signal strength for UI, not correct */
 658        long signal_strength;
 659        long signal_quality;
 660        long last_signal_strength_inpercent;
 661        /* Correct smoothed ss in dbm, only used in driver
 662         * to report real power now */
 663        long recv_signal_power;
 664        u8 rx_rssi_percentage[4];
 665        u8 rx_evm_percentage[2];
 666        long rxSNRdB[4];
 667        rt_tx_rahis_t txrate;
 668        /* For beacon RSSI */
 669        u32 Slide_Beacon_pwdb[100];
 670        u32 Slide_Beacon_Total;
 671        RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 672
 673        u32     CurrentShowTxate;
 674} Stats;
 675
 676
 677/* Bandwidth Offset */
 678#define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 679#define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 680#define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 681
 682
 683typedef struct  ChnlAccessSetting {
 684        u16 SIFS_Timer;
 685        u16 DIFS_Timer;
 686        u16 SlotTimeTimer;
 687        u16 EIFS_Timer;
 688        u16 CWminIndex;
 689        u16 CWmaxIndex;
 690} *PCHANNEL_ACCESS_SETTING, CHANNEL_ACCESS_SETTING;
 691
 692typedef struct _BB_REGISTER_DEFINITION {
 693        /* set software control:        0x870~0x877 [8 bytes]  */
 694        u32 rfintfs;
 695        /* readback data:               0x8e0~0x8e7 [8 bytes]  */
 696        u32 rfintfi;
 697        /* output data:                 0x860~0x86f [16 bytes] */
 698        u32 rfintfo;
 699        /* output enable:               0x860~0x86f [16 bytes] */
 700        u32 rfintfe;
 701        /* LSSI data:                   0x840~0x84f [16 bytes] */
 702        u32 rf3wireOffset;
 703        /* BB Band Select:              0x878~0x87f [8 bytes]  */
 704        u32 rfLSSI_Select;
 705        /* Tx gain stage:               0x80c~0x80f [4 bytes]  */
 706        u32 rfTxGainStage;
 707        /* wire parameter control1:     0x820~0x823, 0x828~0x82b,
 708         *                              0x830~0x833, 0x838~0x83b [16 bytes] */
 709        u32 rfHSSIPara1;
 710        /* wire parameter control2:     0x824~0x827, 0x82c~0x82f,
 711         *                              0x834~0x837, 0x83c~0x83f [16 bytes] */
 712        u32 rfHSSIPara2;
 713        /* Tx Rx antenna control:       0x858~0x85f [16 bytes] */
 714        u32 rfSwitchControl;
 715        /* AGC parameter control1:      0xc50~0xc53, 0xc58~0xc5b,
 716         *                              0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
 717        u32 rfAGCControl1;
 718        /* AGC parameter control2:      0xc54~0xc57, 0xc5c~0xc5f,
 719         *                              0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
 720        u32 rfAGCControl2;
 721        /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
 722         *                              0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
 723        u32 rfRxIQImbalance;
 724        /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
 725         *                              0xc10~0xc13, 0xc18~0xc1b,
 726         *                              0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
 727        u32 rfRxAFE;
 728        /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
 729         *                              0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
 730        u32 rfTxIQImbalance;
 731        /* Tx IQ DC Offset and Tx DFIR type:
 732         *                              0xc84~0xc87, 0xc8c~0xc8f,
 733         *                              0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
 734        u32 rfTxAFE;
 735        /* LSSI RF readback data:       0x8a0~0x8af [16 bytes] */
 736        u32 rfLSSIReadBack;
 737} BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 738
 739typedef enum _RT_RF_TYPE_819xU {
 740        RF_TYPE_MIN = 0,
 741        RF_8225,
 742        RF_8256,
 743        RF_8258,
 744        RF_PSEUDO_11N = 4,
 745} RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
 746
 747typedef struct _rate_adaptive {
 748        u8                              rate_adaptive_disabled;
 749        u8                              ratr_state;
 750        u16                             reserve;
 751
 752        u32                             high_rssi_thresh_for_ra;
 753        u32                             high2low_rssi_thresh_for_ra;
 754        u8                              low2high_rssi_thresh_for_ra40M;
 755        u32                             low_rssi_thresh_for_ra40M;
 756        u8                              low2high_rssi_thresh_for_ra20M;
 757        u32                             low_rssi_thresh_for_ra20M;
 758        u32                             upper_rssi_threshold_ratr;
 759        u32                             middle_rssi_threshold_ratr;
 760        u32                             low_rssi_threshold_ratr;
 761        u32                             low_rssi_threshold_ratr_40M;
 762        u32                             low_rssi_threshold_ratr_20M;
 763        u8                              ping_rssi_enable;
 764        u32                             ping_rssi_ratr;
 765        u32                             ping_rssi_thresh_for_ra;
 766        u32                             last_ratr;
 767
 768} rate_adaptive, *prate_adaptive;
 769
 770#define TxBBGainTableLength 37
 771#define CCKTxBBGainTableLength 23
 772
 773typedef struct _txbbgain_struct {
 774        long    txbb_iq_amplifygain;
 775        u32     txbbgain_value;
 776} txbbgain_struct, *ptxbbgain_struct;
 777
 778typedef struct _ccktxbbgain_struct {
 779        /* The value is from a22 to a29, one byte one time is much safer */
 780        u8      ccktxbb_valuearray[8];
 781} ccktxbbgain_struct, *pccktxbbgain_struct;
 782
 783
 784typedef struct _init_gain {
 785        u8                              xaagccore1;
 786        u8                              xbagccore1;
 787        u8                              xcagccore1;
 788        u8                              xdagccore1;
 789        u8                              cca;
 790
 791} init_gain, *pinit_gain;
 792
 793typedef struct _phy_ofdm_rx_status_report_819xusb {
 794        u8      trsw_gain_X[4];
 795        u8      pwdb_all;
 796        u8      cfosho_X[4];
 797        u8      cfotail_X[4];
 798        u8      rxevm_X[2];
 799        u8      rxsnr_X[4];
 800        u8      pdsnr_X[2];
 801        u8      csi_current_X[2];
 802        u8      csi_target_X[2];
 803        u8      sigevm;
 804        u8      max_ex_pwr;
 805        u8      sgi_en;
 806        u8  rxsc_sgien_exflg;
 807} phy_sts_ofdm_819xusb_t;
 808
 809typedef struct _phy_cck_rx_status_report_819xusb {
 810        /* For CCK rate descriptor. This is an unsigned 8:1 variable.
 811         * LSB bit presend 0.5. And MSB 7 bts presend a signed value.
 812         * Range from -64~+63.5. */
 813        u8      adc_pwdb_X[4];
 814        u8      sq_rpt;
 815        u8      cck_agc_rpt;
 816} phy_sts_cck_819xusb_t;
 817
 818
 819typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag {
 820        u8                      reserved:4;
 821        u8                      rxsc:2;
 822        u8                      sgi_en:1;
 823        u8                      ex_intf_flag:1;
 824} phy_ofdm_rx_status_rxsc_sgien_exintfflag;
 825
 826typedef enum _RT_CUSTOMER_ID {
 827        RT_CID_DEFAULT = 0,
 828        RT_CID_8187_ALPHA0 = 1,
 829        RT_CID_8187_SERCOMM_PS = 2,
 830        RT_CID_8187_HW_LED = 3,
 831        RT_CID_8187_NETGEAR = 4,
 832        RT_CID_WHQL = 5,
 833        RT_CID_819x_CAMEO  = 6,
 834        RT_CID_819x_RUNTOP = 7,
 835        RT_CID_819x_Senao = 8,
 836        RT_CID_TOSHIBA = 9,
 837        RT_CID_819x_Netcore = 10,
 838        RT_CID_Nettronix = 11,
 839        RT_CID_DLINK = 12,
 840        RT_CID_PRONET = 13,
 841} RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 842
 843/*
 844 * ==========================================================================
 845 * LED customization.
 846 * ==========================================================================
 847 */
 848
 849typedef enum _LED_STRATEGY_8190 {
 850        SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
 851        SW_LED_MODE1, /* SW control for PCI Express */
 852        SW_LED_MODE2, /* SW control for Cameo. */
 853        SW_LED_MODE3, /* SW control for RunTop. */
 854        SW_LED_MODE4, /* SW control for Netcore. */
 855        /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
 856        HW_LED,
 857} LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 858
 859typedef enum _RESET_TYPE {
 860        RESET_TYPE_NORESET = 0x00,
 861        RESET_TYPE_NORMAL = 0x01,
 862        RESET_TYPE_SILENT = 0x02
 863} RESET_TYPE;
 864
 865/* The simple tx command OP code. */
 866typedef enum _tag_TxCmd_Config_Index {
 867        TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 868        TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 869        TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 870        TXCMD_SET_TX_DURATION                           = 0xFF900003,
 871        TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 872        TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 873        TXCMD_XXXX_CTRL,
 874} DCMD_TXCMD_OP;
 875
 876typedef struct r8192_priv {
 877        struct usb_device *udev;
 878        /* For maintain info from eeprom */
 879        short epromtype;
 880        u16 eeprom_vid;
 881        u16 eeprom_pid;
 882        u8  eeprom_CustomerID;
 883        u8  eeprom_ChannelPlan;
 884        RT_CUSTOMER_ID CustomerID;
 885        LED_STRATEGY_8190       LedStrategy;
 886        u8  txqueue_to_outpipemap[9];
 887        int irq;
 888        struct ieee80211_device *ieee80211;
 889
 890        /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */
 891        short card_8192;
 892        /* If TCR reports card V B/C, this discriminates */
 893        u8 card_8192_version;
 894        short enable_gpio0;
 895        enum card_type {
 896                PCI, MINIPCI, CARDBUS, USB
 897        } card_type;
 898        short hw_plcp_len;
 899        short plcp_preamble_mode;
 900
 901        spinlock_t irq_lock;
 902        spinlock_t tx_lock;
 903        struct mutex mutex;
 904
 905        u16 irq_mask;
 906        short chan;
 907        short sens;
 908        short max_sens;
 909
 910
 911        short up;
 912        /* If 1, allow bad crc frame, reception in monitor mode */
 913        short crcmon;
 914
 915        struct semaphore wx_sem;
 916        struct semaphore rf_sem;        /* Used to lock rf write operation */
 917
 918        u8 rf_type;                     /* 0: 1T2R, 1: 2T4R */
 919        RT_RF_TYPE_819xU rf_chip;
 920
 921        short (*rf_set_sens)(struct net_device *dev, short sens);
 922        u8 (*rf_set_chan)(struct net_device *dev, u8 ch);
 923        void (*rf_close)(struct net_device *dev);
 924        void (*rf_init)(struct net_device *dev);
 925        short promisc;
 926        /* Stats */
 927        struct Stats stats;
 928        struct iw_statistics wstats;
 929
 930        /* RX stuff */
 931        struct urb **rx_urb;
 932        struct urb **rx_cmd_urb;
 933#ifdef THOMAS_BEACON
 934        u32 *oldaddr;
 935#endif
 936#ifdef THOMAS_TASKLET
 937        atomic_t irt_counter; /* count for irq_rx_tasklet */
 938#endif
 939#ifdef JACKSON_NEW_RX
 940        struct sk_buff **pp_rxskb;
 941        int     rx_inx;
 942#endif
 943
 944       struct sk_buff_head rx_queue;
 945       struct sk_buff_head skb_queue;
 946       struct work_struct qos_activate;
 947        short  tx_urb_index;
 948        atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
 949
 950
 951        struct tasklet_struct irq_rx_tasklet;
 952        struct urb *rxurb_task;
 953
 954        /* Tx Related variables */
 955        u16     ShortRetryLimit;
 956        u16     LongRetryLimit;
 957        u32     TransmitConfig;
 958        u8      RegCWinMin;     /* For turbo mode CW adaptive */
 959
 960        u32     LastRxDescTSFHigh;
 961        u32     LastRxDescTSFLow;
 962
 963
 964        /* Rx Related variables */
 965        u16     EarlyRxThreshold;
 966        u32     ReceiveConfig;
 967        u8      AcmControl;
 968
 969        u8      RFProgType;
 970
 971        u8 retry_data;
 972        u8 retry_rts;
 973        u16 rts;
 974
 975        struct  ChnlAccessSetting  ChannelAccessSetting;
 976        struct work_struct reset_wq;
 977
 978/**********************************************************/
 979        /* For rtl819xUsb */
 980        u16     basic_rate;
 981        u8      short_preamble;
 982        u8      slot_time;
 983        bool    bDcut;
 984        bool bCurrentRxAggrEnable;
 985        u8 Rf_Mode;     /* For Firmware RF -R/W switch */
 986        prt_firmware            pFirmware;
 987        rtl819xUsb_loopback_e   LoopbackMode;
 988        u16 EEPROMTxPowerDiff;
 989        u8 EEPROMThermalMeter;
 990        u8 EEPROMPwDiff;
 991        u8 EEPROMCrystalCap;
 992        u8 EEPROM_Def_Ver;
 993        u8 EEPROMTxPowerLevelCCK;               /* CCK channel 1~14 */
 994        u8 EEPROMTxPowerLevelCCK_V1[3];
 995        u8 EEPROMTxPowerLevelOFDM24G[3];        /* OFDM 2.4G channel 1~14 */
 996        u8 EEPROMTxPowerLevelOFDM5G[24];        /* OFDM 5G */
 997
 998        /* PHY related */
 999        BB_REGISTER_DEFINITION_T PHYRegDef[4];  /* Radio A/B/C/D */
1000        /* Read/write are allow for following hardware information variables */

1001        u32     MCSTxPowerLevelOriginalOffset[6];
1002        u32     CCKTxPowerLevelOriginalOffset;
1003        u8      TxPowerLevelCCK[14];            /* CCK channel 1~14 */
1004        u8      TxPowerLevelOFDM24G[14];        /* OFDM 2.4G channel 1~14 */
1005        u8      TxPowerLevelOFDM5G[14];         /* OFDM 5G */
1006        u32     Pwr_Track;
1007        u8      TxPowerDiff;
1008        u8      AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */
1009        u8      CrystalCap;
1010        u8      ThermalMeter[2];    /* index 0: RFIC0, index 1: RFIC1 */
1011
1012        u8      CckPwEnl;
1013        /* Use to calculate PWBD */
1014        u8      bCckHighPower;
1015        long    undecorated_smoothed_pwdb;
1016
1017        /* For set channel */
1018        u8      SwChnlInProgress;
1019        u8      SwChnlStage;
1020        u8      SwChnlStep;
1021        u8      SetBWModeInProgress;
1022        HT_CHANNEL_WIDTH                CurrentChannelBW;
1023        u8      ChannelPlan;
1024        /* 8190 40MHz mode */
1025        /* Control channel sub-carrier */
1026        u8      nCur40MhzPrimeSC;
1027        /* Test for shorten RF configuration time.
1028         * We save RF reg0 in this variable to reduce RF reading. */
1029        u32                                     RfReg0Value[4];
1030        u8                                      NumTotalRFPath;
1031        bool                            brfpath_rxenable[4];
1032        /* RF set related */
1033        bool                            SetRFPowerStateInProgress;
1034        struct timer_list watch_dog_timer;
1035
1036        /* For dynamic mechanism */
1037        /* Tx Power Control for Near/Far Range */
1038        bool    bdynamic_txpower;
1039        bool    bDynamicTxHighPower;
1040        bool    bDynamicTxLowPower;
1041        bool    bLastDTPFlag_High;
1042        bool    bLastDTPFlag_Low;
1043
1044        bool    bstore_last_dtpflag;
1045        /* Define to discriminate on High power State or
1046         * on sitesurvey to change Tx gain index */
1047        bool    bstart_txctrl_bydtp;
1048        rate_adaptive rate_adaptive;
1049        /* TX power tracking
1050         * OPEN/CLOSE TX POWER TRACKING */
1051        txbbgain_struct txbbgain_table[TxBBGainTableLength];
1052        u8              txpower_count; /* For 6 sec do tracking again */
1053        bool            btxpower_trackingInit;
1054        u8              OFDM_index;
1055        u8              CCK_index;
1056        /* CCK TX Power Tracking */
1057        ccktxbbgain_struct      cck_txbbgain_table[CCKTxBBGainTableLength];
1058        ccktxbbgain_struct      cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1059        u8 rfa_txpowertrackingindex;
1060        u8 rfa_txpowertrackingindex_real;
1061        u8 rfa_txpowertracking_default;
1062        u8 rfc_txpowertrackingindex;
1063        u8 rfc_txpowertrackingindex_real;
1064
1065        s8 cck_present_attentuation;
1066        u8 cck_present_attentuation_20Mdefault;
1067        u8 cck_present_attentuation_40Mdefault;
1068        char cck_present_attentuation_difference;
1069        bool btxpower_tracking;
1070        bool bcck_in_ch14;
1071        bool btxpowerdata_readfromEEPORM;
1072        u16     TSSI_13dBm;
1073        init_gain initgain_backup;
1074        u8 DefaultInitialGain[4];
1075        /* For EDCA Turbo mode */
1076        bool            bis_any_nonbepkts;
1077        bool            bcurrent_turbo_EDCA;
1078        bool            bis_cur_rdlstate;
1079        struct timer_list fsync_timer;
1080        bool bfsync_processing; /* 500ms Fsync timer is active or not */
1081        u32     rate_record;
1082        u32     rateCountDiffRecord;
1083        u32     ContinueDiffCount;
1084        bool bswitch_fsync;
1085
1086        u8      framesync;
1087        u32     framesyncC34;
1088        u8      framesyncMonitor;
1089        u16     nrxAMPDU_size;
1090        u8      nrxAMPDU_aggr_num;
1091
1092        /* For gpio */
1093         bool bHwRadioOff;
1094
1095        u32 reset_count;
1096        bool bpbc_pressed;
1097        u32 txpower_checkcnt;
1098        u32 txpower_tracking_callback_cnt;
1099        u8 thermal_read_val[40];
1100        u8 thermal_readback_index;
1101        u32 ccktxpower_adjustcnt_not_ch14;
1102        u32 ccktxpower_adjustcnt_ch14;
1103        u8 tx_fwinfo_force_subcarriermode;
1104        u8 tx_fwinfo_force_subcarrierval;
1105        /* For silent reset */
1106        RESET_TYPE      ResetProgress;
1107        bool            bForcedSilentReset;
1108        bool            bDisableNormalResetCheck;
1109        u16             TxCounter;
1110        u16             RxCounter;
1111        int             IrpPendingCount;
1112        bool            bResetInProgress;
1113        bool            force_reset;
1114        u8              InitialGainOperateType;
1115
1116        u16             SifsTime;
1117
1118        /* Define work item */
1119
1120        struct delayed_work update_beacon_wq;
1121        struct delayed_work watch_dog_wq;
1122        struct delayed_work txpower_tracking_wq;
1123        struct delayed_work rfpath_check_wq;
1124        struct delayed_work gpio_change_rf_wq;
1125        struct delayed_work initialgain_operate_wq;
1126        struct workqueue_struct *priv_wq;
1127} r8192_priv;
1128
1129/* For rtl8187B */
1130typedef enum{
1131        BULK_PRIORITY = 0x01,
1132        LOW_PRIORITY,
1133        NORM_PRIORITY,
1134        VO_PRIORITY,
1135        VI_PRIORITY,
1136        BE_PRIORITY,
1137        BK_PRIORITY,
1138        RSVD2,
1139        RSVD3,
1140        BEACON_PRIORITY,
1141        HIGH_PRIORITY,
1142        MANAGE_PRIORITY,
1143        RSVD4,
1144        RSVD5,
1145        UART_PRIORITY
1146} priority_t;
1147
1148typedef enum {
1149        NIC_8192U = 1,
1150        NIC_8190P = 2,
1151        NIC_8192E = 3,
1152} nic_t;
1153
1154bool init_firmware(struct net_device *dev);
1155short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1156short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
1157
1158u32 read_cam(struct net_device *dev, u8 addr);
1159void write_cam(struct net_device *dev, u8 addr, u32 data);
1160
1161int read_nic_byte(struct net_device *dev, int x, u8 *data);
1162int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
1163int read_nic_dword(struct net_device *dev, int x, u32 *data);
1164int read_nic_word(struct net_device *dev, int x, u16 *data);
1165void write_nic_byte(struct net_device *dev, int x, u8 y);
1166void write_nic_byte_E(struct net_device *dev, int x, u8 y);
1167void write_nic_word(struct net_device *dev, int x, u16 y);
1168void write_nic_dword(struct net_device *dev, int x, u32 y);
1169void force_pci_posting(struct net_device *dev);
1170
1171void rtl8192_rtx_disable(struct net_device *);
1172void rtl8192_rx_enable(struct net_device *);
1173void rtl8192_tx_enable(struct net_device *);
1174
1175void rtl8192_disassociate(struct net_device *dev);
1176void rtl8185_set_rf_pins_enable(struct net_device *dev, u32 a);
1177
1178void rtl8192_set_anaparam(struct net_device *dev, u32 a);
1179void rtl8185_set_anaparam2(struct net_device *dev, u32 a);
1180void rtl8192_update_msr(struct net_device *dev);
1181int rtl8192_down(struct net_device *dev);
1182int rtl8192_up(struct net_device *dev);
1183void rtl8192_commit(struct net_device *dev);
1184void rtl8192_set_chan(struct net_device *dev, short ch);
1185void write_phy(struct net_device *dev, u8 adr, u8 data);
1186void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1187void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1188void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1189void rtl8192_set_rxconf(struct net_device *dev);
1190extern void rtl819xusb_beacon_tx(struct net_device *dev, u16 tx_rate);
1191
1192void EnableHWSecurityConfig8192(struct net_device *dev);
1193void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1194
1195
1196#endif
1197