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16#include <linux/device.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/serial_8250.h>
20#include <linux/serial_reg.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_platform.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26#include <linux/acpi.h>
27#include <linux/clk.h>
28#include <linux/reset.h>
29#include <linux/pm_runtime.h>
30
31#include <asm/byteorder.h>
32
33#include "8250.h"
34
35
36#define DW_UART_USR 0x1f
37#define DW_UART_CPR 0xf4
38#define DW_UART_UCV 0xf8
39
40
41#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
42#define DW_UART_CPR_AFCE_MODE (1 << 4)
43#define DW_UART_CPR_THRE_MODE (1 << 5)
44#define DW_UART_CPR_SIR_MODE (1 << 6)
45#define DW_UART_CPR_SIR_LP_MODE (1 << 7)
46#define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
47#define DW_UART_CPR_FIFO_ACCESS (1 << 9)
48#define DW_UART_CPR_FIFO_STAT (1 << 10)
49#define DW_UART_CPR_SHADOW (1 << 11)
50#define DW_UART_CPR_ENCODED_PARMS (1 << 12)
51#define DW_UART_CPR_DMA_EXTRA (1 << 13)
52#define DW_UART_CPR_FIFO_MODE (0xff << 16)
53
54#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
55
56
57struct dw8250_data {
58 u8 usr_reg;
59 int last_mcr;
60 int line;
61 int msr_mask_on;
62 int msr_mask_off;
63 struct clk *clk;
64 struct clk *pclk;
65 struct reset_control *rst;
66 struct uart_8250_dma dma;
67};
68
69#define BYT_PRV_CLK 0x800
70#define BYT_PRV_CLK_EN (1 << 0)
71#define BYT_PRV_CLK_M_VAL_SHIFT 1
72#define BYT_PRV_CLK_N_VAL_SHIFT 16
73#define BYT_PRV_CLK_UPDATE (1 << 31)
74
75static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
76{
77 struct dw8250_data *d = p->private_data;
78
79
80 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
81 value |= UART_MSR_CTS;
82 value &= ~UART_MSR_DCTS;
83 }
84
85
86 if (offset == UART_MSR) {
87 value |= d->msr_mask_on;
88 value &= ~d->msr_mask_off;
89 }
90
91 return value;
92}
93
94static void dw8250_force_idle(struct uart_port *p)
95{
96 struct uart_8250_port *up = up_to_u8250p(p);
97
98 serial8250_clear_and_reinit_fifos(up);
99 (void)p->serial_in(p, UART_RX);
100}
101
102static void dw8250_serial_out(struct uart_port *p, int offset, int value)
103{
104 struct dw8250_data *d = p->private_data;
105
106 if (offset == UART_MCR)
107 d->last_mcr = value;
108
109 writeb(value, p->membase + (offset << p->regshift));
110
111
112 if (offset == UART_LCR) {
113 int tries = 1000;
114 while (tries--) {
115 unsigned int lcr = p->serial_in(p, UART_LCR);
116 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
117 return;
118 dw8250_force_idle(p);
119 writeb(value, p->membase + (UART_LCR << p->regshift));
120 }
121
122
123
124
125 }
126}
127
128static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
129{
130 unsigned int value = readb(p->membase + (offset << p->regshift));
131
132 return dw8250_modify_msr(p, offset, value);
133}
134
135#ifdef CONFIG_64BIT
136static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
137{
138 unsigned int value;
139
140 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
141
142 return dw8250_modify_msr(p, offset, value);
143}
144
145static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
146{
147 struct dw8250_data *d = p->private_data;
148
149 if (offset == UART_MCR)
150 d->last_mcr = value;
151
152 value &= 0xff;
153 __raw_writeq(value, p->membase + (offset << p->regshift));
154
155 __raw_readq(p->membase + (UART_LCR << p->regshift));
156
157
158 if (offset == UART_LCR) {
159 int tries = 1000;
160 while (tries--) {
161 unsigned int lcr = p->serial_in(p, UART_LCR);
162 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
163 return;
164 dw8250_force_idle(p);
165 __raw_writeq(value & 0xff,
166 p->membase + (UART_LCR << p->regshift));
167 }
168
169
170
171
172 }
173}
174#endif
175
176static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
177{
178 struct dw8250_data *d = p->private_data;
179
180 if (offset == UART_MCR)
181 d->last_mcr = value;
182
183 writel(value, p->membase + (offset << p->regshift));
184
185
186 if (offset == UART_LCR) {
187 int tries = 1000;
188 while (tries--) {
189 unsigned int lcr = p->serial_in(p, UART_LCR);
190 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
191 return;
192 dw8250_force_idle(p);
193 writel(value, p->membase + (UART_LCR << p->regshift));
194 }
195
196
197
198
199 }
200}
201
202static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
203{
204 unsigned int value = readl(p->membase + (offset << p->regshift));
205
206 return dw8250_modify_msr(p, offset, value);
207}
208
209static int dw8250_handle_irq(struct uart_port *p)
210{
211 struct dw8250_data *d = p->private_data;
212 unsigned int iir = p->serial_in(p, UART_IIR);
213
214 if (serial8250_handle_irq(p, iir)) {
215 return 1;
216 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
217
218 (void)p->serial_in(p, d->usr_reg);
219
220 return 1;
221 }
222
223 return 0;
224}
225
226static void
227dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
228{
229 if (!state)
230 pm_runtime_get_sync(port->dev);
231
232 serial8250_do_pm(port, state, old);
233
234 if (state)
235 pm_runtime_put_sync_suspend(port->dev);
236}
237
238static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
239 struct ktermios *old)
240{
241 unsigned int baud = tty_termios_baud_rate(termios);
242 struct dw8250_data *d = p->private_data;
243 unsigned int rate;
244 int ret;
245
246 if (IS_ERR(d->clk) || !old)
247 goto out;
248
249
250 if (baud < 115200)
251 baud = 115200;
252
253 clk_disable_unprepare(d->clk);
254 rate = clk_round_rate(d->clk, baud * 16);
255 ret = clk_set_rate(d->clk, rate);
256 clk_prepare_enable(d->clk);
257
258 if (!ret)
259 p->uartclk = rate;
260out:
261 serial8250_do_set_termios(p, termios, old);
262}
263
264static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
265{
266 return false;
267}
268
269static void dw8250_setup_port(struct uart_8250_port *up)
270{
271 struct uart_port *p = &up->port;
272 u32 reg = readl(p->membase + DW_UART_UCV);
273
274
275
276
277
278 if (!reg)
279 return;
280
281 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
282 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
283
284 reg = readl(p->membase + DW_UART_CPR);
285 if (!reg)
286 return;
287
288
289 if (reg & DW_UART_CPR_FIFO_MODE) {
290 p->type = PORT_16550A;
291 p->flags |= UPF_FIXED_TYPE;
292 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
293 up->tx_loadsz = p->fifosize;
294 up->capabilities = UART_CAP_FIFO;
295 }
296
297 if (reg & DW_UART_CPR_AFCE_MODE)
298 up->capabilities |= UART_CAP_AFE;
299}
300
301static int dw8250_probe_of(struct uart_port *p,
302 struct dw8250_data *data)
303{
304 struct device_node *np = p->dev->of_node;
305 struct uart_8250_port *up = up_to_u8250p(p);
306 u32 val;
307 bool has_ucv = true;
308 int id;
309
310#ifdef CONFIG_64BIT
311 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
312 p->serial_in = dw8250_serial_inq;
313 p->serial_out = dw8250_serial_outq;
314 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
315 p->type = PORT_OCTEON;
316 data->usr_reg = 0x27;
317 has_ucv = false;
318 } else
319#endif
320 if (!of_property_read_u32(np, "reg-io-width", &val)) {
321 switch (val) {
322 case 1:
323 break;
324 case 4:
325 p->iotype = UPIO_MEM32;
326 p->serial_in = dw8250_serial_in32;
327 p->serial_out = dw8250_serial_out32;
328 break;
329 default:
330 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
331 return -EINVAL;
332 }
333 }
334 if (has_ucv)
335 dw8250_setup_port(up);
336
337
338 if (p->fifosize) {
339 up->dma = &data->dma;
340
341 up->dma->rxconf.src_maxburst = p->fifosize / 4;
342 up->dma->txconf.dst_maxburst = p->fifosize / 4;
343 }
344
345 if (!of_property_read_u32(np, "reg-shift", &val))
346 p->regshift = val;
347
348
349 id = of_alias_get_id(np, "serial");
350 if (id >= 0)
351 p->line = id;
352
353 if (of_property_read_bool(np, "dcd-override")) {
354
355 data->msr_mask_on |= UART_MSR_DCD;
356 data->msr_mask_off |= UART_MSR_DDCD;
357 }
358
359 if (of_property_read_bool(np, "dsr-override")) {
360
361 data->msr_mask_on |= UART_MSR_DSR;
362 data->msr_mask_off |= UART_MSR_DDSR;
363 }
364
365 if (of_property_read_bool(np, "cts-override")) {
366
367 data->msr_mask_on |= UART_MSR_CTS;
368 data->msr_mask_off |= UART_MSR_DCTS;
369 }
370
371 if (of_property_read_bool(np, "ri-override")) {
372
373 data->msr_mask_off |= UART_MSR_RI;
374 data->msr_mask_off |= UART_MSR_TERI;
375 }
376
377 return 0;
378}
379
380static int dw8250_probe_acpi(struct uart_8250_port *up,
381 struct dw8250_data *data)
382{
383 struct uart_port *p = &up->port;
384
385 dw8250_setup_port(up);
386
387 p->iotype = UPIO_MEM32;
388 p->serial_in = dw8250_serial_in32;
389 p->serial_out = dw8250_serial_out32;
390 p->regshift = 2;
391
392 up->dma = &data->dma;
393
394 up->dma->rxconf.src_maxburst = p->fifosize / 4;
395 up->dma->txconf.dst_maxburst = p->fifosize / 4;
396
397 up->port.set_termios = dw8250_set_termios;
398
399 return 0;
400}
401
402static int dw8250_probe(struct platform_device *pdev)
403{
404 struct uart_8250_port uart = {};
405 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
406 int irq = platform_get_irq(pdev, 0);
407 struct dw8250_data *data;
408 int err;
409
410 if (!regs) {
411 dev_err(&pdev->dev, "no registers defined\n");
412 return -EINVAL;
413 }
414
415 if (irq < 0) {
416 if (irq != -EPROBE_DEFER)
417 dev_err(&pdev->dev, "cannot get irq\n");
418 return irq;
419 }
420
421 spin_lock_init(&uart.port.lock);
422 uart.port.mapbase = regs->start;
423 uart.port.irq = irq;
424 uart.port.handle_irq = dw8250_handle_irq;
425 uart.port.pm = dw8250_do_pm;
426 uart.port.type = PORT_8250;
427 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
428 uart.port.dev = &pdev->dev;
429
430 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
431 resource_size(regs));
432 if (!uart.port.membase)
433 return -ENOMEM;
434
435 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
436 if (!data)
437 return -ENOMEM;
438
439 data->usr_reg = DW_UART_USR;
440
441
442 device_property_read_u32(&pdev->dev, "clock-frequency",
443 &uart.port.uartclk);
444
445
446 data->clk = devm_clk_get(&pdev->dev, "baudclk");
447 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
448 data->clk = devm_clk_get(&pdev->dev, NULL);
449 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
450 return -EPROBE_DEFER;
451 if (!IS_ERR_OR_NULL(data->clk)) {
452 err = clk_prepare_enable(data->clk);
453 if (err)
454 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
455 err);
456 else
457 uart.port.uartclk = clk_get_rate(data->clk);
458 }
459
460
461 if (!uart.port.uartclk) {
462 dev_err(&pdev->dev, "clock rate not defined\n");
463 return -EINVAL;
464 }
465
466 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
467 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
468 err = -EPROBE_DEFER;
469 goto err_clk;
470 }
471 if (!IS_ERR(data->pclk)) {
472 err = clk_prepare_enable(data->pclk);
473 if (err) {
474 dev_err(&pdev->dev, "could not enable apb_pclk\n");
475 goto err_clk;
476 }
477 }
478
479 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
480 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
481 err = -EPROBE_DEFER;
482 goto err_pclk;
483 }
484 if (!IS_ERR(data->rst))
485 reset_control_deassert(data->rst);
486
487 data->dma.rx_param = data;
488 data->dma.tx_param = data;
489 data->dma.fn = dw8250_dma_filter;
490
491 uart.port.iotype = UPIO_MEM;
492 uart.port.serial_in = dw8250_serial_in;
493 uart.port.serial_out = dw8250_serial_out;
494 uart.port.private_data = data;
495
496 if (pdev->dev.of_node) {
497 err = dw8250_probe_of(&uart.port, data);
498 if (err)
499 goto err_reset;
500 } else if (ACPI_HANDLE(&pdev->dev)) {
501 err = dw8250_probe_acpi(&uart, data);
502 if (err)
503 goto err_reset;
504 } else {
505 err = -ENODEV;
506 goto err_reset;
507 }
508
509 data->line = serial8250_register_8250_port(&uart);
510 if (data->line < 0) {
511 err = data->line;
512 goto err_reset;
513 }
514
515 platform_set_drvdata(pdev, data);
516
517 pm_runtime_set_active(&pdev->dev);
518 pm_runtime_enable(&pdev->dev);
519
520 return 0;
521
522err_reset:
523 if (!IS_ERR(data->rst))
524 reset_control_assert(data->rst);
525
526err_pclk:
527 if (!IS_ERR(data->pclk))
528 clk_disable_unprepare(data->pclk);
529
530err_clk:
531 if (!IS_ERR(data->clk))
532 clk_disable_unprepare(data->clk);
533
534 return err;
535}
536
537static int dw8250_remove(struct platform_device *pdev)
538{
539 struct dw8250_data *data = platform_get_drvdata(pdev);
540
541 pm_runtime_get_sync(&pdev->dev);
542
543 serial8250_unregister_port(data->line);
544
545 if (!IS_ERR(data->rst))
546 reset_control_assert(data->rst);
547
548 if (!IS_ERR(data->pclk))
549 clk_disable_unprepare(data->pclk);
550
551 if (!IS_ERR(data->clk))
552 clk_disable_unprepare(data->clk);
553
554 pm_runtime_disable(&pdev->dev);
555 pm_runtime_put_noidle(&pdev->dev);
556
557 return 0;
558}
559
560#ifdef CONFIG_PM_SLEEP
561static int dw8250_suspend(struct device *dev)
562{
563 struct dw8250_data *data = dev_get_drvdata(dev);
564
565 serial8250_suspend_port(data->line);
566
567 return 0;
568}
569
570static int dw8250_resume(struct device *dev)
571{
572 struct dw8250_data *data = dev_get_drvdata(dev);
573
574 serial8250_resume_port(data->line);
575
576 return 0;
577}
578#endif
579
580#ifdef CONFIG_PM
581static int dw8250_runtime_suspend(struct device *dev)
582{
583 struct dw8250_data *data = dev_get_drvdata(dev);
584
585 if (!IS_ERR(data->clk))
586 clk_disable_unprepare(data->clk);
587
588 if (!IS_ERR(data->pclk))
589 clk_disable_unprepare(data->pclk);
590
591 return 0;
592}
593
594static int dw8250_runtime_resume(struct device *dev)
595{
596 struct dw8250_data *data = dev_get_drvdata(dev);
597
598 if (!IS_ERR(data->pclk))
599 clk_prepare_enable(data->pclk);
600
601 if (!IS_ERR(data->clk))
602 clk_prepare_enable(data->clk);
603
604 return 0;
605}
606#endif
607
608static const struct dev_pm_ops dw8250_pm_ops = {
609 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
610 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
611};
612
613static const struct of_device_id dw8250_of_match[] = {
614 { .compatible = "snps,dw-apb-uart" },
615 { .compatible = "cavium,octeon-3860-uart" },
616 { }
617};
618MODULE_DEVICE_TABLE(of, dw8250_of_match);
619
620static const struct acpi_device_id dw8250_acpi_match[] = {
621 { "INT33C4", 0 },
622 { "INT33C5", 0 },
623 { "INT3434", 0 },
624 { "INT3435", 0 },
625 { "80860F0A", 0 },
626 { "8086228A", 0 },
627 { "APMC0D08", 0},
628 { "AMD0020", 0 },
629 { },
630};
631MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
632
633static struct platform_driver dw8250_platform_driver = {
634 .driver = {
635 .name = "dw-apb-uart",
636 .pm = &dw8250_pm_ops,
637 .of_match_table = dw8250_of_match,
638 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
639 },
640 .probe = dw8250_probe,
641 .remove = dw8250_remove,
642};
643
644module_platform_driver(dw8250_platform_driver);
645
646MODULE_AUTHOR("Jamie Iles");
647MODULE_LICENSE("GPL");
648MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
649MODULE_ALIAS("platform:dw-apb-uart");
650
