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20#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#include <linux/module.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
29#include <linux/platform_device.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/clk.h>
35#include <linux/delay.h>
36#include <linux/rational.h>
37#include <linux/slab.h>
38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/io.h>
41#include <linux/dma-mapping.h>
42
43#include <asm/irq.h>
44#include <linux/platform_data/serial-imx.h>
45#include <linux/platform_data/dma-imx.h>
46
47
48#define URXD0 0x0
49#define URTX0 0x40
50#define UCR1 0x80
51#define UCR2 0x84
52#define UCR3 0x88
53#define UCR4 0x8c
54#define UFCR 0x90
55#define USR1 0x94
56#define USR2 0x98
57#define UESC 0x9c
58#define UTIM 0xa0
59#define UBIR 0xa4
60#define UBMR 0xa8
61#define UBRC 0xac
62#define IMX21_ONEMS 0xb0
63#define IMX1_UTS 0xd0
64#define IMX21_UTS 0xb4
65
66
67#define URXD_DUMMY_READ (1<<16)
68#define URXD_CHARRDY (1<<15)
69#define URXD_ERR (1<<14)
70#define URXD_OVRRUN (1<<13)
71#define URXD_FRMERR (1<<12)
72#define URXD_BRK (1<<11)
73#define URXD_PRERR (1<<10)
74#define URXD_RX_DATA (0xFF<<0)
75#define UCR1_ADEN (1<<15)
76#define UCR1_ADBR (1<<14)
77#define UCR1_TRDYEN (1<<13)
78#define UCR1_IDEN (1<<12)
79#define UCR1_ICD_REG(x) (((x) & 3) << 10)
80#define UCR1_RRDYEN (1<<9)
81#define UCR1_RDMAEN (1<<8)
82#define UCR1_IREN (1<<7)
83#define UCR1_TXMPTYEN (1<<6)
84#define UCR1_RTSDEN (1<<5)
85#define UCR1_SNDBRK (1<<4)
86#define UCR1_TDMAEN (1<<3)
87#define IMX1_UCR1_UARTCLKEN (1<<2)
88#define UCR1_ATDMAEN (1<<2)
89#define UCR1_DOZE (1<<1)
90#define UCR1_UARTEN (1<<0)
91#define UCR2_ESCI (1<<15)
92#define UCR2_IRTS (1<<14)
93#define UCR2_CTSC (1<<13)
94#define UCR2_CTS (1<<12)
95#define UCR2_ESCEN (1<<11)
96#define UCR2_PREN (1<<8)
97#define UCR2_PROE (1<<7)
98#define UCR2_STPB (1<<6)
99#define UCR2_WS (1<<5)
100#define UCR2_RTSEN (1<<4)
101#define UCR2_ATEN (1<<3)
102#define UCR2_TXEN (1<<2)
103#define UCR2_RXEN (1<<1)
104#define UCR2_SRST (1<<0)
105#define UCR3_DTREN (1<<13)
106#define UCR3_PARERREN (1<<12)
107#define UCR3_FRAERREN (1<<11)
108#define UCR3_DSR (1<<10)
109#define UCR3_DCD (1<<9)
110#define UCR3_RI (1<<8)
111#define UCR3_ADNIMP (1<<7)
112#define UCR3_RXDSEN (1<<6)
113#define UCR3_AIRINTEN (1<<5)
114#define UCR3_AWAKEN (1<<4)
115#define IMX21_UCR3_RXDMUXSEL (1<<2)
116#define UCR3_INVT (1<<1)
117#define UCR3_BPEN (1<<0)
118#define UCR4_CTSTL_SHF 10
119#define UCR4_CTSTL_MASK 0x3F
120#define UCR4_INVR (1<<9)
121#define UCR4_ENIRI (1<<8)
122#define UCR4_WKEN (1<<7)
123#define UCR4_REF16 (1<<6)
124#define UCR4_IDDMAEN (1<<6)
125#define UCR4_IRSC (1<<5)
126#define UCR4_TCEN (1<<3)
127#define UCR4_BKEN (1<<2)
128#define UCR4_OREN (1<<1)
129#define UCR4_DREN (1<<0)
130#define UFCR_RXTL_SHF 0
131#define UFCR_DCEDTE (1<<6)
132#define UFCR_RFDIV (7<<7)
133#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
134#define UFCR_TXTL_SHF 10
135#define USR1_PARITYERR (1<<15)
136#define USR1_RTSS (1<<14)
137#define USR1_TRDY (1<<13)
138#define USR1_RTSD (1<<12)
139#define USR1_ESCF (1<<11)
140#define USR1_FRAMERR (1<<10)
141#define USR1_RRDY (1<<9)
142#define USR1_TIMEOUT (1<<7)
143#define USR1_RXDS (1<<6)
144#define USR1_AIRINT (1<<5)
145#define USR1_AWAKE (1<<4)
146#define USR2_ADET (1<<15)
147#define USR2_TXFE (1<<14)
148#define USR2_DTRF (1<<13)
149#define USR2_IDLE (1<<12)
150#define USR2_IRINT (1<<8)
151#define USR2_WAKE (1<<7)
152#define USR2_RTSF (1<<4)
153#define USR2_TXDC (1<<3)
154#define USR2_BRCD (1<<2)
155#define USR2_ORE (1<<1)
156#define USR2_RDR (1<<0)
157#define UTS_FRCPERR (1<<13)
158#define UTS_LOOP (1<<12)
159#define UTS_TXEMPTY (1<<6)
160#define UTS_RXEMPTY (1<<5)
161#define UTS_TXFULL (1<<4)
162#define UTS_RXFULL (1<<3)
163#define UTS_SOFTRST (1<<0)
164
165
166#define SERIAL_IMX_MAJOR 207
167#define MINOR_START 16
168#define DEV_NAME "ttymxc"
169
170
171
172
173
174
175
176#define MCTRL_TIMEOUT (250*HZ/1000)
177
178#define DRIVER_NAME "IMX-uart"
179
180#define UART_NR 8
181
182
183enum imx_uart_type {
184 IMX1_UART,
185 IMX21_UART,
186 IMX6Q_UART,
187};
188
189
190struct imx_uart_data {
191 unsigned uts_reg;
192 enum imx_uart_type devtype;
193};
194
195struct imx_port {
196 struct uart_port port;
197 struct timer_list timer;
198 unsigned int old_status;
199 unsigned int have_rtscts:1;
200 unsigned int dte_mode:1;
201 unsigned int irda_inv_rx:1;
202 unsigned int irda_inv_tx:1;
203 unsigned short trcv_delay;
204 struct clk *clk_ipg;
205 struct clk *clk_per;
206 const struct imx_uart_data *devdata;
207
208
209 unsigned int dma_is_inited:1;
210 unsigned int dma_is_enabled:1;
211 unsigned int dma_is_rxing:1;
212 unsigned int dma_is_txing:1;
213 struct dma_chan *dma_chan_rx, *dma_chan_tx;
214 struct scatterlist rx_sgl, tx_sgl[2];
215 void *rx_buf;
216 unsigned int tx_bytes;
217 unsigned int dma_tx_nents;
218 wait_queue_head_t dma_wait;
219};
220
221struct imx_port_ucrs {
222 unsigned int ucr1;
223 unsigned int ucr2;
224 unsigned int ucr3;
225};
226
227static struct imx_uart_data imx_uart_devdata[] = {
228 [IMX1_UART] = {
229 .uts_reg = IMX1_UTS,
230 .devtype = IMX1_UART,
231 },
232 [IMX21_UART] = {
233 .uts_reg = IMX21_UTS,
234 .devtype = IMX21_UART,
235 },
236 [IMX6Q_UART] = {
237 .uts_reg = IMX21_UTS,
238 .devtype = IMX6Q_UART,
239 },
240};
241
242static struct platform_device_id imx_uart_devtype[] = {
243 {
244 .name = "imx1-uart",
245 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
246 }, {
247 .name = "imx21-uart",
248 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
249 }, {
250 .name = "imx6q-uart",
251 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
252 }, {
253
254 }
255};
256MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
257
258static const struct of_device_id imx_uart_dt_ids[] = {
259 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
260 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
261 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
262 { }
263};
264MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
265
266static inline unsigned uts_reg(struct imx_port *sport)
267{
268 return sport->devdata->uts_reg;
269}
270
271static inline int is_imx1_uart(struct imx_port *sport)
272{
273 return sport->devdata->devtype == IMX1_UART;
274}
275
276static inline int is_imx21_uart(struct imx_port *sport)
277{
278 return sport->devdata->devtype == IMX21_UART;
279}
280
281static inline int is_imx6q_uart(struct imx_port *sport)
282{
283 return sport->devdata->devtype == IMX6Q_UART;
284}
285
286
287
288#if defined(CONFIG_SERIAL_IMX_CONSOLE)
289static void imx_port_ucrs_save(struct uart_port *port,
290 struct imx_port_ucrs *ucr)
291{
292
293 ucr->ucr1 = readl(port->membase + UCR1);
294 ucr->ucr2 = readl(port->membase + UCR2);
295 ucr->ucr3 = readl(port->membase + UCR3);
296}
297
298static void imx_port_ucrs_restore(struct uart_port *port,
299 struct imx_port_ucrs *ucr)
300{
301
302 writel(ucr->ucr1, port->membase + UCR1);
303 writel(ucr->ucr2, port->membase + UCR2);
304 writel(ucr->ucr3, port->membase + UCR3);
305}
306#endif
307
308
309
310
311static void imx_mctrl_check(struct imx_port *sport)
312{
313 unsigned int status, changed;
314
315 status = sport->port.ops->get_mctrl(&sport->port);
316 changed = status ^ sport->old_status;
317
318 if (changed == 0)
319 return;
320
321 sport->old_status = status;
322
323 if (changed & TIOCM_RI)
324 sport->port.icount.rng++;
325 if (changed & TIOCM_DSR)
326 sport->port.icount.dsr++;
327 if (changed & TIOCM_CAR)
328 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
329 if (changed & TIOCM_CTS)
330 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
331
332 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
333}
334
335
336
337
338
339static void imx_timeout(unsigned long data)
340{
341 struct imx_port *sport = (struct imx_port *)data;
342 unsigned long flags;
343
344 if (sport->port.state) {
345 spin_lock_irqsave(&sport->port.lock, flags);
346 imx_mctrl_check(sport);
347 spin_unlock_irqrestore(&sport->port.lock, flags);
348
349 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
350 }
351}
352
353
354
355
356static void imx_stop_tx(struct uart_port *port)
357{
358 struct imx_port *sport = (struct imx_port *)port;
359 unsigned long temp;
360
361
362
363
364
365 if (sport->dma_is_enabled && sport->dma_is_txing)
366 return;
367
368 temp = readl(port->membase + UCR1);
369 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
370
371
372 if (port->rs485.flags & SER_RS485_ENABLED &&
373 readl(port->membase + USR2) & USR2_TXDC) {
374 temp = readl(port->membase + UCR2);
375 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
376 temp &= ~UCR2_CTS;
377 else
378 temp |= UCR2_CTS;
379 writel(temp, port->membase + UCR2);
380
381 temp = readl(port->membase + UCR4);
382 temp &= ~UCR4_TCEN;
383 writel(temp, port->membase + UCR4);
384 }
385}
386
387
388
389
390static void imx_stop_rx(struct uart_port *port)
391{
392 struct imx_port *sport = (struct imx_port *)port;
393 unsigned long temp;
394
395 if (sport->dma_is_enabled && sport->dma_is_rxing) {
396 if (sport->port.suspended) {
397 dmaengine_terminate_all(sport->dma_chan_rx);
398 sport->dma_is_rxing = 0;
399 } else {
400 return;
401 }
402 }
403
404 temp = readl(sport->port.membase + UCR2);
405 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
406
407
408 temp = readl(sport->port.membase + UCR1);
409 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
410}
411
412
413
414
415static void imx_enable_ms(struct uart_port *port)
416{
417 struct imx_port *sport = (struct imx_port *)port;
418
419 mod_timer(&sport->timer, jiffies);
420}
421
422static void imx_dma_tx(struct imx_port *sport);
423static inline void imx_transmit_buffer(struct imx_port *sport)
424{
425 struct circ_buf *xmit = &sport->port.state->xmit;
426 unsigned long temp;
427
428 if (sport->port.x_char) {
429
430 writel(sport->port.x_char, sport->port.membase + URTX0);
431 sport->port.icount.tx++;
432 sport->port.x_char = 0;
433 return;
434 }
435
436 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
437 imx_stop_tx(&sport->port);
438 return;
439 }
440
441 if (sport->dma_is_enabled) {
442
443
444
445
446 temp = readl(sport->port.membase + UCR1);
447 temp &= ~UCR1_TXMPTYEN;
448 if (sport->dma_is_txing) {
449 temp |= UCR1_TDMAEN;
450 writel(temp, sport->port.membase + UCR1);
451 } else {
452 writel(temp, sport->port.membase + UCR1);
453 imx_dma_tx(sport);
454 }
455 }
456
457 while (!uart_circ_empty(xmit) &&
458 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
459
460
461 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
462 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
463 sport->port.icount.tx++;
464 }
465
466 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
467 uart_write_wakeup(&sport->port);
468
469 if (uart_circ_empty(xmit))
470 imx_stop_tx(&sport->port);
471}
472
473static void dma_tx_callback(void *data)
474{
475 struct imx_port *sport = data;
476 struct scatterlist *sgl = &sport->tx_sgl[0];
477 struct circ_buf *xmit = &sport->port.state->xmit;
478 unsigned long flags;
479 unsigned long temp;
480
481 spin_lock_irqsave(&sport->port.lock, flags);
482
483 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
484
485 temp = readl(sport->port.membase + UCR1);
486 temp &= ~UCR1_TDMAEN;
487 writel(temp, sport->port.membase + UCR1);
488
489
490 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
491 sport->port.icount.tx += sport->tx_bytes;
492
493 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
494
495 sport->dma_is_txing = 0;
496
497 spin_unlock_irqrestore(&sport->port.lock, flags);
498
499 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
500 uart_write_wakeup(&sport->port);
501
502 if (waitqueue_active(&sport->dma_wait)) {
503 wake_up(&sport->dma_wait);
504 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
505 return;
506 }
507
508 spin_lock_irqsave(&sport->port.lock, flags);
509 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
510 imx_dma_tx(sport);
511 spin_unlock_irqrestore(&sport->port.lock, flags);
512}
513
514static void imx_dma_tx(struct imx_port *sport)
515{
516 struct circ_buf *xmit = &sport->port.state->xmit;
517 struct scatterlist *sgl = sport->tx_sgl;
518 struct dma_async_tx_descriptor *desc;
519 struct dma_chan *chan = sport->dma_chan_tx;
520 struct device *dev = sport->port.dev;
521 unsigned long temp;
522 int ret;
523
524 if (sport->dma_is_txing)
525 return;
526
527 sport->tx_bytes = uart_circ_chars_pending(xmit);
528
529 if (xmit->tail < xmit->head) {
530 sport->dma_tx_nents = 1;
531 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
532 } else {
533 sport->dma_tx_nents = 2;
534 sg_init_table(sgl, 2);
535 sg_set_buf(sgl, xmit->buf + xmit->tail,
536 UART_XMIT_SIZE - xmit->tail);
537 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
538 }
539
540 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
541 if (ret == 0) {
542 dev_err(dev, "DMA mapping error for TX.\n");
543 return;
544 }
545 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
546 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
547 if (!desc) {
548 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
549 DMA_TO_DEVICE);
550 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
551 return;
552 }
553 desc->callback = dma_tx_callback;
554 desc->callback_param = sport;
555
556 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
557 uart_circ_chars_pending(xmit));
558
559 temp = readl(sport->port.membase + UCR1);
560 temp |= UCR1_TDMAEN;
561 writel(temp, sport->port.membase + UCR1);
562
563
564 sport->dma_is_txing = 1;
565 dmaengine_submit(desc);
566 dma_async_issue_pending(chan);
567 return;
568}
569
570
571
572
573static void imx_start_tx(struct uart_port *port)
574{
575 struct imx_port *sport = (struct imx_port *)port;
576 unsigned long temp;
577
578 if (port->rs485.flags & SER_RS485_ENABLED) {
579
580 temp = readl(port->membase + UCR2);
581 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
582 temp &= ~UCR2_CTS;
583 else
584 temp |= UCR2_CTS;
585 writel(temp, port->membase + UCR2);
586
587 temp = readl(port->membase + UCR4);
588 temp |= UCR4_TCEN;
589 writel(temp, port->membase + UCR4);
590 }
591
592 if (!sport->dma_is_enabled) {
593 temp = readl(sport->port.membase + UCR1);
594 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
595 }
596
597 if (sport->dma_is_enabled) {
598 if (sport->port.x_char) {
599
600
601 temp = readl(sport->port.membase + UCR1);
602 temp &= ~UCR1_TDMAEN;
603 temp |= UCR1_TXMPTYEN;
604 writel(temp, sport->port.membase + UCR1);
605 return;
606 }
607
608 if (!uart_circ_empty(&port->state->xmit) &&
609 !uart_tx_stopped(port))
610 imx_dma_tx(sport);
611 return;
612 }
613}
614
615static irqreturn_t imx_rtsint(int irq, void *dev_id)
616{
617 struct imx_port *sport = dev_id;
618 unsigned int val;
619 unsigned long flags;
620
621 spin_lock_irqsave(&sport->port.lock, flags);
622
623 writel(USR1_RTSD, sport->port.membase + USR1);
624 val = readl(sport->port.membase + USR1) & USR1_RTSS;
625 uart_handle_cts_change(&sport->port, !!val);
626 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
627
628 spin_unlock_irqrestore(&sport->port.lock, flags);
629 return IRQ_HANDLED;
630}
631
632static irqreturn_t imx_txint(int irq, void *dev_id)
633{
634 struct imx_port *sport = dev_id;
635 unsigned long flags;
636
637 spin_lock_irqsave(&sport->port.lock, flags);
638 imx_transmit_buffer(sport);
639 spin_unlock_irqrestore(&sport->port.lock, flags);
640 return IRQ_HANDLED;
641}
642
643static irqreturn_t imx_rxint(int irq, void *dev_id)
644{
645 struct imx_port *sport = dev_id;
646 unsigned int rx, flg, ignored = 0;
647 struct tty_port *port = &sport->port.state->port;
648 unsigned long flags, temp;
649
650 spin_lock_irqsave(&sport->port.lock, flags);
651
652 while (readl(sport->port.membase + USR2) & USR2_RDR) {
653 flg = TTY_NORMAL;
654 sport->port.icount.rx++;
655
656 rx = readl(sport->port.membase + URXD0);
657
658 temp = readl(sport->port.membase + USR2);
659 if (temp & USR2_BRCD) {
660 writel(USR2_BRCD, sport->port.membase + USR2);
661 if (uart_handle_break(&sport->port))
662 continue;
663 }
664
665 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
666 continue;
667
668 if (unlikely(rx & URXD_ERR)) {
669 if (rx & URXD_BRK)
670 sport->port.icount.brk++;
671 else if (rx & URXD_PRERR)
672 sport->port.icount.parity++;
673 else if (rx & URXD_FRMERR)
674 sport->port.icount.frame++;
675 if (rx & URXD_OVRRUN)
676 sport->port.icount.overrun++;
677
678 if (rx & sport->port.ignore_status_mask) {
679 if (++ignored > 100)
680 goto out;
681 continue;
682 }
683
684 rx &= (sport->port.read_status_mask | 0xFF);
685
686 if (rx & URXD_BRK)
687 flg = TTY_BREAK;
688 else if (rx & URXD_PRERR)
689 flg = TTY_PARITY;
690 else if (rx & URXD_FRMERR)
691 flg = TTY_FRAME;
692 if (rx & URXD_OVRRUN)
693 flg = TTY_OVERRUN;
694
695#ifdef SUPPORT_SYSRQ
696 sport->port.sysrq = 0;
697#endif
698 }
699
700 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
701 goto out;
702
703 tty_insert_flip_char(port, rx, flg);
704 }
705
706out:
707 spin_unlock_irqrestore(&sport->port.lock, flags);
708 tty_flip_buffer_push(port);
709 return IRQ_HANDLED;
710}
711
712static int start_rx_dma(struct imx_port *sport);
713
714
715
716
717static void imx_dma_rxint(struct imx_port *sport)
718{
719 unsigned long temp;
720 unsigned long flags;
721
722 spin_lock_irqsave(&sport->port.lock, flags);
723
724 temp = readl(sport->port.membase + USR2);
725 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
726 sport->dma_is_rxing = 1;
727
728
729 temp = readl(sport->port.membase + UCR1);
730 temp &= ~(UCR1_RRDYEN);
731 writel(temp, sport->port.membase + UCR1);
732
733
734 start_rx_dma(sport);
735 }
736
737 spin_unlock_irqrestore(&sport->port.lock, flags);
738}
739
740static irqreturn_t imx_int(int irq, void *dev_id)
741{
742 struct imx_port *sport = dev_id;
743 unsigned int sts;
744 unsigned int sts2;
745
746 sts = readl(sport->port.membase + USR1);
747 sts2 = readl(sport->port.membase + USR2);
748
749 if (sts & USR1_RRDY) {
750 if (sport->dma_is_enabled)
751 imx_dma_rxint(sport);
752 else
753 imx_rxint(irq, dev_id);
754 }
755
756 if ((sts & USR1_TRDY &&
757 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
758 (sts2 & USR2_TXDC &&
759 readl(sport->port.membase + UCR4) & UCR4_TCEN))
760 imx_txint(irq, dev_id);
761
762 if (sts & USR1_RTSD)
763 imx_rtsint(irq, dev_id);
764
765 if (sts & USR1_AWAKE)
766 writel(USR1_AWAKE, sport->port.membase + USR1);
767
768 if (sts2 & USR2_ORE) {
769 dev_err(sport->port.dev, "Rx FIFO overrun\n");
770 sport->port.icount.overrun++;
771 writel(USR2_ORE, sport->port.membase + USR2);
772 }
773
774 return IRQ_HANDLED;
775}
776
777
778
779
780static unsigned int imx_tx_empty(struct uart_port *port)
781{
782 struct imx_port *sport = (struct imx_port *)port;
783 unsigned int ret;
784
785 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
786
787
788 if (sport->dma_is_enabled && sport->dma_is_txing)
789 ret = 0;
790
791 return ret;
792}
793
794
795
796
797static unsigned int imx_get_mctrl(struct uart_port *port)
798{
799 struct imx_port *sport = (struct imx_port *)port;
800 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
801
802 if (readl(sport->port.membase + USR1) & USR1_RTSS)
803 tmp |= TIOCM_CTS;
804
805 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
806 tmp |= TIOCM_RTS;
807
808 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
809 tmp |= TIOCM_LOOP;
810
811 return tmp;
812}
813
814static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
815{
816 struct imx_port *sport = (struct imx_port *)port;
817 unsigned long temp;
818
819 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
820 temp = readl(sport->port.membase + UCR2);
821 temp &= ~(UCR2_CTS | UCR2_CTSC);
822 if (mctrl & TIOCM_RTS)
823 temp |= UCR2_CTS | UCR2_CTSC;
824 writel(temp, sport->port.membase + UCR2);
825 }
826
827 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
828 if (mctrl & TIOCM_LOOP)
829 temp |= UTS_LOOP;
830 writel(temp, sport->port.membase + uts_reg(sport));
831}
832
833
834
835
836static void imx_break_ctl(struct uart_port *port, int break_state)
837{
838 struct imx_port *sport = (struct imx_port *)port;
839 unsigned long flags, temp;
840
841 spin_lock_irqsave(&sport->port.lock, flags);
842
843 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
844
845 if (break_state != 0)
846 temp |= UCR1_SNDBRK;
847
848 writel(temp, sport->port.membase + UCR1);
849
850 spin_unlock_irqrestore(&sport->port.lock, flags);
851}
852
853#define TXTL 2
854#define RXTL 1
855
856static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
857{
858 unsigned int val;
859
860
861 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
862 val |= TXTL << UFCR_TXTL_SHF | RXTL;
863 writel(val, sport->port.membase + UFCR);
864 return 0;
865}
866
867#define RX_BUF_SIZE (PAGE_SIZE)
868static void imx_rx_dma_done(struct imx_port *sport)
869{
870 unsigned long temp;
871 unsigned long flags;
872
873 spin_lock_irqsave(&sport->port.lock, flags);
874
875
876 temp = readl(sport->port.membase + UCR1);
877 temp |= UCR1_RRDYEN;
878 writel(temp, sport->port.membase + UCR1);
879
880 sport->dma_is_rxing = 0;
881
882
883 if (waitqueue_active(&sport->dma_wait))
884 wake_up(&sport->dma_wait);
885
886 spin_unlock_irqrestore(&sport->port.lock, flags);
887}
888
889
890
891
892
893
894
895
896
897
898
899static void dma_rx_callback(void *data)
900{
901 struct imx_port *sport = data;
902 struct dma_chan *chan = sport->dma_chan_rx;
903 struct scatterlist *sgl = &sport->rx_sgl;
904 struct tty_port *port = &sport->port.state->port;
905 struct dma_tx_state state;
906 enum dma_status status;
907 unsigned int count;
908
909
910 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
911
912 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
913 count = RX_BUF_SIZE - state.residue;
914
915 if (readl(sport->port.membase + USR2) & USR2_IDLE) {
916
917 count--;
918
919 writel(USR2_IDLE, sport->port.membase + USR2);
920 }
921
922 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
923
924 if (count) {
925 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))
926 tty_insert_flip_string(port, sport->rx_buf, count);
927 tty_flip_buffer_push(port);
928
929 start_rx_dma(sport);
930 } else if (readl(sport->port.membase + USR2) & USR2_RDR) {
931
932
933
934
935
936
937 start_rx_dma(sport);
938 } else {
939
940
941
942
943 imx_rx_dma_done(sport);
944 }
945}
946
947static int start_rx_dma(struct imx_port *sport)
948{
949 struct scatterlist *sgl = &sport->rx_sgl;
950 struct dma_chan *chan = sport->dma_chan_rx;
951 struct device *dev = sport->port.dev;
952 struct dma_async_tx_descriptor *desc;
953 int ret;
954
955 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
956 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
957 if (ret == 0) {
958 dev_err(dev, "DMA mapping error for RX.\n");
959 return -EINVAL;
960 }
961 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
962 DMA_PREP_INTERRUPT);
963 if (!desc) {
964 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
965 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
966 return -EINVAL;
967 }
968 desc->callback = dma_rx_callback;
969 desc->callback_param = sport;
970
971 dev_dbg(dev, "RX: prepare for the DMA.\n");
972 dmaengine_submit(desc);
973 dma_async_issue_pending(chan);
974 return 0;
975}
976
977static void imx_uart_dma_exit(struct imx_port *sport)
978{
979 if (sport->dma_chan_rx) {
980 dma_release_channel(sport->dma_chan_rx);
981 sport->dma_chan_rx = NULL;
982
983 kfree(sport->rx_buf);
984 sport->rx_buf = NULL;
985 }
986
987 if (sport->dma_chan_tx) {
988 dma_release_channel(sport->dma_chan_tx);
989 sport->dma_chan_tx = NULL;
990 }
991
992 sport->dma_is_inited = 0;
993}
994
995static int imx_uart_dma_init(struct imx_port *sport)
996{
997 struct dma_slave_config slave_config = {};
998 struct device *dev = sport->port.dev;
999 int ret;
1000
1001
1002 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1003 if (!sport->dma_chan_rx) {
1004 dev_dbg(dev, "cannot get the DMA channel.\n");
1005 ret = -EINVAL;
1006 goto err;
1007 }
1008
1009 slave_config.direction = DMA_DEV_TO_MEM;
1010 slave_config.src_addr = sport->port.mapbase + URXD0;
1011 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1012 slave_config.src_maxburst = RXTL;
1013 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1014 if (ret) {
1015 dev_err(dev, "error in RX dma configuration.\n");
1016 goto err;
1017 }
1018
1019 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1020 if (!sport->rx_buf) {
1021 ret = -ENOMEM;
1022 goto err;
1023 }
1024
1025
1026 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1027 if (!sport->dma_chan_tx) {
1028 dev_err(dev, "cannot get the TX DMA channel!\n");
1029 ret = -EINVAL;
1030 goto err;
1031 }
1032
1033 slave_config.direction = DMA_MEM_TO_DEV;
1034 slave_config.dst_addr = sport->port.mapbase + URTX0;
1035 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1036 slave_config.dst_maxburst = TXTL;
1037 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1038 if (ret) {
1039 dev_err(dev, "error in TX dma configuration.");
1040 goto err;
1041 }
1042
1043 sport->dma_is_inited = 1;
1044
1045 return 0;
1046err:
1047 imx_uart_dma_exit(sport);
1048 return ret;
1049}
1050
1051static void imx_enable_dma(struct imx_port *sport)
1052{
1053 unsigned long temp;
1054
1055 init_waitqueue_head(&sport->dma_wait);
1056
1057
1058 temp = readl(sport->port.membase + UCR1);
1059 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1060
1061 UCR1_ICD_REG(3);
1062 writel(temp, sport->port.membase + UCR1);
1063
1064
1065 temp = readl(sport->port.membase + UCR4);
1066 temp |= UCR4_IDDMAEN;
1067 writel(temp, sport->port.membase + UCR4);
1068
1069 sport->dma_is_enabled = 1;
1070}
1071
1072static void imx_disable_dma(struct imx_port *sport)
1073{
1074 unsigned long temp;
1075
1076
1077 temp = readl(sport->port.membase + UCR1);
1078 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1079 writel(temp, sport->port.membase + UCR1);
1080
1081
1082 temp = readl(sport->port.membase + UCR2);
1083 temp &= ~(UCR2_CTSC | UCR2_CTS);
1084 writel(temp, sport->port.membase + UCR2);
1085
1086
1087 temp = readl(sport->port.membase + UCR4);
1088 temp &= ~UCR4_IDDMAEN;
1089 writel(temp, sport->port.membase + UCR4);
1090
1091 sport->dma_is_enabled = 0;
1092}
1093
1094
1095#define CTSTL 16
1096
1097static int imx_startup(struct uart_port *port)
1098{
1099 struct imx_port *sport = (struct imx_port *)port;
1100 int retval, i;
1101 unsigned long flags, temp;
1102
1103 retval = clk_prepare_enable(sport->clk_per);
1104 if (retval)
1105 return retval;
1106 retval = clk_prepare_enable(sport->clk_ipg);
1107 if (retval) {
1108 clk_disable_unprepare(sport->clk_per);
1109 return retval;
1110 }
1111
1112 imx_setup_ufcr(sport, 0);
1113
1114
1115
1116
1117 temp = readl(sport->port.membase + UCR4);
1118
1119
1120 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1121 temp |= CTSTL << UCR4_CTSTL_SHF;
1122
1123 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1124
1125
1126 i = 100;
1127
1128 temp = readl(sport->port.membase + UCR2);
1129 temp &= ~UCR2_SRST;
1130 writel(temp, sport->port.membase + UCR2);
1131
1132 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1133 udelay(1);
1134
1135
1136 if (is_imx6q_uart(sport) && !uart_console(port) &&
1137 !sport->dma_is_inited)
1138 imx_uart_dma_init(sport);
1139
1140 spin_lock_irqsave(&sport->port.lock, flags);
1141
1142
1143
1144
1145 writel(USR1_RTSD, sport->port.membase + USR1);
1146 writel(USR2_ORE, sport->port.membase + USR2);
1147
1148 if (sport->dma_is_inited && !sport->dma_is_enabled)
1149 imx_enable_dma(sport);
1150
1151 temp = readl(sport->port.membase + UCR1);
1152 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1153
1154 writel(temp, sport->port.membase + UCR1);
1155
1156 temp = readl(sport->port.membase + UCR4);
1157 temp |= UCR4_OREN;
1158 writel(temp, sport->port.membase + UCR4);
1159
1160 temp = readl(sport->port.membase + UCR2);
1161 temp |= (UCR2_RXEN | UCR2_TXEN);
1162 if (!sport->have_rtscts)
1163 temp |= UCR2_IRTS;
1164 writel(temp, sport->port.membase + UCR2);
1165
1166 if (!is_imx1_uart(sport)) {
1167 temp = readl(sport->port.membase + UCR3);
1168 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1169 writel(temp, sport->port.membase + UCR3);
1170 }
1171
1172
1173
1174
1175 imx_enable_ms(&sport->port);
1176 spin_unlock_irqrestore(&sport->port.lock, flags);
1177
1178 return 0;
1179}
1180
1181static void imx_shutdown(struct uart_port *port)
1182{
1183 struct imx_port *sport = (struct imx_port *)port;
1184 unsigned long temp;
1185 unsigned long flags;
1186
1187 if (sport->dma_is_enabled) {
1188 int ret;
1189
1190
1191 ret = wait_event_interruptible(sport->dma_wait,
1192 !sport->dma_is_rxing && !sport->dma_is_txing);
1193 if (ret != 0) {
1194 sport->dma_is_rxing = 0;
1195 sport->dma_is_txing = 0;
1196 dmaengine_terminate_all(sport->dma_chan_tx);
1197 dmaengine_terminate_all(sport->dma_chan_rx);
1198 }
1199 spin_lock_irqsave(&sport->port.lock, flags);
1200 imx_stop_tx(port);
1201 imx_stop_rx(port);
1202 imx_disable_dma(sport);
1203 spin_unlock_irqrestore(&sport->port.lock, flags);
1204 imx_uart_dma_exit(sport);
1205 }
1206
1207 spin_lock_irqsave(&sport->port.lock, flags);
1208 temp = readl(sport->port.membase + UCR2);
1209 temp &= ~(UCR2_TXEN);
1210 writel(temp, sport->port.membase + UCR2);
1211 spin_unlock_irqrestore(&sport->port.lock, flags);
1212
1213
1214
1215
1216 del_timer_sync(&sport->timer);
1217
1218
1219
1220
1221
1222 spin_lock_irqsave(&sport->port.lock, flags);
1223 temp = readl(sport->port.membase + UCR1);
1224 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1225
1226 writel(temp, sport->port.membase + UCR1);
1227 spin_unlock_irqrestore(&sport->port.lock, flags);
1228
1229 clk_disable_unprepare(sport->clk_per);
1230 clk_disable_unprepare(sport->clk_ipg);
1231}
1232
1233static void imx_flush_buffer(struct uart_port *port)
1234{
1235 struct imx_port *sport = (struct imx_port *)port;
1236 struct scatterlist *sgl = &sport->tx_sgl[0];
1237 unsigned long temp;
1238 int i = 100, ubir, ubmr, uts;
1239
1240 if (!sport->dma_chan_tx)
1241 return;
1242
1243 sport->tx_bytes = 0;
1244 dmaengine_terminate_all(sport->dma_chan_tx);
1245 if (sport->dma_is_txing) {
1246 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1247 DMA_TO_DEVICE);
1248 temp = readl(sport->port.membase + UCR1);
1249 temp &= ~UCR1_TDMAEN;
1250 writel(temp, sport->port.membase + UCR1);
1251 sport->dma_is_txing = false;
1252 }
1253
1254
1255
1256
1257
1258
1259
1260
1261 ubir = readl(sport->port.membase + UBIR);
1262 ubmr = readl(sport->port.membase + UBMR);
1263 uts = readl(sport->port.membase + IMX21_UTS);
1264
1265 temp = readl(sport->port.membase + UCR2);
1266 temp &= ~UCR2_SRST;
1267 writel(temp, sport->port.membase + UCR2);
1268
1269 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1270 udelay(1);
1271
1272
1273 writel(ubir, sport->port.membase + UBIR);
1274 writel(ubmr, sport->port.membase + UBMR);
1275 writel(uts, sport->port.membase + IMX21_UTS);
1276}
1277
1278static void
1279imx_set_termios(struct uart_port *port, struct ktermios *termios,
1280 struct ktermios *old)
1281{
1282 struct imx_port *sport = (struct imx_port *)port;
1283 unsigned long flags;
1284 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1285 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1286 unsigned int div, ufcr;
1287 unsigned long num, denom;
1288 uint64_t tdiv64;
1289
1290
1291
1292
1293 while ((termios->c_cflag & CSIZE) != CS7 &&
1294 (termios->c_cflag & CSIZE) != CS8) {
1295 termios->c_cflag &= ~CSIZE;
1296 termios->c_cflag |= old_csize;
1297 old_csize = CS8;
1298 }
1299
1300 if ((termios->c_cflag & CSIZE) == CS8)
1301 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1302 else
1303 ucr2 = UCR2_SRST | UCR2_IRTS;
1304
1305 if (termios->c_cflag & CRTSCTS) {
1306 if (sport->have_rtscts) {
1307 ucr2 &= ~UCR2_IRTS;
1308
1309 if (port->rs485.flags & SER_RS485_ENABLED) {
1310
1311
1312
1313
1314
1315 if (!(port->rs485.flags &
1316 SER_RS485_RTS_AFTER_SEND))
1317 ucr2 |= UCR2_CTS;
1318 } else {
1319 ucr2 |= UCR2_CTSC;
1320 }
1321 } else {
1322 termios->c_cflag &= ~CRTSCTS;
1323 }
1324 } else if (port->rs485.flags & SER_RS485_ENABLED)
1325
1326 if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND))
1327 ucr2 |= UCR2_CTS;
1328
1329 if (termios->c_cflag & CSTOPB)
1330 ucr2 |= UCR2_STPB;
1331 if (termios->c_cflag & PARENB) {
1332 ucr2 |= UCR2_PREN;
1333 if (termios->c_cflag & PARODD)
1334 ucr2 |= UCR2_PROE;
1335 }
1336
1337 del_timer_sync(&sport->timer);
1338
1339
1340
1341
1342 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1343 quot = uart_get_divisor(port, baud);
1344
1345 spin_lock_irqsave(&sport->port.lock, flags);
1346
1347 sport->port.read_status_mask = 0;
1348 if (termios->c_iflag & INPCK)
1349 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1350 if (termios->c_iflag & (BRKINT | PARMRK))
1351 sport->port.read_status_mask |= URXD_BRK;
1352
1353
1354
1355
1356 sport->port.ignore_status_mask = 0;
1357 if (termios->c_iflag & IGNPAR)
1358 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1359 if (termios->c_iflag & IGNBRK) {
1360 sport->port.ignore_status_mask |= URXD_BRK;
1361
1362
1363
1364
1365 if (termios->c_iflag & IGNPAR)
1366 sport->port.ignore_status_mask |= URXD_OVRRUN;
1367 }
1368
1369 if ((termios->c_cflag & CREAD) == 0)
1370 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1371
1372
1373
1374
1375 uart_update_timeout(port, termios->c_cflag, baud);
1376
1377
1378
1379
1380 old_ucr1 = readl(sport->port.membase + UCR1);
1381 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1382 sport->port.membase + UCR1);
1383
1384 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1385 barrier();
1386
1387
1388 old_txrxen = readl(sport->port.membase + UCR2);
1389 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1390 sport->port.membase + UCR2);
1391 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1392
1393
1394 div = sport->port.uartclk / (baud * 16);
1395 if (baud == 38400 && quot != div)
1396 baud = sport->port.uartclk / (quot * 16);
1397
1398 div = sport->port.uartclk / (baud * 16);
1399 if (div > 7)
1400 div = 7;
1401 if (!div)
1402 div = 1;
1403
1404 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1405 1 << 16, 1 << 16, &num, &denom);
1406
1407 tdiv64 = sport->port.uartclk;
1408 tdiv64 *= num;
1409 do_div(tdiv64, denom * 16 * div);
1410 tty_termios_encode_baud_rate(termios,
1411 (speed_t)tdiv64, (speed_t)tdiv64);
1412
1413 num -= 1;
1414 denom -= 1;
1415
1416 ufcr = readl(sport->port.membase + UFCR);
1417 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1418 if (sport->dte_mode)
1419 ufcr |= UFCR_DCEDTE;
1420 writel(ufcr, sport->port.membase + UFCR);
1421
1422 writel(num, sport->port.membase + UBIR);
1423 writel(denom, sport->port.membase + UBMR);
1424
1425 if (!is_imx1_uart(sport))
1426 writel(sport->port.uartclk / div / 1000,
1427 sport->port.membase + IMX21_ONEMS);
1428
1429 writel(old_ucr1, sport->port.membase + UCR1);
1430
1431
1432 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1433
1434 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1435 imx_enable_ms(&sport->port);
1436
1437 spin_unlock_irqrestore(&sport->port.lock, flags);
1438}
1439
1440static const char *imx_type(struct uart_port *port)
1441{
1442 struct imx_port *sport = (struct imx_port *)port;
1443
1444 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1445}
1446
1447
1448
1449
1450static void imx_config_port(struct uart_port *port, int flags)
1451{
1452 struct imx_port *sport = (struct imx_port *)port;
1453
1454 if (flags & UART_CONFIG_TYPE)
1455 sport->port.type = PORT_IMX;
1456}
1457
1458
1459
1460
1461
1462
1463static int
1464imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1465{
1466 struct imx_port *sport = (struct imx_port *)port;
1467 int ret = 0;
1468
1469 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1470 ret = -EINVAL;
1471 if (sport->port.irq != ser->irq)
1472 ret = -EINVAL;
1473 if (ser->io_type != UPIO_MEM)
1474 ret = -EINVAL;
1475 if (sport->port.uartclk / 16 != ser->baud_base)
1476 ret = -EINVAL;
1477 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1478 ret = -EINVAL;
1479 if (sport->port.iobase != ser->port)
1480 ret = -EINVAL;
1481 if (ser->hub6 != 0)
1482 ret = -EINVAL;
1483 return ret;
1484}
1485
1486#if defined(CONFIG_CONSOLE_POLL)
1487
1488static int imx_poll_init(struct uart_port *port)
1489{
1490 struct imx_port *sport = (struct imx_port *)port;
1491 unsigned long flags;
1492 unsigned long temp;
1493 int retval;
1494
1495 retval = clk_prepare_enable(sport->clk_ipg);
1496 if (retval)
1497 return retval;
1498 retval = clk_prepare_enable(sport->clk_per);
1499 if (retval)
1500 clk_disable_unprepare(sport->clk_ipg);
1501
1502 imx_setup_ufcr(sport, 0);
1503
1504 spin_lock_irqsave(&sport->port.lock, flags);
1505
1506 temp = readl(sport->port.membase + UCR1);
1507 if (is_imx1_uart(sport))
1508 temp |= IMX1_UCR1_UARTCLKEN;
1509 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1510 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1511 writel(temp, sport->port.membase + UCR1);
1512
1513 temp = readl(sport->port.membase + UCR2);
1514 temp |= UCR2_RXEN;
1515 writel(temp, sport->port.membase + UCR2);
1516
1517 spin_unlock_irqrestore(&sport->port.lock, flags);
1518
1519 return 0;
1520}
1521
1522static int imx_poll_get_char(struct uart_port *port)
1523{
1524 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1525 return NO_POLL_CHAR;
1526
1527 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1528}
1529
1530static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1531{
1532 unsigned int status;
1533
1534
1535 do {
1536 status = readl_relaxed(port->membase + USR1);
1537 } while (~status & USR1_TRDY);
1538
1539
1540 writel_relaxed(c, port->membase + URTX0);
1541
1542
1543 do {
1544 status = readl_relaxed(port->membase + USR2);
1545 } while (~status & USR2_TXDC);
1546}
1547#endif
1548
1549static int imx_rs485_config(struct uart_port *port,
1550 struct serial_rs485 *rs485conf)
1551{
1552 struct imx_port *sport = (struct imx_port *)port;
1553
1554
1555 rs485conf->delay_rts_before_send = 0;
1556 rs485conf->delay_rts_after_send = 0;
1557 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1558
1559
1560 if (!sport->have_rtscts)
1561 rs485conf->flags &= ~SER_RS485_ENABLED;
1562
1563 if (rs485conf->flags & SER_RS485_ENABLED) {
1564 unsigned long temp;
1565
1566
1567 temp = readl(sport->port.membase + UCR2);
1568 temp &= ~UCR2_CTSC;
1569 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1570 temp &= ~UCR2_CTS;
1571 else
1572 temp |= UCR2_CTS;
1573 writel(temp, sport->port.membase + UCR2);
1574 }
1575
1576 port->rs485 = *rs485conf;
1577
1578 return 0;
1579}
1580
1581static struct uart_ops imx_pops = {
1582 .tx_empty = imx_tx_empty,
1583 .set_mctrl = imx_set_mctrl,
1584 .get_mctrl = imx_get_mctrl,
1585 .stop_tx = imx_stop_tx,
1586 .start_tx = imx_start_tx,
1587 .stop_rx = imx_stop_rx,
1588 .enable_ms = imx_enable_ms,
1589 .break_ctl = imx_break_ctl,
1590 .startup = imx_startup,
1591 .shutdown = imx_shutdown,
1592 .flush_buffer = imx_flush_buffer,
1593 .set_termios = imx_set_termios,
1594 .type = imx_type,
1595 .config_port = imx_config_port,
1596 .verify_port = imx_verify_port,
1597#if defined(CONFIG_CONSOLE_POLL)
1598 .poll_init = imx_poll_init,
1599 .poll_get_char = imx_poll_get_char,
1600 .poll_put_char = imx_poll_put_char,
1601#endif
1602};
1603
1604static struct imx_port *imx_ports[UART_NR];
1605
1606#ifdef CONFIG_SERIAL_IMX_CONSOLE
1607static void imx_console_putchar(struct uart_port *port, int ch)
1608{
1609 struct imx_port *sport = (struct imx_port *)port;
1610
1611 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1612 barrier();
1613
1614 writel(ch, sport->port.membase + URTX0);
1615}
1616
1617
1618
1619
1620static void
1621imx_console_write(struct console *co, const char *s, unsigned int count)
1622{
1623 struct imx_port *sport = imx_ports[co->index];
1624 struct imx_port_ucrs old_ucr;
1625 unsigned int ucr1;
1626 unsigned long flags = 0;
1627 int locked = 1;
1628 int retval;
1629
1630 retval = clk_enable(sport->clk_per);
1631 if (retval)
1632 return;
1633 retval = clk_enable(sport->clk_ipg);
1634 if (retval) {
1635 clk_disable(sport->clk_per);
1636 return;
1637 }
1638
1639 if (sport->port.sysrq)
1640 locked = 0;
1641 else if (oops_in_progress)
1642 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1643 else
1644 spin_lock_irqsave(&sport->port.lock, flags);
1645
1646
1647
1648
1649 imx_port_ucrs_save(&sport->port, &old_ucr);
1650 ucr1 = old_ucr.ucr1;
1651
1652 if (is_imx1_uart(sport))
1653 ucr1 |= IMX1_UCR1_UARTCLKEN;
1654 ucr1 |= UCR1_UARTEN;
1655 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1656
1657 writel(ucr1, sport->port.membase + UCR1);
1658
1659 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1660
1661 uart_console_write(&sport->port, s, count, imx_console_putchar);
1662
1663
1664
1665
1666
1667 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1668
1669 imx_port_ucrs_restore(&sport->port, &old_ucr);
1670
1671 if (locked)
1672 spin_unlock_irqrestore(&sport->port.lock, flags);
1673
1674 clk_disable(sport->clk_ipg);
1675 clk_disable(sport->clk_per);
1676}
1677
1678
1679
1680
1681
1682static void __init
1683imx_console_get_options(struct imx_port *sport, int *baud,
1684 int *parity, int *bits)
1685{
1686
1687 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1688
1689 unsigned int ucr2, ubir, ubmr, uartclk;
1690 unsigned int baud_raw;
1691 unsigned int ucfr_rfdiv;
1692
1693 ucr2 = readl(sport->port.membase + UCR2);
1694
1695 *parity = 'n';
1696 if (ucr2 & UCR2_PREN) {
1697 if (ucr2 & UCR2_PROE)
1698 *parity = 'o';
1699 else
1700 *parity = 'e';
1701 }
1702
1703 if (ucr2 & UCR2_WS)
1704 *bits = 8;
1705 else
1706 *bits = 7;
1707
1708 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1709 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1710
1711 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1712 if (ucfr_rfdiv == 6)
1713 ucfr_rfdiv = 7;
1714 else
1715 ucfr_rfdiv = 6 - ucfr_rfdiv;
1716
1717 uartclk = clk_get_rate(sport->clk_per);
1718 uartclk /= ucfr_rfdiv;
1719
1720 {
1721
1722
1723
1724
1725
1726 unsigned int mul = ubir + 1;
1727 unsigned int div = 16 * (ubmr + 1);
1728 unsigned int rem = uartclk % div;
1729
1730 baud_raw = (uartclk / div) * mul;
1731 baud_raw += (rem * mul + div / 2) / div;
1732 *baud = (baud_raw + 50) / 100 * 100;
1733 }
1734
1735 if (*baud != baud_raw)
1736 pr_info("Console IMX rounded baud rate from %d to %d\n",
1737 baud_raw, *baud);
1738 }
1739}
1740
1741static int __init
1742imx_console_setup(struct console *co, char *options)
1743{
1744 struct imx_port *sport;
1745 int baud = 9600;
1746 int bits = 8;
1747 int parity = 'n';
1748 int flow = 'n';
1749 int retval;
1750
1751
1752
1753
1754
1755
1756 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1757 co->index = 0;
1758 sport = imx_ports[co->index];
1759 if (sport == NULL)
1760 return -ENODEV;
1761
1762
1763 retval = clk_prepare_enable(sport->clk_ipg);
1764 if (retval)
1765 goto error_console;
1766
1767 if (options)
1768 uart_parse_options(options, &baud, &parity, &bits, &flow);
1769 else
1770 imx_console_get_options(sport, &baud, &parity, &bits);
1771
1772 imx_setup_ufcr(sport, 0);
1773
1774 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1775
1776 clk_disable(sport->clk_ipg);
1777 if (retval) {
1778 clk_unprepare(sport->clk_ipg);
1779 goto error_console;
1780 }
1781
1782 retval = clk_prepare(sport->clk_per);
1783 if (retval)
1784 clk_disable_unprepare(sport->clk_ipg);
1785
1786error_console:
1787 return retval;
1788}
1789
1790static struct uart_driver imx_reg;
1791static struct console imx_console = {
1792 .name = DEV_NAME,
1793 .write = imx_console_write,
1794 .device = uart_console_device,
1795 .setup = imx_console_setup,
1796 .flags = CON_PRINTBUFFER,
1797 .index = -1,
1798 .data = &imx_reg,
1799};
1800
1801#define IMX_CONSOLE &imx_console
1802#else
1803#define IMX_CONSOLE NULL
1804#endif
1805
1806static struct uart_driver imx_reg = {
1807 .owner = THIS_MODULE,
1808 .driver_name = DRIVER_NAME,
1809 .dev_name = DEV_NAME,
1810 .major = SERIAL_IMX_MAJOR,
1811 .minor = MINOR_START,
1812 .nr = ARRAY_SIZE(imx_ports),
1813 .cons = IMX_CONSOLE,
1814};
1815
1816static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1817{
1818 struct imx_port *sport = platform_get_drvdata(dev);
1819 unsigned int val;
1820
1821
1822 val = readl(sport->port.membase + UCR3);
1823 val |= UCR3_AWAKEN;
1824 writel(val, sport->port.membase + UCR3);
1825
1826 uart_suspend_port(&imx_reg, &sport->port);
1827
1828 return 0;
1829}
1830
1831static int serial_imx_resume(struct platform_device *dev)
1832{
1833 struct imx_port *sport = platform_get_drvdata(dev);
1834 unsigned int val;
1835
1836
1837 val = readl(sport->port.membase + UCR3);
1838 val &= ~UCR3_AWAKEN;
1839 writel(val, sport->port.membase + UCR3);
1840
1841 uart_resume_port(&imx_reg, &sport->port);
1842
1843 return 0;
1844}
1845
1846#ifdef CONFIG_OF
1847
1848
1849
1850
1851static int serial_imx_probe_dt(struct imx_port *sport,
1852 struct platform_device *pdev)
1853{
1854 struct device_node *np = pdev->dev.of_node;
1855 const struct of_device_id *of_id =
1856 of_match_device(imx_uart_dt_ids, &pdev->dev);
1857 int ret;
1858
1859 if (!np)
1860
1861 return 1;
1862
1863 ret = of_alias_get_id(np, "serial");
1864 if (ret < 0) {
1865 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1866 return ret;
1867 }
1868 sport->port.line = ret;
1869
1870 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1871 sport->have_rtscts = 1;
1872
1873 if (of_get_property(np, "fsl,dte-mode", NULL))
1874 sport->dte_mode = 1;
1875
1876 sport->devdata = of_id->data;
1877
1878 return 0;
1879}
1880#else
1881static inline int serial_imx_probe_dt(struct imx_port *sport,
1882 struct platform_device *pdev)
1883{
1884 return 1;
1885}
1886#endif
1887
1888static void serial_imx_probe_pdata(struct imx_port *sport,
1889 struct platform_device *pdev)
1890{
1891 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1892
1893 sport->port.line = pdev->id;
1894 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1895
1896 if (!pdata)
1897 return;
1898
1899 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1900 sport->have_rtscts = 1;
1901}
1902
1903static int serial_imx_probe(struct platform_device *pdev)
1904{
1905 struct imx_port *sport;
1906 void __iomem *base;
1907 int ret = 0;
1908 struct resource *res;
1909 int txirq, rxirq, rtsirq;
1910
1911 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1912 if (!sport)
1913 return -ENOMEM;
1914
1915 ret = serial_imx_probe_dt(sport, pdev);
1916 if (ret > 0)
1917 serial_imx_probe_pdata(sport, pdev);
1918 else if (ret < 0)
1919 return ret;
1920
1921 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1922 base = devm_ioremap_resource(&pdev->dev, res);
1923 if (IS_ERR(base))
1924 return PTR_ERR(base);
1925
1926 rxirq = platform_get_irq(pdev, 0);
1927 txirq = platform_get_irq(pdev, 1);
1928 rtsirq = platform_get_irq(pdev, 2);
1929
1930 sport->port.dev = &pdev->dev;
1931 sport->port.mapbase = res->start;
1932 sport->port.membase = base;
1933 sport->port.type = PORT_IMX,
1934 sport->port.iotype = UPIO_MEM;
1935 sport->port.irq = rxirq;
1936 sport->port.fifosize = 32;
1937 sport->port.ops = &imx_pops;
1938 sport->port.rs485_config = imx_rs485_config;
1939 sport->port.rs485.flags =
1940 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
1941 sport->port.flags = UPF_BOOT_AUTOCONF;
1942 init_timer(&sport->timer);
1943 sport->timer.function = imx_timeout;
1944 sport->timer.data = (unsigned long)sport;
1945
1946 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1947 if (IS_ERR(sport->clk_ipg)) {
1948 ret = PTR_ERR(sport->clk_ipg);
1949 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1950 return ret;
1951 }
1952
1953 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1954 if (IS_ERR(sport->clk_per)) {
1955 ret = PTR_ERR(sport->clk_per);
1956 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1957 return ret;
1958 }
1959
1960 sport->port.uartclk = clk_get_rate(sport->clk_per);
1961
1962
1963
1964
1965
1966 if (txirq > 0) {
1967 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
1968 dev_name(&pdev->dev), sport);
1969 if (ret)
1970 return ret;
1971
1972 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
1973 dev_name(&pdev->dev), sport);
1974 if (ret)
1975 return ret;
1976 } else {
1977 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
1978 dev_name(&pdev->dev), sport);
1979 if (ret)
1980 return ret;
1981 }
1982
1983 imx_ports[sport->port.line] = sport;
1984
1985 platform_set_drvdata(pdev, sport);
1986
1987 return uart_add_one_port(&imx_reg, &sport->port);
1988}
1989
1990static int serial_imx_remove(struct platform_device *pdev)
1991{
1992 struct imx_port *sport = platform_get_drvdata(pdev);
1993
1994 return uart_remove_one_port(&imx_reg, &sport->port);
1995}
1996
1997static struct platform_driver serial_imx_driver = {
1998 .probe = serial_imx_probe,
1999 .remove = serial_imx_remove,
2000
2001 .suspend = serial_imx_suspend,
2002 .resume = serial_imx_resume,
2003 .id_table = imx_uart_devtype,
2004 .driver = {
2005 .name = "imx-uart",
2006 .of_match_table = imx_uart_dt_ids,
2007 },
2008};
2009
2010static int __init imx_serial_init(void)
2011{
2012 int ret = uart_register_driver(&imx_reg);
2013
2014 if (ret)
2015 return ret;
2016
2017 ret = platform_driver_register(&serial_imx_driver);
2018 if (ret != 0)
2019 uart_unregister_driver(&imx_reg);
2020
2021 return ret;
2022}
2023
2024static void __exit imx_serial_exit(void)
2025{
2026 platform_driver_unregister(&serial_imx_driver);
2027 uart_unregister_driver(&imx_reg);
2028}
2029
2030module_init(imx_serial_init);
2031module_exit(imx_serial_exit);
2032
2033MODULE_AUTHOR("Sascha Hauer");
2034MODULE_DESCRIPTION("IMX generic serial port driver");
2035MODULE_LICENSE("GPL");
2036MODULE_ALIAS("platform:imx-uart");
2037