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9
10#include <linux/irq.h>
11#include <linux/slab.h>
12
13static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
14{
15 int last = urb_priv->length - 1;
16
17 if (last >= 0) {
18 int i;
19 struct td *td;
20
21 for (i = 0; i <= last; i++) {
22 td = urb_priv->td [i];
23 if (td)
24 td_free (hc, td);
25 }
26 }
27
28 list_del (&urb_priv->pending);
29 kfree (urb_priv);
30}
31
32
33
34
35
36
37
38
39static void
40finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
41__releases(ohci->lock)
42__acquires(ohci->lock)
43{
44 struct device *dev = ohci_to_hcd(ohci)->self.controller;
45 struct usb_host_endpoint *ep = urb->ep;
46 struct urb_priv *urb_priv;
47
48
49
50 restart:
51 urb_free_priv (ohci, urb->hcpriv);
52 urb->hcpriv = NULL;
53 if (likely(status == -EINPROGRESS))
54 status = 0;
55
56 switch (usb_pipetype (urb->pipe)) {
57 case PIPE_ISOCHRONOUS:
58 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
59 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
60 if (quirk_amdiso(ohci))
61 usb_amd_quirk_pll_enable();
62 if (quirk_amdprefetch(ohci))
63 sb800_prefetch(dev, 0);
64 }
65 break;
66 case PIPE_INTERRUPT:
67 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
68 break;
69 }
70
71
72 usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
73 spin_unlock (&ohci->lock);
74 usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
75 spin_lock (&ohci->lock);
76
77
78 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
79 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
80 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
81 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
82 }
83
84
85
86
87
88
89
90 if (!list_empty(&ep->urb_list)) {
91 urb = list_first_entry(&ep->urb_list, struct urb, urb_list);
92 urb_priv = urb->hcpriv;
93 if (urb_priv->td_cnt > urb_priv->length) {
94 status = 0;
95 goto restart;
96 }
97 }
98}
99
100
101
102
103
104
105
106
107
108static int balance (struct ohci_hcd *ohci, int interval, int load)
109{
110 int i, branch = -ENOSPC;
111
112
113 if (interval > NUM_INTS)
114 interval = NUM_INTS;
115
116
117
118
119 for (i = 0; i < interval ; i++) {
120 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
121 int j;
122
123
124 for (j = i; j < NUM_INTS; j += interval) {
125 if ((ohci->load [j] + load) > 900)
126 break;
127 }
128 if (j < NUM_INTS)
129 continue;
130 branch = i;
131 }
132 }
133 return branch;
134}
135
136
137
138
139
140
141
142static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
143{
144 unsigned i;
145
146 ohci_dbg(ohci, "link %sed %p branch %d [%dus.], interval %d\n",
147 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
148 ed, ed->branch, ed->load, ed->interval);
149
150 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
151 struct ed **prev = &ohci->periodic [i];
152 __hc32 *prev_p = &ohci->hcca->int_table [i];
153 struct ed *here = *prev;
154
155
156
157
158
159 while (here && ed != here) {
160 if (ed->interval > here->interval)
161 break;
162 prev = &here->ed_next;
163 prev_p = &here->hwNextED;
164 here = *prev;
165 }
166 if (ed != here) {
167 ed->ed_next = here;
168 if (here)
169 ed->hwNextED = *prev_p;
170 wmb ();
171 *prev = ed;
172 *prev_p = cpu_to_hc32(ohci, ed->dma);
173 wmb();
174 }
175 ohci->load [i] += ed->load;
176 }
177 ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
178}
179
180
181
182static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
183{
184 int branch;
185
186 ed->state = ED_OPER;
187 ed->ed_prev = NULL;
188 ed->ed_next = NULL;
189 ed->hwNextED = 0;
190 wmb ();
191
192
193
194
195
196
197
198
199
200
201
202 switch (ed->type) {
203 case PIPE_CONTROL:
204 if (ohci->ed_controltail == NULL) {
205 WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
206 ohci_writel (ohci, ed->dma,
207 &ohci->regs->ed_controlhead);
208 } else {
209 ohci->ed_controltail->ed_next = ed;
210 ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
211 ed->dma);
212 }
213 ed->ed_prev = ohci->ed_controltail;
214 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
215 wmb();
216 ohci->hc_control |= OHCI_CTRL_CLE;
217 ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
218 ohci_writel (ohci, ohci->hc_control,
219 &ohci->regs->control);
220 }
221 ohci->ed_controltail = ed;
222 break;
223
224 case PIPE_BULK:
225 if (ohci->ed_bulktail == NULL) {
226 WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
227 ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
228 } else {
229 ohci->ed_bulktail->ed_next = ed;
230 ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
231 ed->dma);
232 }
233 ed->ed_prev = ohci->ed_bulktail;
234 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
235 wmb();
236 ohci->hc_control |= OHCI_CTRL_BLE;
237 ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
238 ohci_writel (ohci, ohci->hc_control,
239 &ohci->regs->control);
240 }
241 ohci->ed_bulktail = ed;
242 break;
243
244
245
246 default:
247 branch = balance (ohci, ed->interval, ed->load);
248 if (branch < 0) {
249 ohci_dbg (ohci,
250 "ERR %d, interval %d msecs, load %d\n",
251 branch, ed->interval, ed->load);
252
253 return branch;
254 }
255 ed->branch = branch;
256 periodic_link (ohci, ed);
257 }
258
259
260
261
262 return 0;
263}
264
265
266
267
268static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
269{
270 int i;
271
272 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
273 struct ed *temp;
274 struct ed **prev = &ohci->periodic [i];
275 __hc32 *prev_p = &ohci->hcca->int_table [i];
276
277 while (*prev && (temp = *prev) != ed) {
278 prev_p = &temp->hwNextED;
279 prev = &temp->ed_next;
280 }
281 if (*prev) {
282 *prev_p = ed->hwNextED;
283 *prev = ed->ed_next;
284 }
285 ohci->load [i] -= ed->load;
286 }
287 ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
288
289 ohci_dbg(ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
290 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
291 ed, ed->branch, ed->load, ed->interval);
292}
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
316{
317 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
318 wmb ();
319 ed->state = ED_UNLINK;
320
321
322
323
324
325
326
327
328
329
330
331 switch (ed->type) {
332 case PIPE_CONTROL:
333
334 if (ed->ed_prev == NULL) {
335 if (!ed->hwNextED) {
336 ohci->hc_control &= ~OHCI_CTRL_CLE;
337 ohci_writel (ohci, ohci->hc_control,
338 &ohci->regs->control);
339
340 } else
341 ohci_writel (ohci,
342 hc32_to_cpup (ohci, &ed->hwNextED),
343 &ohci->regs->ed_controlhead);
344 } else {
345 ed->ed_prev->ed_next = ed->ed_next;
346 ed->ed_prev->hwNextED = ed->hwNextED;
347 }
348
349 if (ohci->ed_controltail == ed) {
350 ohci->ed_controltail = ed->ed_prev;
351 if (ohci->ed_controltail)
352 ohci->ed_controltail->ed_next = NULL;
353 } else if (ed->ed_next) {
354 ed->ed_next->ed_prev = ed->ed_prev;
355 }
356 break;
357
358 case PIPE_BULK:
359
360 if (ed->ed_prev == NULL) {
361 if (!ed->hwNextED) {
362 ohci->hc_control &= ~OHCI_CTRL_BLE;
363 ohci_writel (ohci, ohci->hc_control,
364 &ohci->regs->control);
365
366 } else
367 ohci_writel (ohci,
368 hc32_to_cpup (ohci, &ed->hwNextED),
369 &ohci->regs->ed_bulkhead);
370 } else {
371 ed->ed_prev->ed_next = ed->ed_next;
372 ed->ed_prev->hwNextED = ed->hwNextED;
373 }
374
375 if (ohci->ed_bulktail == ed) {
376 ohci->ed_bulktail = ed->ed_prev;
377 if (ohci->ed_bulktail)
378 ohci->ed_bulktail->ed_next = NULL;
379 } else if (ed->ed_next) {
380 ed->ed_next->ed_prev = ed->ed_prev;
381 }
382 break;
383
384
385
386 default:
387 periodic_unlink (ohci, ed);
388 break;
389 }
390}
391
392
393
394
395
396
397
398static struct ed *ed_get (
399 struct ohci_hcd *ohci,
400 struct usb_host_endpoint *ep,
401 struct usb_device *udev,
402 unsigned int pipe,
403 int interval
404) {
405 struct ed *ed;
406 unsigned long flags;
407
408 spin_lock_irqsave (&ohci->lock, flags);
409
410 if (!(ed = ep->hcpriv)) {
411 struct td *td;
412 int is_out;
413 u32 info;
414
415 ed = ed_alloc (ohci, GFP_ATOMIC);
416 if (!ed) {
417
418 goto done;
419 }
420
421
422 td = td_alloc (ohci, GFP_ATOMIC);
423 if (!td) {
424
425 ed_free (ohci, ed);
426 ed = NULL;
427 goto done;
428 }
429 ed->dummy = td;
430 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
431 ed->hwHeadP = ed->hwTailP;
432 ed->state = ED_IDLE;
433
434 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
435
436
437
438
439 info = usb_pipedevice (pipe);
440 ed->type = usb_pipetype(pipe);
441
442 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
443 info |= usb_endpoint_maxp(&ep->desc) << 16;
444 if (udev->speed == USB_SPEED_LOW)
445 info |= ED_LOWSPEED;
446
447 if (ed->type != PIPE_CONTROL) {
448 info |= is_out ? ED_OUT : ED_IN;
449 if (ed->type != PIPE_BULK) {
450
451 if (ed->type == PIPE_ISOCHRONOUS)
452 info |= ED_ISO;
453 else if (interval > 32)
454 interval = 32;
455 ed->interval = interval;
456 ed->load = usb_calc_bus_time (
457 udev->speed, !is_out,
458 ed->type == PIPE_ISOCHRONOUS,
459 usb_endpoint_maxp(&ep->desc))
460 / 1000;
461 }
462 }
463 ed->hwINFO = cpu_to_hc32(ohci, info);
464
465 ep->hcpriv = ed;
466 }
467
468done:
469 spin_unlock_irqrestore (&ohci->lock, flags);
470 return ed;
471}
472
473
474
475
476
477
478
479
480
481static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
482{
483 ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
484 ed_deschedule (ohci, ed);
485
486
487 ed->ed_next = ohci->ed_rm_list;
488 ed->ed_prev = NULL;
489 ohci->ed_rm_list = ed;
490
491
492 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
493 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
494
495 (void) ohci_readl (ohci, &ohci->regs->control);
496
497
498
499
500
501
502 ed->tick = ohci_frame_no(ohci) + 1;
503
504}
505
506
507
508
509
510
511
512static void
513td_fill (struct ohci_hcd *ohci, u32 info,
514 dma_addr_t data, int len,
515 struct urb *urb, int index)
516{
517 struct td *td, *td_pt;
518 struct urb_priv *urb_priv = urb->hcpriv;
519 int is_iso = info & TD_ISO;
520 int hash;
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535 if (index != (urb_priv->length - 1)
536 || (urb->transfer_flags & URB_NO_INTERRUPT))
537 info |= TD_DI_SET (6);
538
539
540 td_pt = urb_priv->td [index];
541
542
543 td = urb_priv->td [index] = urb_priv->ed->dummy;
544 urb_priv->ed->dummy = td_pt;
545
546 td->ed = urb_priv->ed;
547 td->next_dl_td = NULL;
548 td->index = index;
549 td->urb = urb;
550 td->data_dma = data;
551 if (!len)
552 data = 0;
553
554 td->hwINFO = cpu_to_hc32 (ohci, info);
555 if (is_iso) {
556 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
557 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
558 (data & 0x0FFF) | 0xE000);
559 } else {
560 td->hwCBP = cpu_to_hc32 (ohci, data);
561 }
562 if (data)
563 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
564 else
565 td->hwBE = 0;
566 td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
567
568
569 list_add_tail (&td->td_list, &td->ed->td_list);
570
571
572 hash = TD_HASH_FUNC (td->td_dma);
573 td->td_hash = ohci->td_hash [hash];
574 ohci->td_hash [hash] = td;
575
576
577 wmb ();
578 td->ed->hwTailP = td->hwNextTD;
579}
580
581
582
583
584
585
586
587
588static void td_submit_urb (
589 struct ohci_hcd *ohci,
590 struct urb *urb
591) {
592 struct urb_priv *urb_priv = urb->hcpriv;
593 struct device *dev = ohci_to_hcd(ohci)->self.controller;
594 dma_addr_t data;
595 int data_len = urb->transfer_buffer_length;
596 int cnt = 0;
597 u32 info = 0;
598 int is_out = usb_pipeout (urb->pipe);
599 int periodic = 0;
600 int i, this_sg_len, n;
601 struct scatterlist *sg;
602
603
604
605
606
607 if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
608 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
609 is_out, 1);
610 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
611 }
612
613 list_add (&urb_priv->pending, &ohci->pending);
614
615 i = urb->num_mapped_sgs;
616 if (data_len > 0 && i > 0) {
617 sg = urb->sg;
618 data = sg_dma_address(sg);
619
620
621
622
623
624 this_sg_len = min_t(int, sg_dma_len(sg), data_len);
625 } else {
626 sg = NULL;
627 if (data_len)
628 data = urb->transfer_dma;
629 else
630 data = 0;
631 this_sg_len = data_len;
632 }
633
634
635
636
637
638 switch (urb_priv->ed->type) {
639
640
641
642
643 case PIPE_INTERRUPT:
644
645 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
646 && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
647
648 case PIPE_BULK:
649 info = is_out
650 ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
651 : TD_T_TOGGLE | TD_CC | TD_DP_IN;
652
653 for (;;) {
654 n = min(this_sg_len, 4096);
655
656
657 if (n >= data_len || (i == 1 && n >= this_sg_len)) {
658 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
659 info |= TD_R;
660 }
661 td_fill(ohci, info, data, n, urb, cnt);
662 this_sg_len -= n;
663 data_len -= n;
664 data += n;
665 cnt++;
666
667 if (this_sg_len <= 0) {
668 if (--i <= 0 || data_len <= 0)
669 break;
670 sg = sg_next(sg);
671 data = sg_dma_address(sg);
672 this_sg_len = min_t(int, sg_dma_len(sg),
673 data_len);
674 }
675 }
676 if ((urb->transfer_flags & URB_ZERO_PACKET)
677 && cnt < urb_priv->length) {
678 td_fill (ohci, info, 0, 0, urb, cnt);
679 cnt++;
680 }
681
682 if (urb_priv->ed->type == PIPE_BULK) {
683 wmb ();
684 ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
685 }
686 break;
687
688
689
690
691 case PIPE_CONTROL:
692 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
693 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
694 if (data_len > 0) {
695 info = TD_CC | TD_R | TD_T_DATA1;
696 info |= is_out ? TD_DP_OUT : TD_DP_IN;
697
698 td_fill (ohci, info, data, data_len, urb, cnt++);
699 }
700 info = (is_out || data_len == 0)
701 ? TD_CC | TD_DP_IN | TD_T_DATA1
702 : TD_CC | TD_DP_OUT | TD_T_DATA1;
703 td_fill (ohci, info, data, 0, urb, cnt++);
704
705 wmb ();
706 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
707 break;
708
709
710
711
712
713 case PIPE_ISOCHRONOUS:
714 for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
715 cnt++) {
716 int frame = urb->start_frame;
717
718
719
720
721 frame += cnt * urb->interval;
722 frame &= 0xffff;
723 td_fill (ohci, TD_CC | TD_ISO | frame,
724 data + urb->iso_frame_desc [cnt].offset,
725 urb->iso_frame_desc [cnt].length, urb, cnt);
726 }
727 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
728 if (quirk_amdiso(ohci))
729 usb_amd_quirk_pll_disable();
730 if (quirk_amdprefetch(ohci))
731 sb800_prefetch(dev, 1);
732 }
733 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
734 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
735 break;
736 }
737
738
739 if (periodic) {
740 wmb ();
741 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
742 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
743 }
744
745
746}
747
748
749
750
751
752
753static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
754{
755 u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
756 int cc = 0;
757 int status = -EINPROGRESS;
758
759 list_del (&td->td_list);
760
761
762 if (tdINFO & TD_ISO) {
763 u16 tdPSW = ohci_hwPSW(ohci, td, 0);
764 int dlen = 0;
765
766
767
768
769
770 cc = (tdPSW >> 12) & 0xF;
771 if (tdINFO & TD_CC)
772 return status;
773
774 if (usb_pipeout (urb->pipe))
775 dlen = urb->iso_frame_desc [td->index].length;
776 else {
777
778 if (cc == TD_DATAUNDERRUN)
779 cc = TD_CC_NOERROR;
780 dlen = tdPSW & 0x3ff;
781 }
782 urb->actual_length += dlen;
783 urb->iso_frame_desc [td->index].actual_length = dlen;
784 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
785
786 if (cc != TD_CC_NOERROR)
787 ohci_dbg(ohci,
788 "urb %p iso td %p (%d) len %d cc %d\n",
789 urb, td, 1 + td->index, dlen, cc);
790
791
792
793
794
795 } else {
796 int type = usb_pipetype (urb->pipe);
797 u32 tdBE = hc32_to_cpup (ohci, &td->hwBE);
798
799 cc = TD_CC_GET (tdINFO);
800
801
802 if (cc == TD_DATAUNDERRUN
803 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
804 cc = TD_CC_NOERROR;
805 if (cc != TD_CC_NOERROR && cc < 0x0E)
806 status = cc_to_error[cc];
807
808
809 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
810 if (td->hwCBP == 0)
811 urb->actual_length += tdBE - td->data_dma + 1;
812 else
813 urb->actual_length +=
814 hc32_to_cpup (ohci, &td->hwCBP)
815 - td->data_dma;
816 }
817
818 if (cc != TD_CC_NOERROR && cc < 0x0E)
819 ohci_dbg(ohci,
820 "urb %p td %p (%d) cc %d, len=%d/%d\n",
821 urb, td, 1 + td->index, cc,
822 urb->actual_length,
823 urb->transfer_buffer_length);
824 }
825 return status;
826}
827
828
829
830static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
831{
832 struct urb *urb = td->urb;
833 urb_priv_t *urb_priv = urb->hcpriv;
834 struct ed *ed = td->ed;
835 struct list_head *tmp = td->td_list.next;
836 __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
837
838
839
840
841 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
842 wmb ();
843 ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
844
845
846
847
848
849 while (tmp != &ed->td_list) {
850 struct td *next;
851
852 next = list_entry (tmp, struct td, td_list);
853 tmp = next->td_list.next;
854
855 if (next->urb != urb)
856 break;
857
858
859
860
861
862
863
864
865
866 list_del(&next->td_list);
867 urb_priv->td_cnt++;
868 ed->hwHeadP = next->hwNextTD | toggle;
869 }
870
871
872
873
874
875 switch (cc) {
876 case TD_DATAUNDERRUN:
877 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
878 break;
879
880 case TD_CC_STALL:
881 if (usb_pipecontrol (urb->pipe))
882 break;
883
884 default:
885 ohci_dbg (ohci,
886 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
887 urb, urb->dev->devpath,
888 usb_pipeendpoint (urb->pipe),
889 usb_pipein (urb->pipe) ? "in" : "out",
890 hc32_to_cpu (ohci, td->hwINFO),
891 cc, cc_to_error [cc]);
892 }
893}
894
895
896static void add_to_done_list(struct ohci_hcd *ohci, struct td *td)
897{
898 struct td *td2, *td_prev;
899 struct ed *ed;
900
901 if (td->next_dl_td)
902 return;
903
904
905 ed = td->ed;
906 td2 = td_prev = td;
907 list_for_each_entry_continue_reverse(td2, &ed->td_list, td_list) {
908 if (td2->next_dl_td)
909 break;
910 td2->next_dl_td = td_prev;
911 td_prev = td2;
912 }
913
914 if (ohci->dl_end)
915 ohci->dl_end->next_dl_td = td_prev;
916 else
917 ohci->dl_start = td_prev;
918
919
920
921
922
923 ohci->dl_end = td->next_dl_td = td;
924
925
926 td2 = ed->pending_td;
927 if (td2 && td2->next_dl_td)
928 ed->pending_td = NULL;
929}
930
931
932static void update_done_list(struct ohci_hcd *ohci)
933{
934 u32 td_dma;
935 struct td *td = NULL;
936
937 td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
938 ohci->hcca->done_head = 0;
939 wmb();
940
941
942
943
944 while (td_dma) {
945 int cc;
946
947 td = dma_to_td (ohci, td_dma);
948 if (!td) {
949 ohci_err (ohci, "bad entry %8x\n", td_dma);
950 break;
951 }
952
953 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
954 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
955
956
957
958
959
960 if (cc != TD_CC_NOERROR
961 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
962 ed_halted(ohci, td, cc);
963
964 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
965 add_to_done_list(ohci, td);
966 }
967}
968
969
970
971
972static void finish_unlinks(struct ohci_hcd *ohci)
973{
974 unsigned tick = ohci_frame_no(ohci);
975 struct ed *ed, **last;
976
977rescan_all:
978 for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
979 struct list_head *entry, *tmp;
980 int completed, modified;
981 __hc32 *prev;
982
983
984 if (ed->state == ED_IDLE)
985 goto ed_idle;
986
987
988
989
990 if (likely(ohci->rh_state == OHCI_RH_RUNNING) &&
991 tick_before(tick, ed->tick)) {
992skip_ed:
993 last = &ed->ed_next;
994 continue;
995 }
996 if (!list_empty(&ed->td_list)) {
997 struct td *td;
998 u32 head;
999
1000 td = list_first_entry(&ed->td_list, struct td, td_list);
1001
1002
1003 head = hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK;
1004 if (td->td_dma != head &&
1005 ohci->rh_state == OHCI_RH_RUNNING)
1006 goto skip_ed;
1007
1008
1009 if (td->next_dl_td)
1010 goto skip_ed;
1011 }
1012
1013
1014 ed->state = ED_IDLE;
1015 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1016 ed->hwNextED = 0;
1017 wmb();
1018 ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE);
1019ed_idle:
1020
1021
1022
1023
1024
1025 modified = 0;
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035rescan_this:
1036 completed = 0;
1037 prev = &ed->hwHeadP;
1038 list_for_each_safe (entry, tmp, &ed->td_list) {
1039 struct td *td;
1040 struct urb *urb;
1041 urb_priv_t *urb_priv;
1042 __hc32 savebits;
1043 u32 tdINFO;
1044
1045 td = list_entry (entry, struct td, td_list);
1046 urb = td->urb;
1047 urb_priv = td->urb->hcpriv;
1048
1049 if (!urb->unlinked) {
1050 prev = &td->hwNextTD;
1051 continue;
1052 }
1053
1054
1055 savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
1056 *prev = td->hwNextTD | savebits;
1057
1058
1059
1060
1061
1062
1063 tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
1064 if ((tdINFO & TD_T) == TD_T_DATA0)
1065 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
1066 else if ((tdINFO & TD_T) == TD_T_DATA1)
1067 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
1068
1069
1070 td_done (ohci, urb, td);
1071 urb_priv->td_cnt++;
1072
1073
1074 if (urb_priv->td_cnt >= urb_priv->length) {
1075 modified = completed = 1;
1076 finish_urb(ohci, urb, 0);
1077 }
1078 }
1079 if (completed && !list_empty (&ed->td_list))
1080 goto rescan_this;
1081
1082
1083
1084
1085
1086
1087 if (list_empty(&ed->td_list)) {
1088 *last = ed->ed_next;
1089 ed->ed_next = NULL;
1090 list_del(&ed->in_use_list);
1091 } else if (ohci->rh_state == OHCI_RH_RUNNING) {
1092 *last = ed->ed_next;
1093 ed->ed_next = NULL;
1094 ed_schedule(ohci, ed);
1095 } else {
1096 last = &ed->ed_next;
1097 }
1098
1099 if (modified)
1100 goto rescan_all;
1101 }
1102
1103
1104 if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
1105 u32 command = 0, control = 0;
1106
1107 if (ohci->ed_controltail) {
1108 command |= OHCI_CLF;
1109 if (quirk_zfmicro(ohci))
1110 mdelay(1);
1111 if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1112 control |= OHCI_CTRL_CLE;
1113 ohci_writel (ohci, 0,
1114 &ohci->regs->ed_controlcurrent);
1115 }
1116 }
1117 if (ohci->ed_bulktail) {
1118 command |= OHCI_BLF;
1119 if (quirk_zfmicro(ohci))
1120 mdelay(1);
1121 if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1122 control |= OHCI_CTRL_BLE;
1123 ohci_writel (ohci, 0,
1124 &ohci->regs->ed_bulkcurrent);
1125 }
1126 }
1127
1128
1129 if (control) {
1130 ohci->hc_control |= control;
1131 if (quirk_zfmicro(ohci))
1132 mdelay(1);
1133 ohci_writel (ohci, ohci->hc_control,
1134 &ohci->regs->control);
1135 }
1136 if (command) {
1137 if (quirk_zfmicro(ohci))
1138 mdelay(1);
1139 ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1140 }
1141 }
1142}
1143
1144
1145
1146
1147
1148
1149static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1150{
1151 struct urb *urb = td->urb;
1152 urb_priv_t *urb_priv = urb->hcpriv;
1153 struct ed *ed = td->ed;
1154 int status;
1155
1156
1157 status = td_done(ohci, urb, td);
1158 urb_priv->td_cnt++;
1159
1160
1161 if (urb_priv->td_cnt >= urb_priv->length)
1162 finish_urb(ohci, urb, status);
1163
1164
1165 if (list_empty(&ed->td_list)) {
1166 if (ed->state == ED_OPER)
1167 start_ed_unlink(ohci, ed);
1168
1169
1170 } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1171 == cpu_to_hc32(ohci, ED_SKIP)) {
1172 td = list_entry(ed->td_list.next, struct td, td_list);
1173 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1174 ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1175
1176 switch (ed->type) {
1177 case PIPE_CONTROL:
1178 ohci_writel(ohci, OHCI_CLF,
1179 &ohci->regs->cmdstatus);
1180 break;
1181 case PIPE_BULK:
1182 ohci_writel(ohci, OHCI_BLF,
1183 &ohci->regs->cmdstatus);
1184 break;
1185 }
1186 }
1187 }
1188}
1189
1190
1191
1192
1193
1194
1195
1196
1197static void process_done_list(struct ohci_hcd *ohci)
1198{
1199 struct td *td;
1200
1201 while (ohci->dl_start) {
1202 td = ohci->dl_start;
1203 if (td == ohci->dl_end)
1204 ohci->dl_start = ohci->dl_end = NULL;
1205 else
1206 ohci->dl_start = td->next_dl_td;
1207
1208 takeback_td(ohci, td);
1209 }
1210}
1211
1212
1213
1214
1215
1216static void ohci_work(struct ohci_hcd *ohci)
1217{
1218 if (ohci->working) {
1219 ohci->restart_work = 1;
1220 return;
1221 }
1222 ohci->working = 1;
1223
1224 restart:
1225 process_done_list(ohci);
1226 if (ohci->ed_rm_list)
1227 finish_unlinks(ohci);
1228
1229 if (ohci->restart_work) {
1230 ohci->restart_work = 0;
1231 goto restart;
1232 }
1233 ohci->working = 0;
1234}
1235