linux/drivers/video/fbdev/mx3fb.c
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   1/*
   2 * Copyright (C) 2008
   3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
   4 *
   5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/kernel.h>
  14#include <linux/platform_device.h>
  15#include <linux/sched.h>
  16#include <linux/errno.h>
  17#include <linux/string.h>
  18#include <linux/interrupt.h>
  19#include <linux/slab.h>
  20#include <linux/fb.h>
  21#include <linux/delay.h>
  22#include <linux/init.h>
  23#include <linux/ioport.h>
  24#include <linux/dma-mapping.h>
  25#include <linux/dmaengine.h>
  26#include <linux/console.h>
  27#include <linux/clk.h>
  28#include <linux/mutex.h>
  29#include <linux/dma/ipu-dma.h>
  30#include <linux/backlight.h>
  31
  32#include <linux/platform_data/dma-imx.h>
  33#include <linux/platform_data/video-mx3fb.h>
  34
  35#include <asm/io.h>
  36#include <asm/uaccess.h>
  37
  38#define MX3FB_NAME              "mx3_sdc_fb"
  39
  40#define MX3FB_REG_OFFSET        0xB4
  41
  42/* SDC Registers */
  43#define SDC_COM_CONF            (0xB4 - MX3FB_REG_OFFSET)
  44#define SDC_GW_CTRL             (0xB8 - MX3FB_REG_OFFSET)
  45#define SDC_FG_POS              (0xBC - MX3FB_REG_OFFSET)
  46#define SDC_BG_POS              (0xC0 - MX3FB_REG_OFFSET)
  47#define SDC_CUR_POS             (0xC4 - MX3FB_REG_OFFSET)
  48#define SDC_PWM_CTRL            (0xC8 - MX3FB_REG_OFFSET)
  49#define SDC_CUR_MAP             (0xCC - MX3FB_REG_OFFSET)
  50#define SDC_HOR_CONF            (0xD0 - MX3FB_REG_OFFSET)
  51#define SDC_VER_CONF            (0xD4 - MX3FB_REG_OFFSET)
  52#define SDC_SHARP_CONF_1        (0xD8 - MX3FB_REG_OFFSET)
  53#define SDC_SHARP_CONF_2        (0xDC - MX3FB_REG_OFFSET)
  54
  55/* Register bits */
  56#define SDC_COM_TFT_COLOR       0x00000001UL
  57#define SDC_COM_FG_EN           0x00000010UL
  58#define SDC_COM_GWSEL           0x00000020UL
  59#define SDC_COM_GLB_A           0x00000040UL
  60#define SDC_COM_KEY_COLOR_G     0x00000080UL
  61#define SDC_COM_BG_EN           0x00000200UL
  62#define SDC_COM_SHARP           0x00001000UL
  63
  64#define SDC_V_SYNC_WIDTH_L      0x00000001UL
  65
  66/* Display Interface registers */
  67#define DI_DISP_IF_CONF         (0x0124 - MX3FB_REG_OFFSET)
  68#define DI_DISP_SIG_POL         (0x0128 - MX3FB_REG_OFFSET)
  69#define DI_SER_DISP1_CONF       (0x012C - MX3FB_REG_OFFSET)
  70#define DI_SER_DISP2_CONF       (0x0130 - MX3FB_REG_OFFSET)
  71#define DI_HSP_CLK_PER          (0x0134 - MX3FB_REG_OFFSET)
  72#define DI_DISP0_TIME_CONF_1    (0x0138 - MX3FB_REG_OFFSET)
  73#define DI_DISP0_TIME_CONF_2    (0x013C - MX3FB_REG_OFFSET)
  74#define DI_DISP0_TIME_CONF_3    (0x0140 - MX3FB_REG_OFFSET)
  75#define DI_DISP1_TIME_CONF_1    (0x0144 - MX3FB_REG_OFFSET)
  76#define DI_DISP1_TIME_CONF_2    (0x0148 - MX3FB_REG_OFFSET)
  77#define DI_DISP1_TIME_CONF_3    (0x014C - MX3FB_REG_OFFSET)
  78#define DI_DISP2_TIME_CONF_1    (0x0150 - MX3FB_REG_OFFSET)
  79#define DI_DISP2_TIME_CONF_2    (0x0154 - MX3FB_REG_OFFSET)
  80#define DI_DISP2_TIME_CONF_3    (0x0158 - MX3FB_REG_OFFSET)
  81#define DI_DISP3_TIME_CONF      (0x015C - MX3FB_REG_OFFSET)
  82#define DI_DISP0_DB0_MAP        (0x0160 - MX3FB_REG_OFFSET)
  83#define DI_DISP0_DB1_MAP        (0x0164 - MX3FB_REG_OFFSET)
  84#define DI_DISP0_DB2_MAP        (0x0168 - MX3FB_REG_OFFSET)
  85#define DI_DISP0_CB0_MAP        (0x016C - MX3FB_REG_OFFSET)
  86#define DI_DISP0_CB1_MAP        (0x0170 - MX3FB_REG_OFFSET)
  87#define DI_DISP0_CB2_MAP        (0x0174 - MX3FB_REG_OFFSET)
  88#define DI_DISP1_DB0_MAP        (0x0178 - MX3FB_REG_OFFSET)
  89#define DI_DISP1_DB1_MAP        (0x017C - MX3FB_REG_OFFSET)
  90#define DI_DISP1_DB2_MAP        (0x0180 - MX3FB_REG_OFFSET)
  91#define DI_DISP1_CB0_MAP        (0x0184 - MX3FB_REG_OFFSET)
  92#define DI_DISP1_CB1_MAP        (0x0188 - MX3FB_REG_OFFSET)
  93#define DI_DISP1_CB2_MAP        (0x018C - MX3FB_REG_OFFSET)
  94#define DI_DISP2_DB0_MAP        (0x0190 - MX3FB_REG_OFFSET)
  95#define DI_DISP2_DB1_MAP        (0x0194 - MX3FB_REG_OFFSET)
  96#define DI_DISP2_DB2_MAP        (0x0198 - MX3FB_REG_OFFSET)
  97#define DI_DISP2_CB0_MAP        (0x019C - MX3FB_REG_OFFSET)
  98#define DI_DISP2_CB1_MAP        (0x01A0 - MX3FB_REG_OFFSET)
  99#define DI_DISP2_CB2_MAP        (0x01A4 - MX3FB_REG_OFFSET)
 100#define DI_DISP3_B0_MAP         (0x01A8 - MX3FB_REG_OFFSET)
 101#define DI_DISP3_B1_MAP         (0x01AC - MX3FB_REG_OFFSET)
 102#define DI_DISP3_B2_MAP         (0x01B0 - MX3FB_REG_OFFSET)
 103#define DI_DISP_ACC_CC          (0x01B4 - MX3FB_REG_OFFSET)
 104#define DI_DISP_LLA_CONF        (0x01B8 - MX3FB_REG_OFFSET)
 105#define DI_DISP_LLA_DATA        (0x01BC - MX3FB_REG_OFFSET)
 106
 107/* DI_DISP_SIG_POL bits */
 108#define DI_D3_VSYNC_POL_SHIFT           28
 109#define DI_D3_HSYNC_POL_SHIFT           27
 110#define DI_D3_DRDY_SHARP_POL_SHIFT      26
 111#define DI_D3_CLK_POL_SHIFT             25
 112#define DI_D3_DATA_POL_SHIFT            24
 113
 114/* DI_DISP_IF_CONF bits */
 115#define DI_D3_CLK_IDLE_SHIFT            26
 116#define DI_D3_CLK_SEL_SHIFT             25
 117#define DI_D3_DATAMSK_SHIFT             24
 118
 119enum ipu_panel {
 120        IPU_PANEL_SHARP_TFT,
 121        IPU_PANEL_TFT,
 122};
 123
 124struct ipu_di_signal_cfg {
 125        unsigned datamask_en:1;
 126        unsigned clksel_en:1;
 127        unsigned clkidle_en:1;
 128        unsigned data_pol:1;    /* true = inverted */
 129        unsigned clk_pol:1;     /* true = rising edge */
 130        unsigned enable_pol:1;
 131        unsigned Hsync_pol:1;   /* true = active high */
 132        unsigned Vsync_pol:1;
 133};
 134
 135static const struct fb_videomode mx3fb_modedb[] = {
 136        {
 137                /* 240x320 @ 60 Hz */
 138                .name           = "Sharp-QVGA",
 139                .refresh        = 60,
 140                .xres           = 240,
 141                .yres           = 320,
 142                .pixclock       = 185925,
 143                .left_margin    = 9,
 144                .right_margin   = 16,
 145                .upper_margin   = 7,
 146                .lower_margin   = 9,
 147                .hsync_len      = 1,
 148                .vsync_len      = 1,
 149                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
 150                                  FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
 151                                  FB_SYNC_CLK_IDLE_EN,
 152                .vmode          = FB_VMODE_NONINTERLACED,
 153                .flag           = 0,
 154        }, {
 155                /* 240x33 @ 60 Hz */
 156                .name           = "Sharp-CLI",
 157                .refresh        = 60,
 158                .xres           = 240,
 159                .yres           = 33,
 160                .pixclock       = 185925,
 161                .left_margin    = 9,
 162                .right_margin   = 16,
 163                .upper_margin   = 7,
 164                .lower_margin   = 9 + 287,
 165                .hsync_len      = 1,
 166                .vsync_len      = 1,
 167                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
 168                                  FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
 169                                  FB_SYNC_CLK_IDLE_EN,
 170                .vmode          = FB_VMODE_NONINTERLACED,
 171                .flag           = 0,
 172        }, {
 173                /* 640x480 @ 60 Hz */
 174                .name           = "NEC-VGA",
 175                .refresh        = 60,
 176                .xres           = 640,
 177                .yres           = 480,
 178                .pixclock       = 38255,
 179                .left_margin    = 144,
 180                .right_margin   = 0,
 181                .upper_margin   = 34,
 182                .lower_margin   = 40,
 183                .hsync_len      = 1,
 184                .vsync_len      = 1,
 185                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
 186                .vmode          = FB_VMODE_NONINTERLACED,
 187                .flag           = 0,
 188        }, {
 189                /* NTSC TV output */
 190                .name           = "TV-NTSC",
 191                .refresh        = 60,
 192                .xres           = 640,
 193                .yres           = 480,
 194                .pixclock       = 37538,
 195                .left_margin    = 38,
 196                .right_margin   = 858 - 640 - 38 - 3,
 197                .upper_margin   = 36,
 198                .lower_margin   = 518 - 480 - 36 - 1,
 199                .hsync_len      = 3,
 200                .vsync_len      = 1,
 201                .sync           = 0,
 202                .vmode          = FB_VMODE_NONINTERLACED,
 203                .flag           = 0,
 204        }, {
 205                /* PAL TV output */
 206                .name           = "TV-PAL",
 207                .refresh        = 50,
 208                .xres           = 640,
 209                .yres           = 480,
 210                .pixclock       = 37538,
 211                .left_margin    = 38,
 212                .right_margin   = 960 - 640 - 38 - 32,
 213                .upper_margin   = 32,
 214                .lower_margin   = 555 - 480 - 32 - 3,
 215                .hsync_len      = 32,
 216                .vsync_len      = 3,
 217                .sync           = 0,
 218                .vmode          = FB_VMODE_NONINTERLACED,
 219                .flag           = 0,
 220        }, {
 221                /* TV output VGA mode, 640x480 @ 65 Hz */
 222                .name           = "TV-VGA",
 223                .refresh        = 60,
 224                .xres           = 640,
 225                .yres           = 480,
 226                .pixclock       = 40574,
 227                .left_margin    = 35,
 228                .right_margin   = 45,
 229                .upper_margin   = 9,
 230                .lower_margin   = 1,
 231                .hsync_len      = 46,
 232                .vsync_len      = 5,
 233                .sync           = 0,
 234                .vmode          = FB_VMODE_NONINTERLACED,
 235                .flag           = 0,
 236        },
 237};
 238
 239struct mx3fb_data {
 240        struct fb_info          *fbi;
 241        int                     backlight_level;
 242        void __iomem            *reg_base;
 243        spinlock_t              lock;
 244        struct device           *dev;
 245        struct backlight_device *bl;
 246
 247        uint32_t                h_start_width;
 248        uint32_t                v_start_width;
 249        enum disp_data_mapping  disp_data_fmt;
 250};
 251
 252struct dma_chan_request {
 253        struct mx3fb_data       *mx3fb;
 254        enum ipu_channel        id;
 255};
 256
 257/* MX3 specific framebuffer information. */
 258struct mx3fb_info {
 259        int                             blank;
 260        enum ipu_channel                ipu_ch;
 261        uint32_t                        cur_ipu_buf;
 262
 263        u32                             pseudo_palette[16];
 264
 265        struct completion               flip_cmpl;
 266        struct mutex                    mutex;  /* Protects fb-ops */
 267        struct mx3fb_data               *mx3fb;
 268        struct idmac_channel            *idmac_channel;
 269        struct dma_async_tx_descriptor  *txd;
 270        dma_cookie_t                    cookie;
 271        struct scatterlist              sg[2];
 272
 273        struct fb_var_screeninfo        cur_var; /* current var info */
 274};
 275
 276static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value);
 277static u32 sdc_get_brightness(struct mx3fb_data *mx3fb);
 278
 279static int mx3fb_bl_get_brightness(struct backlight_device *bl)
 280{
 281        struct mx3fb_data *fbd = bl_get_data(bl);
 282
 283        return sdc_get_brightness(fbd);
 284}
 285
 286static int mx3fb_bl_update_status(struct backlight_device *bl)
 287{
 288        struct mx3fb_data *fbd = bl_get_data(bl);
 289        int brightness = bl->props.brightness;
 290
 291        if (bl->props.power != FB_BLANK_UNBLANK)
 292                brightness = 0;
 293        if (bl->props.fb_blank != FB_BLANK_UNBLANK)
 294                brightness = 0;
 295
 296        fbd->backlight_level = (fbd->backlight_level & ~0xFF) | brightness;
 297
 298        sdc_set_brightness(fbd, fbd->backlight_level);
 299
 300        return 0;
 301}
 302
 303static const struct backlight_ops mx3fb_lcdc_bl_ops = {
 304        .update_status = mx3fb_bl_update_status,
 305        .get_brightness = mx3fb_bl_get_brightness,
 306};
 307
 308static void mx3fb_init_backlight(struct mx3fb_data *fbd)
 309{
 310        struct backlight_properties props;
 311        struct backlight_device *bl;
 312
 313        if (fbd->bl)
 314                return;
 315
 316        memset(&props, 0, sizeof(struct backlight_properties));
 317        props.max_brightness = 0xff;
 318        props.type = BACKLIGHT_RAW;
 319        sdc_set_brightness(fbd, fbd->backlight_level);
 320
 321        bl = backlight_device_register("mx3fb-bl", fbd->dev, fbd,
 322                                       &mx3fb_lcdc_bl_ops, &props);
 323        if (IS_ERR(bl)) {
 324                dev_err(fbd->dev, "error %ld on backlight register\n",
 325                                PTR_ERR(bl));
 326                return;
 327        }
 328
 329        fbd->bl = bl;
 330        bl->props.power = FB_BLANK_UNBLANK;
 331        bl->props.fb_blank = FB_BLANK_UNBLANK;
 332        bl->props.brightness = mx3fb_bl_get_brightness(bl);
 333}
 334
 335static void mx3fb_exit_backlight(struct mx3fb_data *fbd)
 336{
 337        backlight_device_unregister(fbd->bl);
 338}
 339
 340static void mx3fb_dma_done(void *);
 341
 342/* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
 343static const char *fb_mode;
 344static unsigned long default_bpp = 16;
 345
 346static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
 347{
 348        return __raw_readl(mx3fb->reg_base + reg);
 349}
 350
 351static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
 352{
 353        __raw_writel(value, mx3fb->reg_base + reg);
 354}
 355
 356struct di_mapping {
 357        uint32_t b0, b1, b2;
 358};
 359
 360static const struct di_mapping di_mappings[] = {
 361        [IPU_DISP_DATA_MAPPING_RGB666] = { 0x0005000f, 0x000b000f, 0x0011000f },
 362        [IPU_DISP_DATA_MAPPING_RGB565] = { 0x0004003f, 0x000a000f, 0x000f003f },
 363        [IPU_DISP_DATA_MAPPING_RGB888] = { 0x00070000, 0x000f0000, 0x00170000 },
 364};
 365
 366static void sdc_fb_init(struct mx3fb_info *fbi)
 367{
 368        struct mx3fb_data *mx3fb = fbi->mx3fb;
 369        uint32_t reg;
 370
 371        reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
 372
 373        mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
 374}
 375
 376/* Returns enabled flag before uninit */
 377static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi)
 378{
 379        struct mx3fb_data *mx3fb = fbi->mx3fb;
 380        uint32_t reg;
 381
 382        reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
 383
 384        mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
 385
 386        return reg & SDC_COM_BG_EN;
 387}
 388
 389static void sdc_enable_channel(struct mx3fb_info *mx3_fbi)
 390{
 391        struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
 392        struct idmac_channel *ichan = mx3_fbi->idmac_channel;
 393        struct dma_chan *dma_chan = &ichan->dma_chan;
 394        unsigned long flags;
 395        dma_cookie_t cookie;
 396
 397        if (mx3_fbi->txd)
 398                dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
 399                        to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg);
 400        else
 401                dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi);
 402
 403        /* This enables the channel */
 404        if (mx3_fbi->cookie < 0) {
 405                mx3_fbi->txd = dmaengine_prep_slave_sg(dma_chan,
 406                      &mx3_fbi->sg[0], 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 407                if (!mx3_fbi->txd) {
 408                        dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
 409                                dma_chan->chan_id);
 410                        return;
 411                }
 412
 413                mx3_fbi->txd->callback_param    = mx3_fbi->txd;
 414                mx3_fbi->txd->callback          = mx3fb_dma_done;
 415
 416                cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd);
 417                dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
 418                       mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
 419        } else {
 420                if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) {
 421                        dev_err(mx3fb->dev, "Cannot enable channel %d\n",
 422                                dma_chan->chan_id);
 423                        return;
 424                }
 425
 426                /* Just re-activate the same buffer */
 427                dma_async_issue_pending(dma_chan);
 428                cookie = mx3_fbi->cookie;
 429                dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
 430                       mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
 431        }
 432
 433        if (cookie >= 0) {
 434                spin_lock_irqsave(&mx3fb->lock, flags);
 435                sdc_fb_init(mx3_fbi);
 436                mx3_fbi->cookie = cookie;
 437                spin_unlock_irqrestore(&mx3fb->lock, flags);
 438        }
 439
 440        /*
 441         * Attention! Without this msleep the channel keeps generating
 442         * interrupts. Next sdc_set_brightness() is going to be called
 443         * from mx3fb_blank().
 444         */
 445        msleep(2);
 446}
 447
 448static void sdc_disable_channel(struct mx3fb_info *mx3_fbi)
 449{
 450        struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
 451        uint32_t enabled;
 452        unsigned long flags;
 453
 454        if (mx3_fbi->txd == NULL)
 455                return;
 456
 457        spin_lock_irqsave(&mx3fb->lock, flags);
 458
 459        enabled = sdc_fb_uninit(mx3_fbi);
 460
 461        spin_unlock_irqrestore(&mx3fb->lock, flags);
 462
 463        dmaengine_terminate_all(mx3_fbi->txd->chan);
 464        mx3_fbi->txd = NULL;
 465        mx3_fbi->cookie = -EINVAL;
 466}
 467
 468/**
 469 * sdc_set_window_pos() - set window position of the respective plane.
 470 * @mx3fb:      mx3fb context.
 471 * @channel:    IPU DMAC channel ID.
 472 * @x_pos:      X coordinate relative to the top left corner to place window at.
 473 * @y_pos:      Y coordinate relative to the top left corner to place window at.
 474 * @return:     0 on success or negative error code on failure.
 475 */
 476static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
 477                              int16_t x_pos, int16_t y_pos)
 478{
 479        if (channel != IDMAC_SDC_0)
 480                return -EINVAL;
 481
 482        x_pos += mx3fb->h_start_width;
 483        y_pos += mx3fb->v_start_width;
 484
 485        mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
 486        return 0;
 487}
 488
 489/**
 490 * sdc_init_panel() - initialize a synchronous LCD panel.
 491 * @mx3fb:              mx3fb context.
 492 * @panel:              panel type.
 493 * @pixel_clk:          desired pixel clock frequency in Hz.
 494 * @width:              width of panel in pixels.
 495 * @height:             height of panel in pixels.
 496 * @h_start_width:      number of pixel clocks between the HSYNC signal pulse
 497 *                      and the start of valid data.
 498 * @h_sync_width:       width of the HSYNC signal in units of pixel clocks.
 499 * @h_end_width:        number of pixel clocks between the end of valid data
 500 *                      and the HSYNC signal for next line.
 501 * @v_start_width:      number of lines between the VSYNC signal pulse and the
 502 *                      start of valid data.
 503 * @v_sync_width:       width of the VSYNC signal in units of lines
 504 * @v_end_width:        number of lines between the end of valid data and the
 505 *                      VSYNC signal for next frame.
 506 * @sig:                bitfield of signal polarities for LCD interface.
 507 * @return:             0 on success or negative error code on failure.
 508 */
 509static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
 510                          uint32_t pixel_clk,
 511                          uint16_t width, uint16_t height,
 512                          uint16_t h_start_width, uint16_t h_sync_width,
 513                          uint16_t h_end_width, uint16_t v_start_width,
 514                          uint16_t v_sync_width, uint16_t v_end_width,
 515                          struct ipu_di_signal_cfg sig)
 516{
 517        unsigned long lock_flags;
 518        uint32_t reg;
 519        uint32_t old_conf;
 520        uint32_t div;
 521        struct clk *ipu_clk;
 522        const struct di_mapping *map;
 523
 524        dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
 525
 526        if (v_sync_width == 0 || h_sync_width == 0)
 527                return -EINVAL;
 528
 529        /* Init panel size and blanking periods */
 530        reg = ((uint32_t) (h_sync_width - 1) << 26) |
 531                ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
 532        mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
 533
 534#ifdef DEBUG
 535        printk(KERN_CONT " hor_conf %x,", reg);
 536#endif
 537
 538        reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
 539            ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
 540        mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
 541
 542#ifdef DEBUG
 543        printk(KERN_CONT " ver_conf %x\n", reg);
 544#endif
 545
 546        mx3fb->h_start_width = h_start_width;
 547        mx3fb->v_start_width = v_start_width;
 548
 549        switch (panel) {
 550        case IPU_PANEL_SHARP_TFT:
 551                mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
 552                mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
 553                mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
 554                break;
 555        case IPU_PANEL_TFT:
 556                mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
 557                break;
 558        default:
 559                return -EINVAL;
 560        }
 561
 562        /* Init clocking */
 563
 564        /*
 565         * Calculate divider: fractional part is 4 bits so simply multiple by
 566         * 2^4 to get fractional part, as long as we stay under ~250MHz and on
 567         * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
 568         */
 569        ipu_clk = clk_get(mx3fb->dev, NULL);
 570        if (!IS_ERR(ipu_clk)) {
 571                div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
 572                clk_put(ipu_clk);
 573        } else {
 574                div = 0;
 575        }
 576
 577        if (div < 0x40) {       /* Divider less than 4 */
 578                dev_dbg(mx3fb->dev,
 579                        "InitPanel() - Pixel clock divider less than 4\n");
 580                div = 0x40;
 581        }
 582
 583        dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
 584                pixel_clk, div >> 4, (div & 7) * 125);
 585
 586        spin_lock_irqsave(&mx3fb->lock, lock_flags);
 587
 588        /*
 589         * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
 590         * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
 591         * debug. DISP3_IF_CLK_UP_WR is 0
 592         */
 593        mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
 594
 595        /* DI settings */
 596        old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
 597        old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
 598                sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
 599                sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
 600        mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
 601
 602        old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
 603        old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
 604                sig.clk_pol << DI_D3_CLK_POL_SHIFT |
 605                sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
 606                sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
 607                sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
 608        mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
 609
 610        map = &di_mappings[mx3fb->disp_data_fmt];
 611        mx3fb_write_reg(mx3fb, map->b0, DI_DISP3_B0_MAP);
 612        mx3fb_write_reg(mx3fb, map->b1, DI_DISP3_B1_MAP);
 613        mx3fb_write_reg(mx3fb, map->b2, DI_DISP3_B2_MAP);
 614
 615        spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
 616
 617        dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
 618                mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
 619        dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
 620                mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
 621        dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
 622                mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
 623
 624        return 0;
 625}
 626
 627/**
 628 * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
 629 * @mx3fb:      mx3fb context.
 630 * @channel:    IPU DMAC channel ID.
 631 * @enable:     boolean to enable or disable color keyl.
 632 * @color_key:  24-bit RGB color to use as transparent color key.
 633 * @return:     0 on success or negative error code on failure.
 634 */
 635static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
 636                             bool enable, uint32_t color_key)
 637{
 638        uint32_t reg, sdc_conf;
 639        unsigned long lock_flags;
 640
 641        spin_lock_irqsave(&mx3fb->lock, lock_flags);
 642
 643        sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
 644        if (channel == IDMAC_SDC_0)
 645                sdc_conf &= ~SDC_COM_GWSEL;
 646        else
 647                sdc_conf |= SDC_COM_GWSEL;
 648
 649        if (enable) {
 650                reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
 651                mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
 652                             SDC_GW_CTRL);
 653
 654                sdc_conf |= SDC_COM_KEY_COLOR_G;
 655        } else {
 656                sdc_conf &= ~SDC_COM_KEY_COLOR_G;
 657        }
 658        mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
 659
 660        spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
 661
 662        return 0;
 663}
 664
 665/**
 666 * sdc_set_global_alpha() - set global alpha blending modes.
 667 * @mx3fb:      mx3fb context.
 668 * @enable:     boolean to enable or disable global alpha blending. If disabled,
 669 *              per pixel blending is used.
 670 * @alpha:      global alpha value.
 671 * @return:     0 on success or negative error code on failure.
 672 */
 673static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
 674{
 675        uint32_t reg;
 676        unsigned long lock_flags;
 677
 678        spin_lock_irqsave(&mx3fb->lock, lock_flags);
 679
 680        if (enable) {
 681                reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
 682                mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
 683
 684                reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
 685                mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
 686        } else {
 687                reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
 688                mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
 689        }
 690
 691        spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
 692
 693        return 0;
 694}
 695
 696static u32 sdc_get_brightness(struct mx3fb_data *mx3fb)
 697{
 698        u32 brightness;
 699
 700        brightness = mx3fb_read_reg(mx3fb, SDC_PWM_CTRL);
 701        brightness = (brightness >> 16) & 0xFF;
 702
 703        return brightness;
 704}
 705
 706static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
 707{
 708        dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value);
 709        /* This might be board-specific */
 710        mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
 711        return;
 712}
 713
 714static uint32_t bpp_to_pixfmt(int bpp)
 715{
 716        uint32_t pixfmt = 0;
 717        switch (bpp) {
 718        case 24:
 719                pixfmt = IPU_PIX_FMT_BGR24;
 720                break;
 721        case 32:
 722                pixfmt = IPU_PIX_FMT_BGR32;
 723                break;
 724        case 16:
 725                pixfmt = IPU_PIX_FMT_RGB565;
 726                break;
 727        }
 728        return pixfmt;
 729}
 730
 731static int mx3fb_blank(int blank, struct fb_info *fbi);
 732static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
 733                                  bool lock);
 734static int mx3fb_unmap_video_memory(struct fb_info *fbi);
 735
 736/**
 737 * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
 738 * @info:       framebuffer information pointer
 739 * @return:     0 on success or negative error code on failure.
 740 */
 741static int mx3fb_set_fix(struct fb_info *fbi)
 742{
 743        struct fb_fix_screeninfo *fix = &fbi->fix;
 744        struct fb_var_screeninfo *var = &fbi->var;
 745
 746        strncpy(fix->id, "DISP3 BG", 8);
 747
 748        fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
 749
 750        fix->type = FB_TYPE_PACKED_PIXELS;
 751        fix->accel = FB_ACCEL_NONE;
 752        fix->visual = FB_VISUAL_TRUECOLOR;
 753        fix->xpanstep = 1;
 754        fix->ypanstep = 1;
 755
 756        return 0;
 757}
 758
 759static void mx3fb_dma_done(void *arg)
 760{
 761        struct idmac_tx_desc *tx_desc = to_tx_desc(arg);
 762        struct dma_chan *chan = tx_desc->txd.chan;
 763        struct idmac_channel *ichannel = to_idmac_chan(chan);
 764        struct mx3fb_data *mx3fb = ichannel->client;
 765        struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
 766
 767        dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
 768
 769        /* We only need one interrupt, it will be re-enabled as needed */
 770        disable_irq_nosync(ichannel->eof_irq);
 771
 772        complete(&mx3_fbi->flip_cmpl);
 773}
 774
 775static bool mx3fb_must_set_par(struct fb_info *fbi)
 776{
 777        struct mx3fb_info *mx3_fbi = fbi->par;
 778        struct fb_var_screeninfo old_var = mx3_fbi->cur_var;
 779        struct fb_var_screeninfo new_var = fbi->var;
 780
 781        if ((fbi->var.activate & FB_ACTIVATE_FORCE) &&
 782            (fbi->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
 783                return true;
 784
 785        /*
 786         * Ignore xoffset and yoffset update,
 787         * because pan display handles this case.
 788         */
 789        old_var.xoffset = new_var.xoffset;
 790        old_var.yoffset = new_var.yoffset;
 791
 792        return !!memcmp(&old_var, &new_var, sizeof(struct fb_var_screeninfo));
 793}
 794
 795static int __set_par(struct fb_info *fbi, bool lock)
 796{
 797        u32 mem_len, cur_xoffset, cur_yoffset;
 798        struct ipu_di_signal_cfg sig_cfg;
 799        enum ipu_panel mode = IPU_PANEL_TFT;
 800        struct mx3fb_info *mx3_fbi = fbi->par;
 801        struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
 802        struct idmac_channel *ichan = mx3_fbi->idmac_channel;
 803        struct idmac_video_param *video = &ichan->params.video;
 804        struct scatterlist *sg = mx3_fbi->sg;
 805
 806        /* Total cleanup */
 807        if (mx3_fbi->txd)
 808                sdc_disable_channel(mx3_fbi);
 809
 810        mx3fb_set_fix(fbi);
 811
 812        mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
 813        if (mem_len > fbi->fix.smem_len) {
 814                if (fbi->fix.smem_start)
 815                        mx3fb_unmap_video_memory(fbi);
 816
 817                if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
 818                        return -ENOMEM;
 819        }
 820
 821        sg_init_table(&sg[0], 1);
 822        sg_init_table(&sg[1], 1);
 823
 824        sg_dma_address(&sg[0]) = fbi->fix.smem_start;
 825        sg_set_page(&sg[0], virt_to_page(fbi->screen_base),
 826                    fbi->fix.smem_len,
 827                    offset_in_page(fbi->screen_base));
 828
 829        if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
 830                memset(&sig_cfg, 0, sizeof(sig_cfg));
 831                if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
 832                        sig_cfg.Hsync_pol = true;
 833                if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
 834                        sig_cfg.Vsync_pol = true;
 835                if (fbi->var.sync & FB_SYNC_CLK_INVERT)
 836                        sig_cfg.clk_pol = true;
 837                if (fbi->var.sync & FB_SYNC_DATA_INVERT)
 838                        sig_cfg.data_pol = true;
 839                if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH)
 840                        sig_cfg.enable_pol = true;
 841                if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
 842                        sig_cfg.clkidle_en = true;
 843                if (fbi->var.sync & FB_SYNC_CLK_SEL_EN)
 844                        sig_cfg.clksel_en = true;
 845                if (fbi->var.sync & FB_SYNC_SHARP_MODE)
 846                        mode = IPU_PANEL_SHARP_TFT;
 847
 848                dev_dbg(fbi->device, "pixclock = %ul Hz\n",
 849                        (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
 850
 851                if (sdc_init_panel(mx3fb, mode,
 852                                   (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
 853                                   fbi->var.xres, fbi->var.yres,
 854                                   fbi->var.left_margin,
 855                                   fbi->var.hsync_len,
 856                                   fbi->var.right_margin +
 857                                   fbi->var.hsync_len,
 858                                   fbi->var.upper_margin,
 859                                   fbi->var.vsync_len,
 860                                   fbi->var.lower_margin +
 861                                   fbi->var.vsync_len, sig_cfg) != 0) {
 862                        dev_err(fbi->device,
 863                                "mx3fb: Error initializing panel.\n");
 864                        return -EINVAL;
 865                }
 866        }
 867
 868        sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
 869
 870        mx3_fbi->cur_ipu_buf    = 0;
 871
 872        video->out_pixel_fmt    = bpp_to_pixfmt(fbi->var.bits_per_pixel);
 873        video->out_width        = fbi->var.xres;
 874        video->out_height       = fbi->var.yres;
 875        video->out_stride       = fbi->var.xres_virtual;
 876
 877        if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
 878                sdc_enable_channel(mx3_fbi);
 879                /*
 880                 * sg[0] points to fb smem_start address
 881                 * and is actually active in controller.
 882                 */
 883                mx3_fbi->cur_var.xoffset = 0;
 884                mx3_fbi->cur_var.yoffset = 0;
 885        }
 886
 887        /*
 888         * Preserve xoffset and yoffest in case they are
 889         * inactive in controller as fb is blanked.
 890         */
 891        cur_xoffset = mx3_fbi->cur_var.xoffset;
 892        cur_yoffset = mx3_fbi->cur_var.yoffset;
 893        mx3_fbi->cur_var = fbi->var;
 894        mx3_fbi->cur_var.xoffset = cur_xoffset;
 895        mx3_fbi->cur_var.yoffset = cur_yoffset;
 896
 897        return 0;
 898}
 899
 900/**
 901 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
 902 * @fbi:        framebuffer information pointer.
 903 * @return:     0 on success or negative error code on failure.
 904 */
 905static int mx3fb_set_par(struct fb_info *fbi)
 906{
 907        struct mx3fb_info *mx3_fbi = fbi->par;
 908        struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
 909        struct idmac_channel *ichan = mx3_fbi->idmac_channel;
 910        int ret;
 911
 912        dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
 913
 914        mutex_lock(&mx3_fbi->mutex);
 915
 916        ret = mx3fb_must_set_par(fbi) ? __set_par(fbi, true) : 0;
 917
 918        mutex_unlock(&mx3_fbi->mutex);
 919
 920        return ret;
 921}
 922
 923/**
 924 * mx3fb_check_var() - check and adjust framebuffer variable parameters.
 925 * @var:        framebuffer variable parameters
 926 * @fbi:        framebuffer information pointer
 927 */
 928static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
 929{
 930        struct mx3fb_info *mx3_fbi = fbi->par;
 931        u32 vtotal;
 932        u32 htotal;
 933
 934        dev_dbg(fbi->device, "%s\n", __func__);
 935
 936        if (var->xres_virtual < var->xres)
 937                var->xres_virtual = var->xres;
 938        if (var->yres_virtual < var->yres)
 939                var->yres_virtual = var->yres;
 940
 941        if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
 942            (var->bits_per_pixel != 16))
 943                var->bits_per_pixel = default_bpp;
 944
 945        switch (var->bits_per_pixel) {
 946        case 16:
 947                var->red.length = 5;
 948                var->red.offset = 11;
 949                var->red.msb_right = 0;
 950
 951                var->green.length = 6;
 952                var->green.offset = 5;
 953                var->green.msb_right = 0;
 954
 955                var->blue.length = 5;
 956                var->blue.offset = 0;
 957                var->blue.msb_right = 0;
 958
 959                var->transp.length = 0;
 960                var->transp.offset = 0;
 961                var->transp.msb_right = 0;
 962                break;
 963        case 24:
 964                var->red.length = 8;
 965                var->red.offset = 16;
 966                var->red.msb_right = 0;
 967
 968                var->green.length = 8;
 969                var->green.offset = 8;
 970                var->green.msb_right = 0;
 971
 972                var->blue.length = 8;
 973                var->blue.offset = 0;
 974                var->blue.msb_right = 0;
 975
 976                var->transp.length = 0;
 977                var->transp.offset = 0;
 978                var->transp.msb_right = 0;
 979                break;
 980        case 32:
 981                var->red.length = 8;
 982                var->red.offset = 16;
 983                var->red.msb_right = 0;
 984
 985                var->green.length = 8;
 986                var->green.offset = 8;
 987                var->green.msb_right = 0;
 988
 989                var->blue.length = 8;
 990                var->blue.offset = 0;
 991                var->blue.msb_right = 0;
 992
 993                var->transp.length = 8;
 994                var->transp.offset = 24;
 995                var->transp.msb_right = 0;
 996                break;
 997        }
 998
 999        if (var->pixclock < 1000) {
1000                htotal = var->xres + var->right_margin + var->hsync_len +
1001                    var->left_margin;
1002                vtotal = var->yres + var->lower_margin + var->vsync_len +
1003                    var->upper_margin;
1004                var->pixclock = (vtotal * htotal * 6UL) / 100UL;
1005                var->pixclock = KHZ2PICOS(var->pixclock);
1006                dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n",
1007                        var->pixclock);
1008        }
1009
1010        var->height = -1;
1011        var->width = -1;
1012        var->grayscale = 0;
1013
1014        /* Preserve sync flags */
1015        var->sync |= mx3_fbi->cur_var.sync;
1016        mx3_fbi->cur_var.sync |= var->sync;
1017
1018        return 0;
1019}
1020
1021static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf)
1022{
1023        chan &= 0xffff;
1024        chan >>= 16 - bf->length;
1025        return chan << bf->offset;
1026}
1027
1028static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
1029                           unsigned int green, unsigned int blue,
1030                           unsigned int trans, struct fb_info *fbi)
1031{
1032        struct mx3fb_info *mx3_fbi = fbi->par;
1033        u32 val;
1034        int ret = 1;
1035
1036        dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno);
1037
1038        mutex_lock(&mx3_fbi->mutex);
1039        /*
1040         * If greyscale is true, then we convert the RGB value
1041         * to greyscale no matter what visual we are using.
1042         */
1043        if (fbi->var.grayscale)
1044                red = green = blue = (19595 * red + 38470 * green +
1045                                      7471 * blue) >> 16;
1046        switch (fbi->fix.visual) {
1047        case FB_VISUAL_TRUECOLOR:
1048                /*
1049                 * 16-bit True Colour.  We encode the RGB value
1050                 * according to the RGB bitfield information.
1051                 */
1052                if (regno < 16) {
1053                        u32 *pal = fbi->pseudo_palette;
1054
1055                        val = chan_to_field(red, &fbi->var.red);
1056                        val |= chan_to_field(green, &fbi->var.green);
1057                        val |= chan_to_field(blue, &fbi->var.blue);
1058
1059                        pal[regno] = val;
1060
1061                        ret = 0;
1062                }
1063                break;
1064
1065        case FB_VISUAL_STATIC_PSEUDOCOLOR:
1066        case FB_VISUAL_PSEUDOCOLOR:
1067                break;
1068        }
1069        mutex_unlock(&mx3_fbi->mutex);
1070
1071        return ret;
1072}
1073
1074static void __blank(int blank, struct fb_info *fbi)
1075{
1076        struct mx3fb_info *mx3_fbi = fbi->par;
1077        struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
1078        int was_blank = mx3_fbi->blank;
1079
1080        mx3_fbi->blank = blank;
1081
1082        /* Attention!
1083         * Do not call sdc_disable_channel() for a channel that is disabled
1084         * already! This will result in a kernel NULL pointer dereference
1085         * (mx3_fbi->txd is NULL). Hide the fact, that all blank modes are
1086         * handled equally by this driver.
1087         */
1088        if (blank > FB_BLANK_UNBLANK && was_blank > FB_BLANK_UNBLANK)
1089                return;
1090
1091        switch (blank) {
1092        case FB_BLANK_POWERDOWN:
1093        case FB_BLANK_VSYNC_SUSPEND:
1094        case FB_BLANK_HSYNC_SUSPEND:
1095        case FB_BLANK_NORMAL:
1096                sdc_set_brightness(mx3fb, 0);
1097                memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
1098                /* Give LCD time to update - enough for 50 and 60 Hz */
1099                msleep(25);
1100                sdc_disable_channel(mx3_fbi);
1101                break;
1102        case FB_BLANK_UNBLANK:
1103                sdc_enable_channel(mx3_fbi);
1104                sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1105                break;
1106        }
1107}
1108
1109/**
1110 * mx3fb_blank() - blank the display.
1111 */
1112static int mx3fb_blank(int blank, struct fb_info *fbi)
1113{
1114        struct mx3fb_info *mx3_fbi = fbi->par;
1115
1116        dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
1117                blank, fbi->screen_base, fbi->fix.smem_len);
1118
1119        if (mx3_fbi->blank == blank)
1120                return 0;
1121
1122        mutex_lock(&mx3_fbi->mutex);
1123        __blank(blank, fbi);
1124        mutex_unlock(&mx3_fbi->mutex);
1125
1126        return 0;
1127}
1128
1129/**
1130 * mx3fb_pan_display() - pan or wrap the display
1131 * @var:        variable screen buffer information.
1132 * @info:       framebuffer information pointer.
1133 *
1134 * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1135 */
1136static int mx3fb_pan_display(struct fb_var_screeninfo *var,
1137                             struct fb_info *fbi)
1138{
1139        struct mx3fb_info *mx3_fbi = fbi->par;
1140        u32 y_bottom;
1141        unsigned long base;
1142        off_t offset;
1143        dma_cookie_t cookie;
1144        struct scatterlist *sg = mx3_fbi->sg;
1145        struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan;
1146        struct dma_async_tx_descriptor *txd;
1147        int ret;
1148
1149        dev_dbg(fbi->device, "%s [%c]\n", __func__,
1150                list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+');
1151
1152        if (var->xoffset > 0) {
1153                dev_dbg(fbi->device, "x panning not supported\n");
1154                return -EINVAL;
1155        }
1156
1157        if (mx3_fbi->cur_var.xoffset == var->xoffset &&
1158            mx3_fbi->cur_var.yoffset == var->yoffset)
1159                return 0;       /* No change, do nothing */
1160
1161        y_bottom = var->yoffset;
1162
1163        if (!(var->vmode & FB_VMODE_YWRAP))
1164                y_bottom += fbi->var.yres;
1165
1166        if (y_bottom > fbi->var.yres_virtual)
1167                return -EINVAL;
1168
1169        mutex_lock(&mx3_fbi->mutex);
1170
1171        offset = var->yoffset * fbi->fix.line_length
1172               + var->xoffset * (fbi->var.bits_per_pixel / 8);
1173        base = fbi->fix.smem_start + offset;
1174
1175        dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n",
1176                mx3_fbi->cur_ipu_buf, base);
1177
1178        /*
1179         * We enable the End of Frame interrupt, which will free a tx-descriptor,
1180         * which we will need for the next dmaengine_prep_slave_sg(). The
1181         * IRQ-handler will disable the IRQ again.
1182         */
1183        init_completion(&mx3_fbi->flip_cmpl);
1184        enable_irq(mx3_fbi->idmac_channel->eof_irq);
1185
1186        ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10);
1187        if (ret <= 0) {
1188                mutex_unlock(&mx3_fbi->mutex);
1189                dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ?
1190                         "user interrupt" : "timeout");
1191                disable_irq(mx3_fbi->idmac_channel->eof_irq);
1192                return ret ? : -ETIMEDOUT;
1193        }
1194
1195        mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf;
1196
1197        sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base;
1198        sg_set_page(&sg[mx3_fbi->cur_ipu_buf],
1199                    virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len,
1200                    offset_in_page(fbi->screen_base + offset));
1201
1202        if (mx3_fbi->txd)
1203                async_tx_ack(mx3_fbi->txd);
1204
1205        txd = dmaengine_prep_slave_sg(dma_chan, sg +
1206                mx3_fbi->cur_ipu_buf, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
1207        if (!txd) {
1208                dev_err(fbi->device,
1209                        "Error preparing a DMA transaction descriptor.\n");
1210                mutex_unlock(&mx3_fbi->mutex);
1211                return -EIO;
1212        }
1213
1214        txd->callback_param     = txd;
1215        txd->callback           = mx3fb_dma_done;
1216
1217        /*
1218         * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1219         * should switch to another buffer
1220         */
1221        cookie = txd->tx_submit(txd);
1222        dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie);
1223        if (cookie < 0) {
1224                dev_err(fbi->device,
1225                        "Error updating SDC buf %d to address=0x%08lX\n",
1226                        mx3_fbi->cur_ipu_buf, base);
1227                mutex_unlock(&mx3_fbi->mutex);
1228                return -EIO;
1229        }
1230
1231        mx3_fbi->txd = txd;
1232
1233        fbi->var.xoffset = var->xoffset;
1234        fbi->var.yoffset = var->yoffset;
1235
1236        if (var->vmode & FB_VMODE_YWRAP)
1237                fbi->var.vmode |= FB_VMODE_YWRAP;
1238        else
1239                fbi->var.vmode &= ~FB_VMODE_YWRAP;
1240
1241        mx3_fbi->cur_var = fbi->var;
1242
1243        mutex_unlock(&mx3_fbi->mutex);
1244
1245        dev_dbg(fbi->device, "Update complete\n");
1246
1247        return 0;
1248}
1249
1250/*
1251 * This structure contains the pointers to the control functions that are
1252 * invoked by the core framebuffer driver to perform operations like
1253 * blitting, rectangle filling, copy regions and cursor definition.
1254 */
1255static struct fb_ops mx3fb_ops = {
1256        .owner = THIS_MODULE,
1257        .fb_set_par = mx3fb_set_par,
1258        .fb_check_var = mx3fb_check_var,
1259        .fb_setcolreg = mx3fb_setcolreg,
1260        .fb_pan_display = mx3fb_pan_display,
1261        .fb_fillrect = cfb_fillrect,
1262        .fb_copyarea = cfb_copyarea,
1263        .fb_imageblit = cfb_imageblit,
1264        .fb_blank = mx3fb_blank,
1265};
1266
1267#ifdef CONFIG_PM
1268/*
1269 * Power management hooks.      Note that we won't be called from IRQ context,
1270 * unlike the blank functions above, so we may sleep.
1271 */
1272
1273/*
1274 * Suspends the framebuffer and blanks the screen. Power management support
1275 */
1276static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state)
1277{
1278        struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1279        struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1280
1281        console_lock();
1282        fb_set_suspend(mx3fb->fbi, 1);
1283        console_unlock();
1284
1285        if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1286                sdc_disable_channel(mx3_fbi);
1287                sdc_set_brightness(mx3fb, 0);
1288
1289        }
1290        return 0;
1291}
1292
1293/*
1294 * Resumes the framebuffer and unblanks the screen. Power management support
1295 */
1296static int mx3fb_resume(struct platform_device *pdev)
1297{
1298        struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1299        struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1300
1301        if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1302                sdc_enable_channel(mx3_fbi);
1303                sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1304        }
1305
1306        console_lock();
1307        fb_set_suspend(mx3fb->fbi, 0);
1308        console_unlock();
1309
1310        return 0;
1311}
1312#else
1313#define mx3fb_suspend   NULL
1314#define mx3fb_resume    NULL
1315#endif
1316
1317/*
1318 * Main framebuffer functions
1319 */
1320
1321/**
1322 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
1323 * @fbi:        framebuffer information pointer
1324 * @mem_len:    length of mapped memory
1325 * @lock:       do not lock during initialisation
1326 * @return:     Error code indicating success or failure
1327 *
1328 * This buffer is remapped into a non-cached, non-buffered, memory region to
1329 * allow palette and pixel writes to occur without flushing the cache. Once this
1330 * area is remapped, all virtual memory access to the video memory should occur
1331 * at the new region.
1332 */
1333static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
1334                                  bool lock)
1335{
1336        int retval = 0;
1337        dma_addr_t addr;
1338
1339        fbi->screen_base = dma_alloc_writecombine(fbi->device,
1340                                                  mem_len,
1341                                                  &addr, GFP_DMA | GFP_KERNEL);
1342
1343        if (!fbi->screen_base) {
1344                dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n",
1345                        mem_len);
1346                retval = -EBUSY;
1347                goto err0;
1348        }
1349
1350        if (lock)
1351                mutex_lock(&fbi->mm_lock);
1352        fbi->fix.smem_start = addr;
1353        fbi->fix.smem_len = mem_len;
1354        if (lock)
1355                mutex_unlock(&fbi->mm_lock);
1356
1357        dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1358                (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
1359
1360        fbi->screen_size = fbi->fix.smem_len;
1361
1362        /* Clear the screen */
1363        memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
1364
1365        return 0;
1366
1367err0:
1368        fbi->fix.smem_len = 0;
1369        fbi->fix.smem_start = 0;
1370        fbi->screen_base = NULL;
1371        return retval;
1372}
1373
1374/**
1375 * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
1376 * @fbi:        framebuffer information pointer
1377 * @return:     error code indicating success or failure
1378 */
1379static int mx3fb_unmap_video_memory(struct fb_info *fbi)
1380{
1381        dma_free_writecombine(fbi->device, fbi->fix.smem_len,
1382                              fbi->screen_base, fbi->fix.smem_start);
1383
1384        fbi->screen_base = NULL;
1385        mutex_lock(&fbi->mm_lock);
1386        fbi->fix.smem_start = 0;
1387        fbi->fix.smem_len = 0;
1388        mutex_unlock(&fbi->mm_lock);
1389        return 0;
1390}
1391
1392/**
1393 * mx3fb_init_fbinfo() - initialize framebuffer information object.
1394 * @return:     initialized framebuffer structure.
1395 */
1396static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops)
1397{
1398        struct fb_info *fbi;
1399        struct mx3fb_info *mx3fbi;
1400        int ret;
1401
1402        /* Allocate sufficient memory for the fb structure */
1403        fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev);
1404        if (!fbi)
1405                return NULL;
1406
1407        mx3fbi                  = fbi->par;
1408        mx3fbi->cookie          = -EINVAL;
1409        mx3fbi->cur_ipu_buf     = 0;
1410
1411        fbi->var.activate       = FB_ACTIVATE_NOW;
1412
1413        fbi->fbops              = ops;
1414        fbi->flags              = FBINFO_FLAG_DEFAULT;
1415        fbi->pseudo_palette     = mx3fbi->pseudo_palette;
1416
1417        mutex_init(&mx3fbi->mutex);
1418
1419        /* Allocate colormap */
1420        ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
1421        if (ret < 0) {
1422                framebuffer_release(fbi);
1423                return NULL;
1424        }
1425
1426        return fbi;
1427}
1428
1429static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1430{
1431        struct device *dev = mx3fb->dev;
1432        struct mx3fb_platform_data *mx3fb_pdata = dev_get_platdata(dev);
1433        const char *name = mx3fb_pdata->name;
1434        unsigned int irq;
1435        struct fb_info *fbi;
1436        struct mx3fb_info *mx3fbi;
1437        const struct fb_videomode *mode;
1438        int ret, num_modes;
1439
1440        if (mx3fb_pdata->disp_data_fmt >= ARRAY_SIZE(di_mappings)) {
1441                dev_err(dev, "Illegal display data format %d\n",
1442                                mx3fb_pdata->disp_data_fmt);
1443                return -EINVAL;
1444        }
1445
1446        ichan->client = mx3fb;
1447        irq = ichan->eof_irq;
1448
1449        if (ichan->dma_chan.chan_id != IDMAC_SDC_0)
1450                return -EINVAL;
1451
1452        fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops);
1453        if (!fbi)
1454                return -ENOMEM;
1455
1456        if (!fb_mode)
1457                fb_mode = name;
1458
1459        if (!fb_mode) {
1460                ret = -EINVAL;
1461                goto emode;
1462        }
1463
1464        if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) {
1465                mode = mx3fb_pdata->mode;
1466                num_modes = mx3fb_pdata->num_modes;
1467        } else {
1468                mode = mx3fb_modedb;
1469                num_modes = ARRAY_SIZE(mx3fb_modedb);
1470        }
1471
1472        if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode,
1473                          num_modes, NULL, default_bpp)) {
1474                ret = -EBUSY;
1475                goto emode;
1476        }
1477
1478        fb_videomode_to_modelist(mode, num_modes, &fbi->modelist);
1479
1480        /* Default Y virtual size is 2x panel size */
1481        fbi->var.yres_virtual = fbi->var.yres * 2;
1482
1483        mx3fb->fbi = fbi;
1484
1485        /* set Display Interface clock period */
1486        mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
1487        /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
1488
1489        sdc_set_brightness(mx3fb, 255);
1490        sdc_set_global_alpha(mx3fb, true, 0xFF);
1491        sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
1492
1493        mx3fbi                  = fbi->par;
1494        mx3fbi->idmac_channel   = ichan;
1495        mx3fbi->ipu_ch          = ichan->dma_chan.chan_id;
1496        mx3fbi->mx3fb           = mx3fb;
1497        mx3fbi->blank           = FB_BLANK_NORMAL;
1498
1499        mx3fb->disp_data_fmt    = mx3fb_pdata->disp_data_fmt;
1500
1501        init_completion(&mx3fbi->flip_cmpl);
1502        disable_irq(ichan->eof_irq);
1503        dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
1504        ret = __set_par(fbi, false);
1505        if (ret < 0)
1506                goto esetpar;
1507
1508        __blank(FB_BLANK_UNBLANK, fbi);
1509
1510        dev_info(dev, "registered, using mode %s\n", fb_mode);
1511
1512        ret = register_framebuffer(fbi);
1513        if (ret < 0)
1514                goto erfb;
1515
1516        return 0;
1517
1518erfb:
1519esetpar:
1520emode:
1521        fb_dealloc_cmap(&fbi->cmap);
1522        framebuffer_release(fbi);
1523
1524        return ret;
1525}
1526
1527static bool chan_filter(struct dma_chan *chan, void *arg)
1528{
1529        struct dma_chan_request *rq = arg;
1530        struct device *dev;
1531        struct mx3fb_platform_data *mx3fb_pdata;
1532
1533        if (!imx_dma_is_ipu(chan))
1534                return false;
1535
1536        if (!rq)
1537                return false;
1538
1539        dev = rq->mx3fb->dev;
1540        mx3fb_pdata = dev_get_platdata(dev);
1541
1542        return rq->id == chan->chan_id &&
1543                mx3fb_pdata->dma_dev == chan->device->dev;
1544}
1545
1546static void release_fbi(struct fb_info *fbi)
1547{
1548        mx3fb_unmap_video_memory(fbi);
1549
1550        fb_dealloc_cmap(&fbi->cmap);
1551
1552        unregister_framebuffer(fbi);
1553        framebuffer_release(fbi);
1554}
1555
1556static int mx3fb_probe(struct platform_device *pdev)
1557{
1558        struct device *dev = &pdev->dev;
1559        int ret;
1560        struct resource *sdc_reg;
1561        struct mx3fb_data *mx3fb;
1562        dma_cap_mask_t mask;
1563        struct dma_chan *chan;
1564        struct dma_chan_request rq;
1565
1566        /*
1567         * Display Interface (DI) and Synchronous Display Controller (SDC)
1568         * registers
1569         */
1570        sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1571        if (!sdc_reg)
1572                return -EINVAL;
1573
1574        mx3fb = devm_kzalloc(&pdev->dev, sizeof(*mx3fb), GFP_KERNEL);
1575        if (!mx3fb)
1576                return -ENOMEM;
1577
1578        spin_lock_init(&mx3fb->lock);
1579
1580        mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1581        if (!mx3fb->reg_base) {
1582                ret = -ENOMEM;
1583                goto eremap;
1584        }
1585
1586        pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base);
1587
1588        /* IDMAC interface */
1589        dmaengine_get();
1590
1591        mx3fb->dev = dev;
1592        platform_set_drvdata(pdev, mx3fb);
1593
1594        rq.mx3fb = mx3fb;
1595
1596        dma_cap_zero(mask);
1597        dma_cap_set(DMA_SLAVE, mask);
1598        dma_cap_set(DMA_PRIVATE, mask);
1599        rq.id = IDMAC_SDC_0;
1600        chan = dma_request_channel(mask, chan_filter, &rq);
1601        if (!chan) {
1602                ret = -EBUSY;
1603                goto ersdc0;
1604        }
1605
1606        mx3fb->backlight_level = 255;
1607
1608        ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
1609        if (ret < 0)
1610                goto eisdc0;
1611
1612        mx3fb_init_backlight(mx3fb);
1613
1614        return 0;
1615
1616eisdc0:
1617        dma_release_channel(chan);
1618ersdc0:
1619        dmaengine_put();
1620        iounmap(mx3fb->reg_base);
1621eremap:
1622        dev_err(dev, "mx3fb: failed to register fb\n");
1623        return ret;
1624}
1625
1626static int mx3fb_remove(struct platform_device *dev)
1627{
1628        struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
1629        struct fb_info *fbi = mx3fb->fbi;
1630        struct mx3fb_info *mx3_fbi = fbi->par;
1631        struct dma_chan *chan;
1632
1633        chan = &mx3_fbi->idmac_channel->dma_chan;
1634        release_fbi(fbi);
1635
1636        mx3fb_exit_backlight(mx3fb);
1637
1638        dma_release_channel(chan);
1639        dmaengine_put();
1640
1641        iounmap(mx3fb->reg_base);
1642        return 0;
1643}
1644
1645static struct platform_driver mx3fb_driver = {
1646        .driver = {
1647                .name = MX3FB_NAME,
1648        },
1649        .probe = mx3fb_probe,
1650        .remove = mx3fb_remove,
1651        .suspend = mx3fb_suspend,
1652        .resume = mx3fb_resume,
1653};
1654
1655/*
1656 * Parse user specified options (`video=mx3fb:')
1657 * example:
1658 *      video=mx3fb:bpp=16
1659 */
1660static int __init mx3fb_setup(void)
1661{
1662#ifndef MODULE
1663        char *opt, *options = NULL;
1664
1665        if (fb_get_options("mx3fb", &options))
1666                return -ENODEV;
1667
1668        if (!options || !*options)
1669                return 0;
1670
1671        while ((opt = strsep(&options, ",")) != NULL) {
1672                if (!*opt)
1673                        continue;
1674                if (!strncmp(opt, "bpp=", 4))
1675                        default_bpp = simple_strtoul(opt + 4, NULL, 0);
1676                else
1677                        fb_mode = opt;
1678        }
1679#endif
1680
1681        return 0;
1682}
1683
1684static int __init mx3fb_init(void)
1685{
1686        int ret = mx3fb_setup();
1687
1688        if (ret < 0)
1689                return ret;
1690
1691        ret = platform_driver_register(&mx3fb_driver);
1692        return ret;
1693}
1694
1695static void __exit mx3fb_exit(void)
1696{
1697        platform_driver_unregister(&mx3fb_driver);
1698}
1699
1700module_init(mx3fb_init);
1701module_exit(mx3fb_exit);
1702
1703MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1704MODULE_DESCRIPTION("MX3 framebuffer driver");
1705MODULE_ALIAS("platform:" MX3FB_NAME);
1706MODULE_LICENSE("GPL v2");
1707