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49#include <linux/kernel.h>
50#include <linux/pci.h>
51#include <linux/pci_ids.h>
52#include "riva_hw.h"
53#include "riva_tbl.h"
54#include "nv_type.h"
55
56
57
58
59
60static int nv3Busy
61(
62 RIVA_HW_INST *chip
63)
64{
65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01);
67}
68static int nv4Busy
69(
70 RIVA_HW_INST *chip
71)
72{
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
75}
76static int nv10Busy
77(
78 RIVA_HW_INST *chip
79)
80{
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
83}
84
85static void vgaLockUnlock
86(
87 RIVA_HW_INST *chip,
88 int Lock
89)
90{
91 U008 cr11;
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11);
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5);
94 if(Lock) cr11 |= 0x80;
95 else cr11 &= ~0x80;
96 VGA_WR08(chip->PCIO, 0x3D5, cr11);
97}
98static void nv3LockUnlock
99(
100 RIVA_HW_INST *chip,
101 int Lock
102)
103{
104 VGA_WR08(chip->PVIO, 0x3C4, 0x06);
105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
106 vgaLockUnlock(chip, Lock);
107}
108static void nv4LockUnlock
109(
110 RIVA_HW_INST *chip,
111 int Lock
112)
113{
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
116 vgaLockUnlock(chip, Lock);
117}
118
119static int ShowHideCursor
120(
121 RIVA_HW_INST *chip,
122 int ShowHide
123)
124{
125 int cursor;
126 cursor = chip->CurrentState->cursor1;
127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
128 (ShowHide & 0x01);
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31);
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
131 return (cursor & 0x01);
132}
133
134
135
136
137
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139
140
141
142#define DEFAULT_GR_LWM 100
143#define DEFAULT_VID_LWM 100
144#define DEFAULT_GR_BURST_SIZE 256
145#define DEFAULT_VID_BURST_SIZE 128
146#define VIDEO 0
147#define GRAPHICS 1
148#define MPORT 2
149#define ENGINE 3
150#define GFIFO_SIZE 320
151#define GFIFO_SIZE_128 256
152#define MFIFO_SIZE 120
153#define VFIFO_SIZE 256
154
155typedef struct {
156 int gdrain_rate;
157 int vdrain_rate;
158 int mdrain_rate;
159 int gburst_size;
160 int vburst_size;
161 char vid_en;
162 char gr_en;
163 int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm;
164 int by_gfacc;
165 char vid_only_once;
166 char gr_only_once;
167 char first_vacc;
168 char first_gacc;
169 char first_macc;
170 int vocc;
171 int gocc;
172 int mocc;
173 char cur;
174 char engine_en;
175 char converged;
176 int priority;
177} nv3_arb_info;
178typedef struct {
179 int graphics_lwm;
180 int video_lwm;
181 int graphics_burst_size;
182 int video_burst_size;
183 int graphics_hi_priority;
184 int media_hi_priority;
185 int rtl_values;
186 int valid;
187} nv3_fifo_info;
188typedef struct {
189 char pix_bpp;
190 char enable_video;
191 char gr_during_vid;
192 char enable_mp;
193 int memory_width;
194 int video_scale;
195 int pclk_khz;
196 int mclk_khz;
197 int mem_page_miss;
198 int mem_latency;
199 char mem_aligned;
200} nv3_sim_state;
201typedef struct {
202 int graphics_lwm;
203 int video_lwm;
204 int graphics_burst_size;
205 int video_burst_size;
206 int valid;
207} nv4_fifo_info;
208typedef struct {
209 int pclk_khz;
210 int mclk_khz;
211 int nvclk_khz;
212 char mem_page_miss;
213 char mem_latency;
214 int memory_width;
215 char enable_video;
216 char gr_during_vid;
217 char pix_bpp;
218 char mem_aligned;
219 char enable_mp;
220} nv4_sim_state;
221typedef struct {
222 int graphics_lwm;
223 int video_lwm;
224 int graphics_burst_size;
225 int video_burst_size;
226 int valid;
227} nv10_fifo_info;
228typedef struct {
229 int pclk_khz;
230 int mclk_khz;
231 int nvclk_khz;
232 char mem_page_miss;
233 char mem_latency;
234 u32 memory_type;
235 int memory_width;
236 char enable_video;
237 char gr_during_vid;
238 char pix_bpp;
239 char mem_aligned;
240 char enable_mp;
241} nv10_sim_state;
242static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
243{
244 int iter = 0;
245 int tmp;
246 int vfsize, mfsize, gfsize;
247 int mburst_size = 32;
248 int mmisses, gmisses, vmisses;
249 int misses;
250 int vlwm, glwm, mlwm;
251 int last, next, cur;
252 int max_gfsize ;
253 long ns;
254
255 vlwm = 0;
256 glwm = 0;
257 mlwm = 0;
258 vfsize = 0;
259 gfsize = 0;
260 cur = ainfo->cur;
261 mmisses = 2;
262 gmisses = 2;
263 vmisses = 2;
264 if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128;
265 else max_gfsize = GFIFO_SIZE;
266 max_gfsize = GFIFO_SIZE;
267 while (1)
268 {
269 if (ainfo->vid_en)
270 {
271 if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc;
272 if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ;
273 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
274 vfsize = ns * ainfo->vdrain_rate / 1000000;
275 vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize;
276 }
277 if (state->enable_mp)
278 {
279 if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc;
280 }
281 if (ainfo->gr_en)
282 {
283 if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ;
284 if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc;
285 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
286 gfsize = (ns * (long) ainfo->gdrain_rate)/1000000;
287 gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize;
288 }
289 mfsize = 0;
290 if (!state->gr_during_vid && ainfo->vid_en)
291 if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once)
292 next = VIDEO;
293 else if (ainfo->mocc < 0)
294 next = MPORT;
295 else if (ainfo->gocc< ainfo->by_gfacc)
296 next = GRAPHICS;
297 else return (0);
298 else switch (ainfo->priority)
299 {
300 case VIDEO:
301 if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
302 next = VIDEO;
303 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
304 next = GRAPHICS;
305 else if (ainfo->mocc<0)
306 next = MPORT;
307 else return (0);
308 break;
309 case GRAPHICS:
310 if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
311 next = GRAPHICS;
312 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
313 next = VIDEO;
314 else if (ainfo->mocc<0)
315 next = MPORT;
316 else return (0);
317 break;
318 default:
319 if (ainfo->mocc<0)
320 next = MPORT;
321 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
322 next = GRAPHICS;
323 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
324 next = VIDEO;
325 else return (0);
326 break;
327 }
328 last = cur;
329 cur = next;
330 iter++;
331 switch (cur)
332 {
333 case VIDEO:
334 if (last==cur) misses = 0;
335 else if (ainfo->first_vacc) misses = vmisses;
336 else misses = 1;
337 ainfo->first_vacc = 0;
338 if (last!=cur)
339 {
340 ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
341 vlwm = ns * ainfo->vdrain_rate/ 1000000;
342 vlwm = ainfo->vocc - vlwm;
343 }
344 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
345 ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000;
346 ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000;
347 ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000;
348 break;
349 case GRAPHICS:
350 if (last==cur) misses = 0;
351 else if (ainfo->first_gacc) misses = gmisses;
352 else misses = 1;
353 ainfo->first_gacc = 0;
354 if (last!=cur)
355 {
356 ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;
357 glwm = ns * ainfo->gdrain_rate/1000000;
358 glwm = ainfo->gocc - glwm;
359 }
360 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
361 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
362 ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000;
363 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000;
364 break;
365 default:
366 if (last==cur) misses = 0;
367 else if (ainfo->first_macc) misses = mmisses;
368 else misses = 1;
369 ainfo->first_macc = 0;
370 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
371 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
372 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000;
373 ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000;
374 break;
375 }
376 if (iter>100)
377 {
378 ainfo->converged = 0;
379 return (1);
380 }
381 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
382 tmp = ns * ainfo->gdrain_rate/1000000;
383 if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize)
384 {
385 ainfo->converged = 0;
386 return (1);
387 }
388 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
389 tmp = ns * ainfo->vdrain_rate/1000000;
390 if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE)
391 {
392 ainfo->converged = 0;
393 return (1);
394 }
395 if (abs(ainfo->gocc) > max_gfsize)
396 {
397 ainfo->converged = 0;
398 return (1);
399 }
400 if (abs(ainfo->vocc) > VFIFO_SIZE)
401 {
402 ainfo->converged = 0;
403 return (1);
404 }
405 if (abs(ainfo->mocc) > MFIFO_SIZE)
406 {
407 ainfo->converged = 0;
408 return (1);
409 }
410 if (abs(vfsize) > VFIFO_SIZE)
411 {
412 ainfo->converged = 0;
413 return (1);
414 }
415 if (abs(gfsize) > max_gfsize)
416 {
417 ainfo->converged = 0;
418 return (1);
419 }
420 if (abs(mfsize) > MFIFO_SIZE)
421 {
422 ainfo->converged = 0;
423 return (1);
424 }
425 }
426}
427static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
428{
429 long ens, vns, mns, gns;
430 int mmisses, gmisses, vmisses, eburst_size, mburst_size;
431 int refresh_cycle;
432
433 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;
434 mmisses = 2;
435 if (state->mem_aligned) gmisses = 2;
436 else gmisses = 3;
437 vmisses = 2;
438 eburst_size = state->memory_width * 1;
439 mburst_size = 32;
440 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
441 ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000;
442 ainfo->wcmocc = 0;
443 ainfo->wcgocc = 0;
444 ainfo->wcvocc = 0;
445 ainfo->wcvlwm = 0;
446 ainfo->wcglwm = 0;
447 ainfo->engine_en = 1;
448 ainfo->converged = 1;
449 if (ainfo->engine_en)
450 {
451 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
452 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;
453 ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0;
454 ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0;
455 ainfo->cur = ENGINE;
456 ainfo->first_vacc = 1;
457 ainfo->first_gacc = 1;
458 ainfo->first_macc = 1;
459 nv3_iterate(res_info, state,ainfo);
460 }
461 if (state->enable_mp)
462 {
463 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
464 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;
465 ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000;
466 ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000;
467 ainfo->cur = MPORT;
468 ainfo->first_vacc = 1;
469 ainfo->first_gacc = 1;
470 ainfo->first_macc = 0;
471 nv3_iterate(res_info, state,ainfo);
472 }
473 if (ainfo->gr_en)
474 {
475 ainfo->first_vacc = 1;
476 ainfo->first_gacc = 0;
477 ainfo->first_macc = 1;
478 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
479 ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000;
480 ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0;
481 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0;
482 ainfo->cur = GRAPHICS;
483 nv3_iterate(res_info, state,ainfo);
484 }
485 if (ainfo->vid_en)
486 {
487 ainfo->first_vacc = 0;
488 ainfo->first_gacc = 1;
489 ainfo->first_macc = 1;
490 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
491 ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000;
492 ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0;
493 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;
494 ainfo->cur = VIDEO;
495 nv3_iterate(res_info, state, ainfo);
496 }
497 if (ainfo->converged)
498 {
499 res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16;
500 res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32;
501 res_info->graphics_burst_size = ainfo->gburst_size;
502 res_info->video_burst_size = ainfo->vburst_size;
503 res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS);
504 res_info->media_hi_priority = (ainfo->priority == MPORT);
505 if (res_info->video_lwm > 160)
506 {
507 res_info->graphics_lwm = 256;
508 res_info->video_lwm = 128;
509 res_info->graphics_burst_size = 64;
510 res_info->video_burst_size = 64;
511 res_info->graphics_hi_priority = 0;
512 res_info->media_hi_priority = 0;
513 ainfo->converged = 0;
514 return (0);
515 }
516 if (res_info->video_lwm > 128)
517 {
518 res_info->video_lwm = 128;
519 }
520 return (1);
521 }
522 else
523 {
524 res_info->graphics_lwm = 256;
525 res_info->video_lwm = 128;
526 res_info->graphics_burst_size = 64;
527 res_info->video_burst_size = 64;
528 res_info->graphics_hi_priority = 0;
529 res_info->media_hi_priority = 0;
530 return (0);
531 }
532}
533static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
534{
535 int done, g,v, p;
536
537 done = 0;
538 for (p=0; p < 2; p++)
539 {
540 for (g=128 ; g > 32; g= g>> 1)
541 {
542 for (v=128; v >=32; v = v>> 1)
543 {
544 ainfo->priority = p;
545 ainfo->gburst_size = g;
546 ainfo->vburst_size = v;
547 done = nv3_arb(res_info, state,ainfo);
548 if (done && (g==128))
549 if ((res_info->graphics_lwm + g) > 256)
550 done = 0;
551 if (done)
552 goto Done;
553 }
554 }
555 }
556
557 Done:
558 return done;
559}
560static void nv3CalcArbitration
561(
562 nv3_fifo_info * res_info,
563 nv3_sim_state * state
564)
565{
566 nv3_fifo_info save_info;
567 nv3_arb_info ainfo;
568 char res_gr, res_vid;
569
570 ainfo.gr_en = 1;
571 ainfo.vid_en = state->enable_video;
572 ainfo.vid_only_once = 0;
573 ainfo.gr_only_once = 0;
574 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
575 ainfo.vdrain_rate = (int) state->pclk_khz * 2;
576 if (state->video_scale != 0)
577 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;
578 ainfo.mdrain_rate = 33000;
579 res_info->rtl_values = 0;
580 if (!state->gr_during_vid && state->enable_video)
581 {
582 ainfo.gr_only_once = 1;
583 ainfo.gr_en = 1;
584 ainfo.gdrain_rate = 0;
585 res_vid = nv3_get_param(res_info, state, &ainfo);
586 res_vid = ainfo.converged;
587 save_info.video_lwm = res_info->video_lwm;
588 save_info.video_burst_size = res_info->video_burst_size;
589 ainfo.vid_en = 1;
590 ainfo.vid_only_once = 1;
591 ainfo.gr_en = 1;
592 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
593 ainfo.vdrain_rate = 0;
594 res_gr = nv3_get_param(res_info, state, &ainfo);
595 res_gr = ainfo.converged;
596 res_info->video_lwm = save_info.video_lwm;
597 res_info->video_burst_size = save_info.video_burst_size;
598 res_info->valid = res_gr & res_vid;
599 }
600 else
601 {
602 if (!ainfo.gr_en) ainfo.gdrain_rate = 0;
603 if (!ainfo.vid_en) ainfo.vdrain_rate = 0;
604 res_gr = nv3_get_param(res_info, state, &ainfo);
605 res_info->valid = ainfo.converged;
606 }
607}
608static void nv3UpdateArbitrationSettings
609(
610 unsigned VClk,
611 unsigned pixelDepth,
612 unsigned *burst,
613 unsigned *lwm,
614 RIVA_HW_INST *chip
615)
616{
617 nv3_fifo_info fifo_data;
618 nv3_sim_state sim_data;
619 unsigned int M, N, P, pll, MClk;
620
621 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
622 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
623 MClk = (N * chip->CrystalFreqKHz / M) >> P;
624 sim_data.pix_bpp = (char)pixelDepth;
625 sim_data.enable_video = 0;
626 sim_data.enable_mp = 0;
627 sim_data.video_scale = 1;
628 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
629 128 : 64;
630 sim_data.memory_width = 128;
631
632 sim_data.mem_latency = 9;
633 sim_data.mem_aligned = 1;
634 sim_data.mem_page_miss = 11;
635 sim_data.gr_during_vid = 0;
636 sim_data.pclk_khz = VClk;
637 sim_data.mclk_khz = MClk;
638 nv3CalcArbitration(&fifo_data, &sim_data);
639 if (fifo_data.valid)
640 {
641 int b = fifo_data.graphics_burst_size >> 4;
642 *burst = 0;
643 while (b >>= 1)
644 (*burst)++;
645 *lwm = fifo_data.graphics_lwm >> 3;
646 }
647 else
648 {
649 *lwm = 0x24;
650 *burst = 0x2;
651 }
652}
653static void nv4CalcArbitration
654(
655 nv4_fifo_info *fifo,
656 nv4_sim_state *arb
657)
658{
659 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
660 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
661 int found, mclk_extra, mclk_loop, cbs, m1, p1;
662 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
663 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
664 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
665 int craw, vraw;
666
667 fifo->valid = 1;
668 pclk_freq = arb->pclk_khz;
669 mclk_freq = arb->mclk_khz;
670 nvclk_freq = arb->nvclk_khz;
671 pagemiss = arb->mem_page_miss;
672 cas = arb->mem_latency;
673 width = arb->memory_width >> 6;
674 video_enable = arb->enable_video;
675 color_key_enable = arb->gr_during_vid;
676 bpp = arb->pix_bpp;
677 align = arb->mem_aligned;
678 mp_enable = arb->enable_mp;
679 clwm = 0;
680 vlwm = 0;
681 cbs = 128;
682 pclks = 2;
683 nvclks = 2;
684 nvclks += 2;
685 nvclks += 1;
686 mclks = 5;
687 mclks += 3;
688 mclks += 1;
689 mclks += cas;
690 mclks += 1;
691 mclks += 1;
692 mclks += 1;
693 mclks += 1;
694 mclk_extra = 3;
695 nvclks += 2;
696 nvclks += 1;
697 nvclks += 1;
698 nvclks += 1;
699 if (mp_enable)
700 mclks+=4;
701 nvclks += 0;
702 pclks += 0;
703 found = 0;
704 vbs = 0;
705 while (found != 1)
706 {
707 fifo->valid = 1;
708 found = 1;
709 mclk_loop = mclks+mclk_extra;
710 us_m = mclk_loop *1000*1000 / mclk_freq;
711 us_n = nvclks*1000*1000 / nvclk_freq;
712 us_p = nvclks*1000*1000 / pclk_freq;
713 if (video_enable)
714 {
715 video_drain_rate = pclk_freq * 2;
716 crtc_drain_rate = pclk_freq * bpp/8;
717 vpagemiss = 2;
718 vpagemiss += 1;
719 crtpagemiss = 2;
720 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
721 if (nvclk_freq * 2 > mclk_freq * width)
722 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
723 else
724 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
725 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
726 vlwm = us_video * video_drain_rate/(1000*1000);
727 vlwm++;
728 vbs = 128;
729 if (vlwm > 128) vbs = 64;
730 if (vlwm > (256-64)) vbs = 32;
731 if (nvclk_freq * 2 > mclk_freq * width)
732 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
733 else
734 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
735 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
736 us_crt =
737 us_video
738 +video_fill_us
739 +cpm_us
740 +us_m + us_n +us_p
741 ;
742 clwm = us_crt * crtc_drain_rate/(1000*1000);
743 clwm++;
744 }
745 else
746 {
747 crtc_drain_rate = pclk_freq * bpp/8;
748 crtpagemiss = 2;
749 crtpagemiss += 1;
750 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
751 us_crt = cpm_us + us_m + us_n + us_p ;
752 clwm = us_crt * crtc_drain_rate/(1000*1000);
753 clwm++;
754 }
755 m1 = clwm + cbs - 512;
756 p1 = m1 * pclk_freq / mclk_freq;
757 p1 = p1 * bpp / 8;
758 if ((p1 < m1) && (m1 > 0))
759 {
760 fifo->valid = 0;
761 found = 0;
762 if (mclk_extra ==0) found = 1;
763 mclk_extra--;
764 }
765 else if (video_enable)
766 {
767 if ((clwm > 511) || (vlwm > 255))
768 {
769 fifo->valid = 0;
770 found = 0;
771 if (mclk_extra ==0) found = 1;
772 mclk_extra--;
773 }
774 }
775 else
776 {
777 if (clwm > 519)
778 {
779 fifo->valid = 0;
780 found = 0;
781 if (mclk_extra ==0) found = 1;
782 mclk_extra--;
783 }
784 }
785 craw = clwm;
786 vraw = vlwm;
787 if (clwm < 384) clwm = 384;
788 if (vlwm < 128) vlwm = 128;
789 data = (int)(clwm);
790 fifo->graphics_lwm = data;
791 fifo->graphics_burst_size = 128;
792 data = (int)((vlwm+15));
793 fifo->video_lwm = data;
794 fifo->video_burst_size = vbs;
795 }
796}
797static void nv4UpdateArbitrationSettings
798(
799 unsigned VClk,
800 unsigned pixelDepth,
801 unsigned *burst,
802 unsigned *lwm,
803 RIVA_HW_INST *chip
804)
805{
806 nv4_fifo_info fifo_data;
807 nv4_sim_state sim_data;
808 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
809
810 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
811 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
812 MClk = (N * chip->CrystalFreqKHz / M) >> P;
813 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
814 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
815 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
816 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
817 sim_data.pix_bpp = (char)pixelDepth;
818 sim_data.enable_video = 0;
819 sim_data.enable_mp = 0;
820 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
821 128 : 64;
822 sim_data.mem_latency = (char)cfg1 & 0x0F;
823 sim_data.mem_aligned = 1;
824 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
825 sim_data.gr_during_vid = 0;
826 sim_data.pclk_khz = VClk;
827 sim_data.mclk_khz = MClk;
828 sim_data.nvclk_khz = NVClk;
829 nv4CalcArbitration(&fifo_data, &sim_data);
830 if (fifo_data.valid)
831 {
832 int b = fifo_data.graphics_burst_size >> 4;
833 *burst = 0;
834 while (b >>= 1)
835 (*burst)++;
836 *lwm = fifo_data.graphics_lwm >> 3;
837 }
838}
839static void nv10CalcArbitration
840(
841 nv10_fifo_info *fifo,
842 nv10_sim_state *arb
843)
844{
845 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
846 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
847 int nvclk_fill, us_extra;
848 int found, mclk_extra, mclk_loop, cbs, m1;
849 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
850 int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate;
851 int vus_m, vus_n, vus_p;
852 int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm;
853 int clwm_rnd_down;
854 int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2;
855 int pclks_2_top_fifo, min_mclk_extra;
856 int us_min_mclk_extra;
857
858 fifo->valid = 1;
859 pclk_freq = arb->pclk_khz;
860 mclk_freq = arb->mclk_khz;
861 nvclk_freq = arb->nvclk_khz;
862 pagemiss = arb->mem_page_miss;
863 cas = arb->mem_latency;
864 width = arb->memory_width/64;
865 video_enable = arb->enable_video;
866 color_key_enable = arb->gr_during_vid;
867 bpp = arb->pix_bpp;
868 align = arb->mem_aligned;
869 mp_enable = arb->enable_mp;
870 clwm = 0;
871 vlwm = 1024;
872
873 cbs = 512;
874 vbs = 512;
875
876 pclks = 4;
877
878 nvclks = 3;
879 nvclks += 2;
880
881 mclks = 1;
882
883 mclks += 1;
884 mclks += 5;
885
886 mclks += 2;
887 mclks += 2;
888 mclks += 7;
889
890
891 if (arb->memory_type == 0)
892 if (arb->memory_width == 64)
893 mclks += 4;
894 else
895 mclks += 2;
896 else
897 if (arb->memory_width == 64)
898 mclks += 2;
899 else
900 mclks += 1;
901
902 if ((!video_enable) && (arb->memory_width == 128))
903 {
904 mclk_extra = (bpp == 32) ? 31 : 42;
905 min_mclk_extra = 17;
906 }
907 else
908 {
909 mclk_extra = (bpp == 32) ? 8 : 4;
910
911 min_mclk_extra = 18;
912 }
913
914 nvclks += 1;
915 nvclks += 1;
916 nvclks += 1;
917 nvclks += 1;
918
919 if(mp_enable)
920 mclks+=4;
921
922
923 nvclks += 0;
924 pclks += 0;
925 found = 0;
926 while(found != 1) {
927 fifo->valid = 1;
928 found = 1;
929 mclk_loop = mclks+mclk_extra;
930 us_m = mclk_loop *1000*1000 / mclk_freq;
931 us_m_min = mclks * 1000*1000 / mclk_freq;
932 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
933 us_n = nvclks*1000*1000 / nvclk_freq;
934 us_p = pclks*1000*1000 / pclk_freq;
935 us_pipe = us_m + us_n + us_p;
936 us_pipe_min = us_m_min + us_n + us_p;
937 us_extra = 0;
938
939 vus_m = mclk_loop *1000*1000 / mclk_freq;
940 vus_n = (4)*1000*1000 / nvclk_freq;
941 vus_p = 0*1000*1000 / pclk_freq;
942 vus_pipe = vus_m + vus_n + vus_p;
943
944 if(video_enable) {
945 video_drain_rate = pclk_freq * 4;
946 crtc_drain_rate = pclk_freq * bpp/8;
947
948 vpagemiss = 1;
949 vpagemiss += 1;
950
951 crtpagemiss = 2;
952 if(mp_enable)
953 crtpagemiss += 1;
954
955 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
956
957 us_video = vpm_us + vus_m;
958
959 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
960 us_crt =
961 us_video
962 +cpm_us
963 +us_m + us_n +us_p
964 ;
965
966 clwm = us_crt * crtc_drain_rate/(1000*1000);
967 clwm++;
968 } else {
969 crtc_drain_rate = pclk_freq * bpp/8;
970
971 crtpagemiss = 1;
972 crtpagemiss += 1;
973 if(mp_enable)
974 crtpagemiss += 1;
975 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
976 us_crt = cpm_us + us_m + us_n + us_p ;
977 clwm = us_crt * crtc_drain_rate/(1000*1000);
978 clwm++;
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996 if(width == 1){
997 nvclk_fill = nvclk_freq * 8;
998 if(crtc_drain_rate * 100 >= nvclk_fill * 102)
999 clwm = 0xfff;
1000
1001 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) {
1002 clwm = 1024;
1003 cbs = 512;
1004 us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ;
1005 }
1006 }
1007 }
1008
1009
1010
1011
1012
1013
1014
1015 clwm_rnd_down = ((int)clwm/8)*8;
1016 if (clwm_rnd_down < clwm)
1017 clwm += 8;
1018
1019 m1 = clwm + cbs - 1024;
1020 m2us = us_pipe_min + us_min_mclk_extra;
1021 pclks_2_top_fifo = (1024-clwm)/(8*width);
1022
1023
1024 p1clk = m2us * pclk_freq/(1000*1000);
1025 p2 = p1clk * bpp / 8;
1026
1027 if((p2 < m1) && (m1 > 0)) {
1028 fifo->valid = 0;
1029 found = 0;
1030 if(min_mclk_extra == 0) {
1031 if(cbs <= 32) {
1032 found = 1;
1033 } else {
1034 cbs = cbs/2;
1035 }
1036 } else {
1037 min_mclk_extra--;
1038 }
1039 } else {
1040 if (clwm > 1023){
1041 fifo->valid = 0;
1042 found = 0;
1043 if(min_mclk_extra == 0)
1044 found = 1;
1045 else
1046 min_mclk_extra--;
1047 }
1048 }
1049 craw = clwm;
1050
1051 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
1052 data = (int)(clwm);
1053
1054 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs;
1055
1056
1057 fifo->video_lwm = 1024; fifo->video_burst_size = 512;
1058 }
1059}
1060static void nv10UpdateArbitrationSettings
1061(
1062 unsigned VClk,
1063 unsigned pixelDepth,
1064 unsigned *burst,
1065 unsigned *lwm,
1066 RIVA_HW_INST *chip
1067)
1068{
1069 nv10_fifo_info fifo_data;
1070 nv10_sim_state sim_data;
1071 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
1072
1073 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
1074 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1075 MClk = (N * chip->CrystalFreqKHz / M) >> P;
1076 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1077 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1078 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1079 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
1080 sim_data.pix_bpp = (char)pixelDepth;
1081 sim_data.enable_video = 0;
1082 sim_data.enable_mp = 0;
1083 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ?
1084 1 : 0;
1085 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1086 128 : 64;
1087 sim_data.mem_latency = (char)cfg1 & 0x0F;
1088 sim_data.mem_aligned = 1;
1089 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
1090 sim_data.gr_during_vid = 0;
1091 sim_data.pclk_khz = VClk;
1092 sim_data.mclk_khz = MClk;
1093 sim_data.nvclk_khz = NVClk;
1094 nv10CalcArbitration(&fifo_data, &sim_data);
1095 if (fifo_data.valid)
1096 {
1097 int b = fifo_data.graphics_burst_size >> 4;
1098 *burst = 0;
1099 while (b >>= 1)
1100 (*burst)++;
1101 *lwm = fifo_data.graphics_lwm >> 3;
1102 }
1103}
1104
1105static void nForceUpdateArbitrationSettings
1106(
1107 unsigned VClk,
1108 unsigned pixelDepth,
1109 unsigned *burst,
1110 unsigned *lwm,
1111 RIVA_HW_INST *chip
1112)
1113{
1114 nv10_fifo_info fifo_data;
1115 nv10_sim_state sim_data;
1116 unsigned int M, N, P, pll, MClk, NVClk;
1117 unsigned int uMClkPostDiv;
1118 struct pci_dev *dev;
1119
1120 dev = pci_get_bus_and_slot(0, 3);
1121 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
1122 pci_dev_put(dev);
1123 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
1124
1125 if(!uMClkPostDiv) uMClkPostDiv = 4;
1126 MClk = 400000 / uMClkPostDiv;
1127
1128 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1129 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1130 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1131 sim_data.pix_bpp = (char)pixelDepth;
1132 sim_data.enable_video = 0;
1133 sim_data.enable_mp = 0;
1134
1135 dev = pci_get_bus_and_slot(0, 1);
1136 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
1137 pci_dev_put(dev);
1138 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
1139
1140 sim_data.memory_width = 64;
1141 sim_data.mem_latency = 3;
1142 sim_data.mem_aligned = 1;
1143 sim_data.mem_page_miss = 10;
1144 sim_data.gr_during_vid = 0;
1145 sim_data.pclk_khz = VClk;
1146 sim_data.mclk_khz = MClk;
1147 sim_data.nvclk_khz = NVClk;
1148 nv10CalcArbitration(&fifo_data, &sim_data);
1149 if (fifo_data.valid)
1150 {
1151 int b = fifo_data.graphics_burst_size >> 4;
1152 *burst = 0;
1153 while (b >>= 1)
1154 (*burst)++;
1155 *lwm = fifo_data.graphics_lwm >> 3;
1156 }
1157}
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168static int CalcVClock
1169(
1170 int clockIn,
1171 int *clockOut,
1172 int *mOut,
1173 int *nOut,
1174 int *pOut,
1175 RIVA_HW_INST *chip
1176)
1177{
1178 unsigned lowM, highM, highP;
1179 unsigned DeltaNew, DeltaOld;
1180 unsigned VClk, Freq;
1181 unsigned M, N, P;
1182
1183 DeltaOld = 0xFFFFFFFF;
1184
1185 VClk = (unsigned)clockIn;
1186
1187 if (chip->CrystalFreqKHz == 13500)
1188 {
1189 lowM = 7;
1190 highM = 13 - (chip->Architecture == NV_ARCH_03);
1191 }
1192 else
1193 {
1194 lowM = 8;
1195 highM = 14 - (chip->Architecture == NV_ARCH_03);
1196 }
1197
1198 highP = 4 - (chip->Architecture == NV_ARCH_03);
1199 for (P = 0; P <= highP; P ++)
1200 {
1201 Freq = VClk << P;
1202 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
1203 {
1204 for (M = lowM; M <= highM; M++)
1205 {
1206 N = (VClk << P) * M / chip->CrystalFreqKHz;
1207 if(N <= 255) {
1208 Freq = (chip->CrystalFreqKHz * N / M) >> P;
1209 if (Freq > VClk)
1210 DeltaNew = Freq - VClk;
1211 else
1212 DeltaNew = VClk - Freq;
1213 if (DeltaNew < DeltaOld)
1214 {
1215 *mOut = M;
1216 *nOut = N;
1217 *pOut = P;
1218 *clockOut = Freq;
1219 DeltaOld = DeltaNew;
1220 }
1221 }
1222 }
1223 }
1224 }
1225
1226
1227 return (DeltaOld != 0xFFFFFFFF);
1228}
1229
1230
1231
1232
1233int CalcStateExt
1234(
1235 RIVA_HW_INST *chip,
1236 RIVA_HW_STATE *state,
1237 int bpp,
1238 int width,
1239 int hDisplaySize,
1240 int height,
1241 int dotClock
1242)
1243{
1244 int pixelDepth;
1245 int uninitialized_var(VClk),uninitialized_var(m),
1246 uninitialized_var(n), uninitialized_var(p);
1247
1248
1249
1250
1251 state->bpp = bpp;
1252 state->width = width;
1253 state->height = height;
1254
1255
1256
1257 pixelDepth = (bpp + 1)/8;
1258 if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip))
1259 return -EINVAL;
1260
1261 switch (chip->Architecture)
1262 {
1263 case NV_ARCH_03:
1264 nv3UpdateArbitrationSettings(VClk,
1265 pixelDepth * 8,
1266 &(state->arbitration0),
1267 &(state->arbitration1),
1268 chip);
1269 state->cursor0 = 0x00;
1270 state->cursor1 = 0x78;
1271 state->cursor2 = 0x00000000;
1272 state->pllsel = 0x10010100;
1273 state->config = ((width + 31)/32)
1274 | (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
1275 | 0x1000;
1276 state->general = 0x00100100;
1277 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
1278 break;
1279 case NV_ARCH_04:
1280 nv4UpdateArbitrationSettings(VClk,
1281 pixelDepth * 8,
1282 &(state->arbitration0),
1283 &(state->arbitration1),
1284 chip);
1285 state->cursor0 = 0x00;
1286 state->cursor1 = 0xFC;
1287 state->cursor2 = 0x00000000;
1288 state->pllsel = 0x10000700;
1289 state->config = 0x00001114;
1290 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1291 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1292 break;
1293 case NV_ARCH_10:
1294 case NV_ARCH_20:
1295 case NV_ARCH_30:
1296 if((chip->Chipset == NV_CHIP_IGEFORCE2) ||
1297 (chip->Chipset == NV_CHIP_0x01F0))
1298 {
1299 nForceUpdateArbitrationSettings(VClk,
1300 pixelDepth * 8,
1301 &(state->arbitration0),
1302 &(state->arbitration1),
1303 chip);
1304 } else {
1305 nv10UpdateArbitrationSettings(VClk,
1306 pixelDepth * 8,
1307 &(state->arbitration0),
1308 &(state->arbitration1),
1309 chip);
1310 }
1311 state->cursor0 = 0x80 | (chip->CursorStart >> 17);
1312 state->cursor1 = (chip->CursorStart >> 11) << 2;
1313 state->cursor2 = chip->CursorStart >> 24;
1314 state->pllsel = 0x10000700;
1315 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0);
1316 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1317 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1318 break;
1319 }
1320
1321
1322
1323 if((bpp != 8) && (chip->Architecture != NV_ARCH_03))
1324 state->general |= 0x00000030;
1325
1326 state->vpll = (p << 16) | (n << 8) | m;
1327 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
1328 state->pixel = pixelDepth > 2 ? 3 : pixelDepth;
1329 state->offset0 =
1330 state->offset1 =
1331 state->offset2 =
1332 state->offset3 = 0;
1333 state->pitch0 =
1334 state->pitch1 =
1335 state->pitch2 =
1336 state->pitch3 = pixelDepth * width;
1337
1338 return 0;
1339}
1340
1341
1342
1343#if 0
1344#define LOAD_FIXED_STATE(tbl,dev) \
1345 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1346 chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
1347#define LOAD_FIXED_STATE_8BPP(tbl,dev) \
1348 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1349 chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
1350#define LOAD_FIXED_STATE_15BPP(tbl,dev) \
1351 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1352 chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
1353#define LOAD_FIXED_STATE_16BPP(tbl,dev) \
1354 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1355 chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
1356#define LOAD_FIXED_STATE_32BPP(tbl,dev) \
1357 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1358 chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
1359#endif
1360
1361#define LOAD_FIXED_STATE(tbl,dev) \
1362 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1363 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1364#define LOAD_FIXED_STATE_8BPP(tbl,dev) \
1365 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1366 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1367#define LOAD_FIXED_STATE_15BPP(tbl,dev) \
1368 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1369 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1370#define LOAD_FIXED_STATE_16BPP(tbl,dev) \
1371 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1372 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1373#define LOAD_FIXED_STATE_32BPP(tbl,dev) \
1374 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1375 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])
1376
1377static void UpdateFifoState
1378(
1379 RIVA_HW_INST *chip
1380)
1381{
1382 int i;
1383
1384 switch (chip->Architecture)
1385 {
1386 case NV_ARCH_04:
1387 LOAD_FIXED_STATE(nv4,FIFO);
1388 chip->Tri03 = NULL;
1389 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1390 break;
1391 case NV_ARCH_10:
1392 case NV_ARCH_20:
1393 case NV_ARCH_30:
1394
1395
1396
1397 LOAD_FIXED_STATE(nv10tri05,PGRAPH);
1398 LOAD_FIXED_STATE(nv10,FIFO);
1399 chip->Tri03 = NULL;
1400 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1401 break;
1402 }
1403}
1404static void LoadStateExt
1405(
1406 RIVA_HW_INST *chip,
1407 RIVA_HW_STATE *state
1408)
1409{
1410 int i;
1411
1412
1413
1414
1415 LOAD_FIXED_STATE(Riva,PMC);
1416 LOAD_FIXED_STATE(Riva,PTIMER);
1417 switch (chip->Architecture)
1418 {
1419 case NV_ARCH_03:
1420
1421
1422
1423 NV_WR32(chip->PFB, 0x00000200, state->config);
1424 LOAD_FIXED_STATE(nv3,PFIFO);
1425 LOAD_FIXED_STATE(nv3,PRAMIN);
1426 LOAD_FIXED_STATE(nv3,PGRAPH);
1427 switch (state->bpp)
1428 {
1429 case 15:
1430 case 16:
1431 LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
1432 LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
1433 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1434 break;
1435 case 24:
1436 case 32:
1437 LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
1438 LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
1439 chip->Tri03 = NULL;
1440 break;
1441 case 8:
1442 default:
1443 LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
1444 LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
1445 chip->Tri03 = NULL;
1446 break;
1447 }
1448 for (i = 0x00000; i < 0x00800; i++)
1449 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03);
1450 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0);
1451 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1);
1452 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2);
1453 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3);
1454 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0);
1455 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1);
1456 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2);
1457 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3);
1458 break;
1459 case NV_ARCH_04:
1460
1461
1462
1463 NV_WR32(chip->PFB, 0x00000200, state->config);
1464 LOAD_FIXED_STATE(nv4,PFIFO);
1465 LOAD_FIXED_STATE(nv4,PRAMIN);
1466 LOAD_FIXED_STATE(nv4,PGRAPH);
1467 switch (state->bpp)
1468 {
1469 case 15:
1470 LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
1471 LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
1472 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1473 break;
1474 case 16:
1475 LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
1476 LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
1477 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1478 break;
1479 case 24:
1480 case 32:
1481 LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
1482 LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
1483 chip->Tri03 = NULL;
1484 break;
1485 case 8:
1486 default:
1487 LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
1488 LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
1489 chip->Tri03 = NULL;
1490 break;
1491 }
1492 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1493 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1494 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1495 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1496 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1497 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1498 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1499 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1500 break;
1501 case NV_ARCH_10:
1502 case NV_ARCH_20:
1503 case NV_ARCH_30:
1504 if(chip->twoHeads) {
1505 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1506 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
1507 chip->LockUnlock(chip, 0);
1508 }
1509
1510 LOAD_FIXED_STATE(nv10,PFIFO);
1511 LOAD_FIXED_STATE(nv10,PRAMIN);
1512 LOAD_FIXED_STATE(nv10,PGRAPH);
1513 switch (state->bpp)
1514 {
1515 case 15:
1516 LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);
1517 LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);
1518 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1519 break;
1520 case 16:
1521 LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);
1522 LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);
1523 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1524 break;
1525 case 24:
1526 case 32:
1527 LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);
1528 LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);
1529 chip->Tri03 = NULL;
1530 break;
1531 case 8:
1532 default:
1533 LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);
1534 LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);
1535 chip->Tri03 = NULL;
1536 break;
1537 }
1538
1539 if(chip->Architecture == NV_ARCH_10) {
1540 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1541 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1542 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1543 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1544 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1545 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1546 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1547 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1548 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3);
1549 } else {
1550 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0);
1551 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1);
1552 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2);
1553 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3);
1554 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0);
1555 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1);
1556 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2);
1557 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3);
1558 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3);
1559 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3);
1560 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200));
1561 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204));
1562 }
1563 if(chip->twoHeads) {
1564 NV_WR32(chip->PCRTC0, 0x00000860, state->head);
1565 NV_WR32(chip->PCRTC0, 0x00002860, state->head2);
1566 }
1567 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25));
1568
1569 NV_WR32(chip->PMC, 0x00008704, 1);
1570 NV_WR32(chip->PMC, 0x00008140, 0);
1571 NV_WR32(chip->PMC, 0x00008920, 0);
1572 NV_WR32(chip->PMC, 0x00008924, 0);
1573 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff);
1574 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff);
1575 NV_WR32(chip->PMC, 0x00001588, 0);
1576
1577 NV_WR32(chip->PFB, 0x00000240, 0);
1578 NV_WR32(chip->PFB, 0x00000250, 0);
1579 NV_WR32(chip->PFB, 0x00000260, 0);
1580 NV_WR32(chip->PFB, 0x00000270, 0);
1581 NV_WR32(chip->PFB, 0x00000280, 0);
1582 NV_WR32(chip->PFB, 0x00000290, 0);
1583 NV_WR32(chip->PFB, 0x000002A0, 0);
1584 NV_WR32(chip->PFB, 0x000002B0, 0);
1585
1586 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240));
1587 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244));
1588 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248));
1589 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C));
1590 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250));
1591 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254));
1592 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258));
1593 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C));
1594 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260));
1595 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264));
1596 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268));
1597 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C));
1598 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270));
1599 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274));
1600 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278));
1601 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C));
1602 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280));
1603 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284));
1604 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288));
1605 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C));
1606 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290));
1607 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294));
1608 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298));
1609 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C));
1610 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0));
1611 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4));
1612 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8));
1613 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC));
1614 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0));
1615 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4));
1616 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8));
1617 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC));
1618 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000);
1619 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000);
1620 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1621 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008);
1622 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200);
1623 for (i = 0; i < (3*16); i++)
1624 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1625 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1626 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1627 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800);
1628 for (i = 0; i < (16*16); i++)
1629 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1630 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000);
1631 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004);
1632 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400);
1633 for (i = 0; i < (59*4); i++)
1634 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1635 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800);
1636 for (i = 0; i < (47*4); i++)
1637 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1638 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00);
1639 for (i = 0; i < (3*4); i++)
1640 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1641 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000);
1642 for (i = 0; i < (19*4); i++)
1643 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1644 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400);
1645 for (i = 0; i < (12*4); i++)
1646 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1647 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800);
1648 for (i = 0; i < (12*4); i++)
1649 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1650 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400);
1651 for (i = 0; i < (8*4); i++)
1652 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1653 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000);
1654 for (i = 0; i < 16; i++)
1655 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1656 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1657 for (i = 0; i < 4; i++)
1658 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1659
1660 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig);
1661
1662 if(chip->flatPanel) {
1663 if((chip->Chipset & 0x0ff0) == 0x0110) {
1664 NV_WR32(chip->PRAMDAC, 0x0528, state->dither);
1665 } else
1666 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1667 NV_WR32(chip->PRAMDAC, 0x083C, state->dither);
1668 }
1669
1670 VGA_WR08(chip->PCIO, 0x03D4, 0x53);
1671 VGA_WR08(chip->PCIO, 0x03D5, 0);
1672 VGA_WR08(chip->PCIO, 0x03D4, 0x54);
1673 VGA_WR08(chip->PCIO, 0x03D5, 0);
1674 VGA_WR08(chip->PCIO, 0x03D4, 0x21);
1675 VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
1676 }
1677
1678 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1679 VGA_WR08(chip->PCIO, 0x03D5, state->extra);
1680 }
1681 LOAD_FIXED_STATE(Riva,FIFO);
1682 UpdateFifoState(chip);
1683
1684
1685
1686 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1687 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
1688 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1689 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
1690 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1691 VGA_WR08(chip->PCIO, 0x03D5, state->screen);
1692 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1693 VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
1694 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1695 VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
1696 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1697 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
1698 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1699 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
1700 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1701 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
1702 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1703 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
1704 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1705 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
1706 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1707 VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
1708
1709 if(!chip->flatPanel) {
1710 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll);
1711 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel);
1712 if(chip->twoHeads)
1713 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2);
1714 } else {
1715 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale);
1716 }
1717 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general);
1718
1719
1720
1721
1722 NV_WR32(chip->PCRTC, 0x00000140, 0);
1723 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit);
1724
1725
1726
1727 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01);
1728
1729
1730
1731 chip->CurrentState = state;
1732
1733
1734
1735 chip->FifoFreeCount = 0;
1736
1737 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0);
1738}
1739static void UnloadStateExt
1740(
1741 RIVA_HW_INST *chip,
1742 RIVA_HW_STATE *state
1743)
1744{
1745
1746
1747
1748 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1749 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
1750 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1751 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
1752 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1753 state->screen = VGA_RD08(chip->PCIO, 0x03D5);
1754 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1755 state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
1756 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1757 state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
1758 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1759 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
1760 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1761 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
1762 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1763 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
1764 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1765 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
1766 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1767 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
1768 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1769 state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
1770 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508);
1771 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520);
1772 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C);
1773 state->general = NV_RD32(chip->PRAMDAC, 0x00000600);
1774 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848);
1775 state->config = NV_RD32(chip->PFB, 0x00000200);
1776 switch (chip->Architecture)
1777 {
1778 case NV_ARCH_03:
1779 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630);
1780 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634);
1781 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638);
1782 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C);
1783 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650);
1784 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654);
1785 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658);
1786 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C);
1787 break;
1788 case NV_ARCH_04:
1789 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1790 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1791 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1792 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1793 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1794 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1795 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1796 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1797 break;
1798 case NV_ARCH_10:
1799 case NV_ARCH_20:
1800 case NV_ARCH_30:
1801 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1802 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1803 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1804 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1805 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1806 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1807 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1808 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1809 if(chip->twoHeads) {
1810 state->head = NV_RD32(chip->PCRTC0, 0x00000860);
1811 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860);
1812 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1813 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
1814 }
1815 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1816 state->extra = VGA_RD08(chip->PCIO, 0x03D5);
1817 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810);
1818
1819 if((chip->Chipset & 0x0ff0) == 0x0110) {
1820 state->dither = NV_RD32(chip->PRAMDAC, 0x0528);
1821 } else
1822 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1823 state->dither = NV_RD32(chip->PRAMDAC, 0x083C);
1824 }
1825 break;
1826 }
1827}
1828static void SetStartAddress
1829(
1830 RIVA_HW_INST *chip,
1831 unsigned start
1832)
1833{
1834 NV_WR32(chip->PCRTC, 0x800, start);
1835}
1836
1837static void SetStartAddress3
1838(
1839 RIVA_HW_INST *chip,
1840 unsigned start
1841)
1842{
1843 int offset = start >> 2;
1844 int pan = (start & 3) << 1;
1845 unsigned char tmp;
1846
1847
1848
1849
1850 chip->LockUnlock(chip, 0);
1851
1852
1853
1854 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
1855 offset >>= 8;
1856 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
1857 offset >>= 8;
1858 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1859 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
1860 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1861 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
1862
1863
1864
1865 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
1866 VGA_WR08(chip->PCIO, 0x3C0, 0x13);
1867 VGA_WR08(chip->PCIO, 0x3C0, pan);
1868}
1869static void nv3SetSurfaces2D
1870(
1871 RIVA_HW_INST *chip,
1872 unsigned surf0,
1873 unsigned surf1
1874)
1875{
1876 RivaSurface __iomem *Surface =
1877 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1878
1879 RIVA_FIFO_FREE(*chip,Tri03,5);
1880 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1881 NV_WR32(&Surface->Offset, 0, surf0);
1882 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1883 NV_WR32(&Surface->Offset, 0, surf1);
1884 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1885}
1886static void nv4SetSurfaces2D
1887(
1888 RIVA_HW_INST *chip,
1889 unsigned surf0,
1890 unsigned surf1
1891)
1892{
1893 RivaSurface __iomem *Surface =
1894 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1895
1896 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1897 NV_WR32(&Surface->Offset, 0, surf0);
1898 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1899 NV_WR32(&Surface->Offset, 0, surf1);
1900 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1901}
1902static void nv10SetSurfaces2D
1903(
1904 RIVA_HW_INST *chip,
1905 unsigned surf0,
1906 unsigned surf1
1907)
1908{
1909 RivaSurface __iomem *Surface =
1910 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1911
1912 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1913 NV_WR32(&Surface->Offset, 0, surf0);
1914 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1915 NV_WR32(&Surface->Offset, 0, surf1);
1916 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1917}
1918static void nv3SetSurfaces3D
1919(
1920 RIVA_HW_INST *chip,
1921 unsigned surf0,
1922 unsigned surf1
1923)
1924{
1925 RivaSurface __iomem *Surface =
1926 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1927
1928 RIVA_FIFO_FREE(*chip,Tri03,5);
1929 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1930 NV_WR32(&Surface->Offset, 0, surf0);
1931 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1932 NV_WR32(&Surface->Offset, 0, surf1);
1933 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1934}
1935static void nv4SetSurfaces3D
1936(
1937 RIVA_HW_INST *chip,
1938 unsigned surf0,
1939 unsigned surf1
1940)
1941{
1942 RivaSurface __iomem *Surface =
1943 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1944
1945 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1946 NV_WR32(&Surface->Offset, 0, surf0);
1947 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1948 NV_WR32(&Surface->Offset, 0, surf1);
1949 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1950}
1951static void nv10SetSurfaces3D
1952(
1953 RIVA_HW_INST *chip,
1954 unsigned surf0,
1955 unsigned surf1
1956)
1957{
1958 RivaSurface3D __iomem *Surfaces3D =
1959 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]);
1960
1961 RIVA_FIFO_FREE(*chip,Tri03,4);
1962 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007);
1963 NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0);
1964 NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1);
1965 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1966}
1967
1968
1969
1970
1971
1972
1973
1974static void nv3GetConfig
1975(
1976 RIVA_HW_INST *chip
1977)
1978{
1979
1980
1981
1982 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020)
1983 {
1984 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
1985 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02))
1986 {
1987
1988
1989
1990 chip->RamBandwidthKBytesPerSec = 800000;
1991 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03)
1992 {
1993 case 2:
1994 chip->RamAmountKBytes = 1024 * 4;
1995 break;
1996 case 1:
1997 chip->RamAmountKBytes = 1024 * 2;
1998 break;
1999 default:
2000 chip->RamAmountKBytes = 1024 * 8;
2001 break;
2002 }
2003 }
2004 else
2005 {
2006 chip->RamBandwidthKBytesPerSec = 1000000;
2007 chip->RamAmountKBytes = 1024 * 8;
2008 }
2009 }
2010 else
2011 {
2012
2013
2014
2015 chip->RamBandwidthKBytesPerSec = 1000000;
2016 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
2017 {
2018 case 0:
2019 chip->RamAmountKBytes = 1024 * 8;
2020 break;
2021 case 2:
2022 chip->RamAmountKBytes = 1024 * 4;
2023 break;
2024 default:
2025 chip->RamAmountKBytes = 1024 * 2;
2026 break;
2027 }
2028 }
2029 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
2030 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
2031 chip->VBlankBit = 0x00000100;
2032 chip->MaxVClockFreqKHz = 256000;
2033
2034
2035
2036 chip->Busy = nv3Busy;
2037 chip->ShowHideCursor = ShowHideCursor;
2038 chip->LoadStateExt = LoadStateExt;
2039 chip->UnloadStateExt = UnloadStateExt;
2040 chip->SetStartAddress = SetStartAddress3;
2041 chip->SetSurfaces2D = nv3SetSurfaces2D;
2042 chip->SetSurfaces3D = nv3SetSurfaces3D;
2043 chip->LockUnlock = nv3LockUnlock;
2044}
2045static void nv4GetConfig
2046(
2047 RIVA_HW_INST *chip
2048)
2049{
2050
2051
2052
2053 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100)
2054 {
2055 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2
2056 + 1024 * 2;
2057 }
2058 else
2059 {
2060 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
2061 {
2062 case 0:
2063 chip->RamAmountKBytes = 1024 * 32;
2064 break;
2065 case 1:
2066 chip->RamAmountKBytes = 1024 * 4;
2067 break;
2068 case 2:
2069 chip->RamAmountKBytes = 1024 * 8;
2070 break;
2071 case 3:
2072 default:
2073 chip->RamAmountKBytes = 1024 * 16;
2074 break;
2075 }
2076 }
2077 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2078 {
2079 case 3:
2080 chip->RamBandwidthKBytesPerSec = 800000;
2081 break;
2082 default:
2083 chip->RamBandwidthKBytesPerSec = 1000000;
2084 break;
2085 }
2086 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
2087 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
2088 chip->VBlankBit = 0x00000001;
2089 chip->MaxVClockFreqKHz = 350000;
2090
2091
2092
2093 chip->Busy = nv4Busy;
2094 chip->ShowHideCursor = ShowHideCursor;
2095 chip->LoadStateExt = LoadStateExt;
2096 chip->UnloadStateExt = UnloadStateExt;
2097 chip->SetStartAddress = SetStartAddress;
2098 chip->SetSurfaces2D = nv4SetSurfaces2D;
2099 chip->SetSurfaces3D = nv4SetSurfaces3D;
2100 chip->LockUnlock = nv4LockUnlock;
2101}
2102static void nv10GetConfig
2103(
2104 RIVA_HW_INST *chip,
2105 unsigned int chipset
2106)
2107{
2108 struct pci_dev* dev;
2109 u32 amt;
2110
2111#ifdef __BIG_ENDIAN
2112
2113 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001))
2114 NV_WR32(chip->PMC, 0x00000004, 0x01000001);
2115#endif
2116
2117
2118
2119
2120 if(chipset == NV_CHIP_IGEFORCE2) {
2121 dev = pci_get_bus_and_slot(0, 1);
2122 pci_read_config_dword(dev, 0x7C, &amt);
2123 pci_dev_put(dev);
2124 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
2125 } else if(chipset == NV_CHIP_0x01F0) {
2126 dev = pci_get_bus_and_slot(0, 1);
2127 pci_read_config_dword(dev, 0x84, &amt);
2128 pci_dev_put(dev);
2129 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
2130 } else {
2131 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)
2132 {
2133 case 0x02:
2134 chip->RamAmountKBytes = 1024 * 2;
2135 break;
2136 case 0x04:
2137 chip->RamAmountKBytes = 1024 * 4;
2138 break;
2139 case 0x08:
2140 chip->RamAmountKBytes = 1024 * 8;
2141 break;
2142 case 0x10:
2143 chip->RamAmountKBytes = 1024 * 16;
2144 break;
2145 case 0x20:
2146 chip->RamAmountKBytes = 1024 * 32;
2147 break;
2148 case 0x40:
2149 chip->RamAmountKBytes = 1024 * 64;
2150 break;
2151 case 0x80:
2152 chip->RamAmountKBytes = 1024 * 128;
2153 break;
2154 default:
2155 chip->RamAmountKBytes = 1024 * 16;
2156 break;
2157 }
2158 }
2159 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2160 {
2161 case 3:
2162 chip->RamBandwidthKBytesPerSec = 800000;
2163 break;
2164 default:
2165 chip->RamBandwidthKBytesPerSec = 1000000;
2166 break;
2167 }
2168 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ?
2169 14318 : 13500;
2170
2171 switch (chipset & 0x0ff0) {
2172 case 0x0170:
2173 case 0x0180:
2174 case 0x01F0:
2175 case 0x0250:
2176 case 0x0280:
2177 case 0x0300:
2178 case 0x0310:
2179 case 0x0320:
2180 case 0x0330:
2181 case 0x0340:
2182 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22))
2183 chip->CrystalFreqKHz = 27000;
2184 break;
2185 default:
2186 break;
2187 }
2188
2189 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
2190 chip->CURSOR = NULL;
2191 chip->VBlankBit = 0x00000001;
2192 chip->MaxVClockFreqKHz = 350000;
2193
2194
2195
2196 chip->Busy = nv10Busy;
2197 chip->ShowHideCursor = ShowHideCursor;
2198 chip->LoadStateExt = LoadStateExt;
2199 chip->UnloadStateExt = UnloadStateExt;
2200 chip->SetStartAddress = SetStartAddress;
2201 chip->SetSurfaces2D = nv10SetSurfaces2D;
2202 chip->SetSurfaces3D = nv10SetSurfaces3D;
2203 chip->LockUnlock = nv4LockUnlock;
2204
2205 switch(chipset & 0x0ff0) {
2206 case 0x0110:
2207 case 0x0170:
2208 case 0x0180:
2209 case 0x01F0:
2210 case 0x0250:
2211 case 0x0280:
2212 case 0x0300:
2213 case 0x0310:
2214 case 0x0320:
2215 case 0x0330:
2216 case 0x0340:
2217 chip->twoHeads = TRUE;
2218 break;
2219 default:
2220 chip->twoHeads = FALSE;
2221 break;
2222 }
2223}
2224int RivaGetConfig
2225(
2226 RIVA_HW_INST *chip,
2227 unsigned int chipset
2228)
2229{
2230
2231
2232
2233 chip->Version = RIVA_SW_VERSION;
2234
2235
2236
2237 switch (chip->Architecture)
2238 {
2239 case NV_ARCH_03:
2240 nv3GetConfig(chip);
2241 break;
2242 case NV_ARCH_04:
2243 nv4GetConfig(chip);
2244 break;
2245 case NV_ARCH_10:
2246 case NV_ARCH_20:
2247 case NV_ARCH_30:
2248 nv10GetConfig(chip, chipset);
2249 break;
2250 default:
2251 return (-1);
2252 }
2253 chip->Chipset = chipset;
2254
2255
2256
2257 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]);
2258 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]);
2259 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]);
2260 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]);
2261 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]);
2262 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]);
2263 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]);
2264 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
2265 return (0);
2266}
2267
2268