1#ifndef _LINUX_IRQ_H
2#define _LINUX_IRQ_H
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12#include <linux/smp.h>
13#include <linux/linkage.h>
14#include <linux/cache.h>
15#include <linux/spinlock.h>
16#include <linux/cpumask.h>
17#include <linux/gfp.h>
18#include <linux/irqhandler.h>
19#include <linux/irqreturn.h>
20#include <linux/irqnr.h>
21#include <linux/errno.h>
22#include <linux/topology.h>
23#include <linux/wait.h>
24#include <linux/io.h>
25
26#include <asm/irq.h>
27#include <asm/ptrace.h>
28#include <asm/irq_regs.h>
29
30struct seq_file;
31struct module;
32struct msi_msg;
33enum irqchip_irq_state;
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76enum {
77 IRQ_TYPE_NONE = 0x00000000,
78 IRQ_TYPE_EDGE_RISING = 0x00000001,
79 IRQ_TYPE_EDGE_FALLING = 0x00000002,
80 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
81 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
82 IRQ_TYPE_LEVEL_LOW = 0x00000008,
83 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
84 IRQ_TYPE_SENSE_MASK = 0x0000000f,
85 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
86
87 IRQ_TYPE_PROBE = 0x00000010,
88
89 IRQ_LEVEL = (1 << 8),
90 IRQ_PER_CPU = (1 << 9),
91 IRQ_NOPROBE = (1 << 10),
92 IRQ_NOREQUEST = (1 << 11),
93 IRQ_NOAUTOEN = (1 << 12),
94 IRQ_NO_BALANCING = (1 << 13),
95 IRQ_MOVE_PCNTXT = (1 << 14),
96 IRQ_NESTED_THREAD = (1 << 15),
97 IRQ_NOTHREAD = (1 << 16),
98 IRQ_PER_CPU_DEVID = (1 << 17),
99 IRQ_IS_POLLED = (1 << 18),
100};
101
102#define IRQF_MODIFY_MASK \
103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
106 IRQ_IS_POLLED)
107
108#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
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119enum {
120 IRQ_SET_MASK_OK = 0,
121 IRQ_SET_MASK_OK_NOCOPY,
122 IRQ_SET_MASK_OK_DONE,
123};
124
125struct msi_desc;
126struct irq_domain;
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151struct irq_data {
152 u32 mask;
153 unsigned int irq;
154 unsigned long hwirq;
155 unsigned int node;
156 unsigned int state_use_accessors;
157 struct irq_chip *chip;
158 struct irq_domain *domain;
159#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
160 struct irq_data *parent_data;
161#endif
162 void *handler_data;
163 void *chip_data;
164 struct msi_desc *msi_desc;
165 cpumask_var_t affinity;
166};
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186enum {
187 IRQD_TRIGGER_MASK = 0xf,
188 IRQD_SETAFFINITY_PENDING = (1 << 8),
189 IRQD_NO_BALANCING = (1 << 10),
190 IRQD_PER_CPU = (1 << 11),
191 IRQD_AFFINITY_SET = (1 << 12),
192 IRQD_LEVEL = (1 << 13),
193 IRQD_WAKEUP_STATE = (1 << 14),
194 IRQD_MOVE_PCNTXT = (1 << 15),
195 IRQD_IRQ_DISABLED = (1 << 16),
196 IRQD_IRQ_MASKED = (1 << 17),
197 IRQD_IRQ_INPROGRESS = (1 << 18),
198 IRQD_WAKEUP_ARMED = (1 << 19),
199};
200
201static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
202{
203 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
204}
205
206static inline bool irqd_is_per_cpu(struct irq_data *d)
207{
208 return d->state_use_accessors & IRQD_PER_CPU;
209}
210
211static inline bool irqd_can_balance(struct irq_data *d)
212{
213 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
214}
215
216static inline bool irqd_affinity_was_set(struct irq_data *d)
217{
218 return d->state_use_accessors & IRQD_AFFINITY_SET;
219}
220
221static inline void irqd_mark_affinity_was_set(struct irq_data *d)
222{
223 d->state_use_accessors |= IRQD_AFFINITY_SET;
224}
225
226static inline u32 irqd_get_trigger_type(struct irq_data *d)
227{
228 return d->state_use_accessors & IRQD_TRIGGER_MASK;
229}
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234static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
235{
236 d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
237 d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
238}
239
240static inline bool irqd_is_level_type(struct irq_data *d)
241{
242 return d->state_use_accessors & IRQD_LEVEL;
243}
244
245static inline bool irqd_is_wakeup_set(struct irq_data *d)
246{
247 return d->state_use_accessors & IRQD_WAKEUP_STATE;
248}
249
250static inline bool irqd_can_move_in_process_context(struct irq_data *d)
251{
252 return d->state_use_accessors & IRQD_MOVE_PCNTXT;
253}
254
255static inline bool irqd_irq_disabled(struct irq_data *d)
256{
257 return d->state_use_accessors & IRQD_IRQ_DISABLED;
258}
259
260static inline bool irqd_irq_masked(struct irq_data *d)
261{
262 return d->state_use_accessors & IRQD_IRQ_MASKED;
263}
264
265static inline bool irqd_irq_inprogress(struct irq_data *d)
266{
267 return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
268}
269
270static inline bool irqd_is_wakeup_armed(struct irq_data *d)
271{
272 return d->state_use_accessors & IRQD_WAKEUP_ARMED;
273}
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281static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
282{
283 d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
284}
285
286static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
287{
288 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
289}
290
291static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
292{
293 return d->hwirq;
294}
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332struct irq_chip {
333 const char *name;
334 unsigned int (*irq_startup)(struct irq_data *data);
335 void (*irq_shutdown)(struct irq_data *data);
336 void (*irq_enable)(struct irq_data *data);
337 void (*irq_disable)(struct irq_data *data);
338
339 void (*irq_ack)(struct irq_data *data);
340 void (*irq_mask)(struct irq_data *data);
341 void (*irq_mask_ack)(struct irq_data *data);
342 void (*irq_unmask)(struct irq_data *data);
343 void (*irq_eoi)(struct irq_data *data);
344
345 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
346 int (*irq_retrigger)(struct irq_data *data);
347 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
348 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
349
350 void (*irq_bus_lock)(struct irq_data *data);
351 void (*irq_bus_sync_unlock)(struct irq_data *data);
352
353 void (*irq_cpu_online)(struct irq_data *data);
354 void (*irq_cpu_offline)(struct irq_data *data);
355
356 void (*irq_suspend)(struct irq_data *data);
357 void (*irq_resume)(struct irq_data *data);
358 void (*irq_pm_shutdown)(struct irq_data *data);
359
360 void (*irq_calc_mask)(struct irq_data *data);
361
362 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
363 int (*irq_request_resources)(struct irq_data *data);
364 void (*irq_release_resources)(struct irq_data *data);
365
366 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
367 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
368
369 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
370 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
371
372 unsigned long flags;
373};
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387enum {
388 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
389 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
390 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
391 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
392 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
393 IRQCHIP_ONESHOT_SAFE = (1 << 5),
394 IRQCHIP_EOI_THREADED = (1 << 6),
395};
396
397
398#include <linux/irqdesc.h>
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403#include <asm/hw_irq.h>
404
405#ifndef NR_IRQS_LEGACY
406# define NR_IRQS_LEGACY 0
407#endif
408
409#ifndef ARCH_IRQ_INIT_FLAGS
410# define ARCH_IRQ_INIT_FLAGS 0
411#endif
412
413#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
414
415struct irqaction;
416extern int setup_irq(unsigned int irq, struct irqaction *new);
417extern void remove_irq(unsigned int irq, struct irqaction *act);
418extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
419extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
420
421extern void irq_cpu_online(void);
422extern void irq_cpu_offline(void);
423extern int irq_set_affinity_locked(struct irq_data *data,
424 const struct cpumask *cpumask, bool force);
425
426#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
427void irq_move_irq(struct irq_data *data);
428void irq_move_masked_irq(struct irq_data *data);
429#else
430static inline void irq_move_irq(struct irq_data *data) { }
431static inline void irq_move_masked_irq(struct irq_data *data) { }
432#endif
433
434extern int no_irq_affinity;
435
436#ifdef CONFIG_HARDIRQS_SW_RESEND
437int irq_set_parent(int irq, int parent_irq);
438#else
439static inline int irq_set_parent(int irq, int parent_irq)
440{
441 return 0;
442}
443#endif
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449extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
450extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
451extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
452extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
453extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
454extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
455extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
456extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
457extern void handle_nested_irq(unsigned int irq);
458
459extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
460#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
461extern void irq_chip_ack_parent(struct irq_data *data);
462extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
463extern void irq_chip_mask_parent(struct irq_data *data);
464extern void irq_chip_unmask_parent(struct irq_data *data);
465extern void irq_chip_eoi_parent(struct irq_data *data);
466extern int irq_chip_set_affinity_parent(struct irq_data *data,
467 const struct cpumask *dest,
468 bool force);
469extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
470#endif
471
472
473extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
474 irqreturn_t action_ret);
475
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477
478extern int noirqdebug_setup(char *str);
479
480
481extern int can_request_irq(unsigned int irq, unsigned long irqflags);
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484extern struct irq_chip no_irq_chip;
485extern struct irq_chip dummy_irq_chip;
486
487extern void
488irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
489 irq_flow_handler_t handle, const char *name);
490
491static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
492 irq_flow_handler_t handle)
493{
494 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
495}
496
497extern int irq_set_percpu_devid(unsigned int irq);
498
499extern void
500__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
501 const char *name);
502
503static inline void
504irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
505{
506 __irq_set_handler(irq, handle, 0, NULL);
507}
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514static inline void
515irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
516{
517 __irq_set_handler(irq, handle, 1, NULL);
518}
519
520void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
521
522static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
523{
524 irq_modify_status(irq, 0, set);
525}
526
527static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
528{
529 irq_modify_status(irq, clr, 0);
530}
531
532static inline void irq_set_noprobe(unsigned int irq)
533{
534 irq_modify_status(irq, 0, IRQ_NOPROBE);
535}
536
537static inline void irq_set_probe(unsigned int irq)
538{
539 irq_modify_status(irq, IRQ_NOPROBE, 0);
540}
541
542static inline void irq_set_nothread(unsigned int irq)
543{
544 irq_modify_status(irq, 0, IRQ_NOTHREAD);
545}
546
547static inline void irq_set_thread(unsigned int irq)
548{
549 irq_modify_status(irq, IRQ_NOTHREAD, 0);
550}
551
552static inline void irq_set_nested_thread(unsigned int irq, bool nest)
553{
554 if (nest)
555 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
556 else
557 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
558}
559
560static inline void irq_set_percpu_devid_flags(unsigned int irq)
561{
562 irq_set_status_flags(irq,
563 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
564 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
565}
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568extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
569extern int irq_set_handler_data(unsigned int irq, void *data);
570extern int irq_set_chip_data(unsigned int irq, void *data);
571extern int irq_set_irq_type(unsigned int irq, unsigned int type);
572extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
573extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
574 struct msi_desc *entry);
575extern struct irq_data *irq_get_irq_data(unsigned int irq);
576
577static inline struct irq_chip *irq_get_chip(unsigned int irq)
578{
579 struct irq_data *d = irq_get_irq_data(irq);
580 return d ? d->chip : NULL;
581}
582
583static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
584{
585 return d->chip;
586}
587
588static inline void *irq_get_chip_data(unsigned int irq)
589{
590 struct irq_data *d = irq_get_irq_data(irq);
591 return d ? d->chip_data : NULL;
592}
593
594static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
595{
596 return d->chip_data;
597}
598
599static inline void *irq_get_handler_data(unsigned int irq)
600{
601 struct irq_data *d = irq_get_irq_data(irq);
602 return d ? d->handler_data : NULL;
603}
604
605static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
606{
607 return d->handler_data;
608}
609
610static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
611{
612 struct irq_data *d = irq_get_irq_data(irq);
613 return d ? d->msi_desc : NULL;
614}
615
616static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
617{
618 return d->msi_desc;
619}
620
621static inline u32 irq_get_trigger_type(unsigned int irq)
622{
623 struct irq_data *d = irq_get_irq_data(irq);
624 return d ? irqd_get_trigger_type(d) : 0;
625}
626
627unsigned int arch_dynirq_lower_bound(unsigned int from);
628
629int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
630 struct module *owner);
631
632
633#define irq_alloc_descs(irq, from, cnt, node) \
634 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
635
636#define irq_alloc_desc(node) \
637 irq_alloc_descs(-1, 0, 1, node)
638
639#define irq_alloc_desc_at(at, node) \
640 irq_alloc_descs(at, at, 1, node)
641
642#define irq_alloc_desc_from(from, node) \
643 irq_alloc_descs(-1, from, 1, node)
644
645#define irq_alloc_descs_from(from, cnt, node) \
646 irq_alloc_descs(-1, from, cnt, node)
647
648void irq_free_descs(unsigned int irq, unsigned int cnt);
649static inline void irq_free_desc(unsigned int irq)
650{
651 irq_free_descs(irq, 1);
652}
653
654#ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
655unsigned int irq_alloc_hwirqs(int cnt, int node);
656static inline unsigned int irq_alloc_hwirq(int node)
657{
658 return irq_alloc_hwirqs(1, node);
659}
660void irq_free_hwirqs(unsigned int from, int cnt);
661static inline void irq_free_hwirq(unsigned int irq)
662{
663 return irq_free_hwirqs(irq, 1);
664}
665int arch_setup_hwirq(unsigned int irq, int node);
666void arch_teardown_hwirq(unsigned int irq);
667#endif
668
669#ifdef CONFIG_GENERIC_IRQ_LEGACY
670void irq_init_desc(unsigned int irq);
671#endif
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683struct irq_chip_regs {
684 unsigned long enable;
685 unsigned long disable;
686 unsigned long mask;
687 unsigned long ack;
688 unsigned long eoi;
689 unsigned long type;
690 unsigned long polarity;
691};
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706struct irq_chip_type {
707 struct irq_chip chip;
708 struct irq_chip_regs regs;
709 irq_flow_handler_t handler;
710 u32 type;
711 u32 mask_cache_priv;
712 u32 *mask_cache;
713};
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742struct irq_chip_generic {
743 raw_spinlock_t lock;
744 void __iomem *reg_base;
745 u32 (*reg_readl)(void __iomem *addr);
746 void (*reg_writel)(u32 val, void __iomem *addr);
747 unsigned int irq_base;
748 unsigned int irq_cnt;
749 u32 mask_cache;
750 u32 type_cache;
751 u32 polarity_cache;
752 u32 wake_enabled;
753 u32 wake_active;
754 unsigned int num_ct;
755 void *private;
756 unsigned long installed;
757 unsigned long unused;
758 struct irq_domain *domain;
759 struct list_head list;
760 struct irq_chip_type chip_types[0];
761};
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773enum irq_gc_flags {
774 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
775 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
776 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
777 IRQ_GC_NO_MASK = 1 << 3,
778 IRQ_GC_BE_IO = 1 << 4,
779};
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790struct irq_domain_chip_generic {
791 unsigned int irqs_per_chip;
792 unsigned int num_chips;
793 unsigned int irq_flags_to_clear;
794 unsigned int irq_flags_to_set;
795 enum irq_gc_flags gc_flags;
796 struct irq_chip_generic *gc[0];
797};
798
799
800void irq_gc_noop(struct irq_data *d);
801void irq_gc_mask_disable_reg(struct irq_data *d);
802void irq_gc_mask_set_bit(struct irq_data *d);
803void irq_gc_mask_clr_bit(struct irq_data *d);
804void irq_gc_unmask_enable_reg(struct irq_data *d);
805void irq_gc_ack_set_bit(struct irq_data *d);
806void irq_gc_ack_clr_bit(struct irq_data *d);
807void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
808void irq_gc_eoi(struct irq_data *d);
809int irq_gc_set_wake(struct irq_data *d, unsigned int on);
810
811
812int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
813 irq_hw_number_t hw_irq);
814struct irq_chip_generic *
815irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
816 void __iomem *reg_base, irq_flow_handler_t handler);
817void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
818 enum irq_gc_flags flags, unsigned int clr,
819 unsigned int set);
820int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
821void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
822 unsigned int clr, unsigned int set);
823
824struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
825int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
826 int num_ct, const char *name,
827 irq_flow_handler_t handler,
828 unsigned int clr, unsigned int set,
829 enum irq_gc_flags flags);
830
831
832static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
833{
834 return container_of(d->chip, struct irq_chip_type, chip);
835}
836
837#define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
838
839#ifdef CONFIG_SMP
840static inline void irq_gc_lock(struct irq_chip_generic *gc)
841{
842 raw_spin_lock(&gc->lock);
843}
844
845static inline void irq_gc_unlock(struct irq_chip_generic *gc)
846{
847 raw_spin_unlock(&gc->lock);
848}
849#else
850static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
851static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
852#endif
853
854static inline void irq_reg_writel(struct irq_chip_generic *gc,
855 u32 val, int reg_offset)
856{
857 if (gc->reg_writel)
858 gc->reg_writel(val, gc->reg_base + reg_offset);
859 else
860 writel(val, gc->reg_base + reg_offset);
861}
862
863static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
864 int reg_offset)
865{
866 if (gc->reg_readl)
867 return gc->reg_readl(gc->reg_base + reg_offset);
868 else
869 return readl(gc->reg_base + reg_offset);
870}
871
872#endif
873