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33#ifndef MLX5_IFC_H
34#define MLX5_IFC_H
35
36enum {
37 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
38 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
39 MLX5_CMD_OP_INIT_HCA = 0x102,
40 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
41 MLX5_CMD_OP_ENABLE_HCA = 0x104,
42 MLX5_CMD_OP_DISABLE_HCA = 0x105,
43 MLX5_CMD_OP_QUERY_PAGES = 0x107,
44 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
45 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
46 MLX5_CMD_OP_CREATE_MKEY = 0x200,
47 MLX5_CMD_OP_QUERY_MKEY = 0x201,
48 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
49 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
50 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
51 MLX5_CMD_OP_CREATE_EQ = 0x301,
52 MLX5_CMD_OP_DESTROY_EQ = 0x302,
53 MLX5_CMD_OP_QUERY_EQ = 0x303,
54 MLX5_CMD_OP_GEN_EQE = 0x304,
55 MLX5_CMD_OP_CREATE_CQ = 0x400,
56 MLX5_CMD_OP_DESTROY_CQ = 0x401,
57 MLX5_CMD_OP_QUERY_CQ = 0x402,
58 MLX5_CMD_OP_MODIFY_CQ = 0x403,
59 MLX5_CMD_OP_CREATE_QP = 0x500,
60 MLX5_CMD_OP_DESTROY_QP = 0x501,
61 MLX5_CMD_OP_RST2INIT_QP = 0x502,
62 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
63 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
64 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
65 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
66 MLX5_CMD_OP_2ERR_QP = 0x507,
67 MLX5_CMD_OP_2RST_QP = 0x50a,
68 MLX5_CMD_OP_QUERY_QP = 0x50b,
69 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
70 MLX5_CMD_OP_CREATE_PSV = 0x600,
71 MLX5_CMD_OP_DESTROY_PSV = 0x601,
72 MLX5_CMD_OP_CREATE_SRQ = 0x700,
73 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
74 MLX5_CMD_OP_QUERY_SRQ = 0x702,
75 MLX5_CMD_OP_ARM_RQ = 0x703,
76 MLX5_CMD_OP_RESIZE_SRQ = 0x704,
77 MLX5_CMD_OP_CREATE_DCT = 0x710,
78 MLX5_CMD_OP_DESTROY_DCT = 0x711,
79 MLX5_CMD_OP_DRAIN_DCT = 0x712,
80 MLX5_CMD_OP_QUERY_DCT = 0x713,
81 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
82 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
83 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
84 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
85 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
86 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
87 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
88 MLX5_CMD_OP_QUERY_RCOE_ADDRESS = 0x760,
89 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
90 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
91 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
92 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
93 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
94 MLX5_CMD_OP_ALLOC_PD = 0x800,
95 MLX5_CMD_OP_DEALLOC_PD = 0x801,
96 MLX5_CMD_OP_ALLOC_UAR = 0x802,
97 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
98 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
99 MLX5_CMD_OP_ACCESS_REG = 0x805,
100 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
101 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
102 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
103 MLX5_CMD_OP_MAD_IFC = 0x50d,
104 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
105 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
106 MLX5_CMD_OP_NOP = 0x80d,
107 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
108 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
109 MLX5_CMD_OP_SET_BURST_SIZE = 0x812,
110 MLX5_CMD_OP_QUERY_BURST_SZIE = 0x813,
111 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814,
112 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815,
113 MLX5_CMD_OP_CREATE_SNIFFER_RULE = 0x820,
114 MLX5_CMD_OP_DESTROY_SNIFFER_RULE = 0x821,
115 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x822,
116 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x823,
117 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x824,
118 MLX5_CMD_OP_CREATE_TIR = 0x900,
119 MLX5_CMD_OP_MODIFY_TIR = 0x901,
120 MLX5_CMD_OP_DESTROY_TIR = 0x902,
121 MLX5_CMD_OP_QUERY_TIR = 0x903,
122 MLX5_CMD_OP_CREATE_TIS = 0x912,
123 MLX5_CMD_OP_MODIFY_TIS = 0x913,
124 MLX5_CMD_OP_DESTROY_TIS = 0x914,
125 MLX5_CMD_OP_QUERY_TIS = 0x915,
126 MLX5_CMD_OP_CREATE_SQ = 0x904,
127 MLX5_CMD_OP_MODIFY_SQ = 0x905,
128 MLX5_CMD_OP_DESTROY_SQ = 0x906,
129 MLX5_CMD_OP_QUERY_SQ = 0x907,
130 MLX5_CMD_OP_CREATE_RQ = 0x908,
131 MLX5_CMD_OP_MODIFY_RQ = 0x909,
132 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
133 MLX5_CMD_OP_QUERY_RQ = 0x90b,
134 MLX5_CMD_OP_CREATE_RMP = 0x90c,
135 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
136 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
137 MLX5_CMD_OP_QUERY_RMP = 0x90f,
138 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x910,
139 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x911,
140 MLX5_CMD_OP_MAX = 0x911
141};
142
143struct mlx5_ifc_cmd_hca_cap_bits {
144 u8 reserved_0[0x80];
145
146 u8 log_max_srq_sz[0x8];
147 u8 log_max_qp_sz[0x8];
148 u8 reserved_1[0xb];
149 u8 log_max_qp[0x5];
150
151 u8 log_max_strq_sz[0x8];
152 u8 reserved_2[0x3];
153 u8 log_max_srqs[0x5];
154 u8 reserved_3[0x10];
155
156 u8 reserved_4[0x8];
157 u8 log_max_cq_sz[0x8];
158 u8 reserved_5[0xb];
159 u8 log_max_cq[0x5];
160
161 u8 log_max_eq_sz[0x8];
162 u8 reserved_6[0x2];
163 u8 log_max_mkey[0x6];
164 u8 reserved_7[0xc];
165 u8 log_max_eq[0x4];
166
167 u8 max_indirection[0x8];
168 u8 reserved_8[0x1];
169 u8 log_max_mrw_sz[0x7];
170 u8 reserved_9[0x2];
171 u8 log_max_bsf_list_size[0x6];
172 u8 reserved_10[0x2];
173 u8 log_max_klm_list_size[0x6];
174
175 u8 reserved_11[0xa];
176 u8 log_max_ra_req_dc[0x6];
177 u8 reserved_12[0xa];
178 u8 log_max_ra_res_dc[0x6];
179
180 u8 reserved_13[0xa];
181 u8 log_max_ra_req_qp[0x6];
182 u8 reserved_14[0xa];
183 u8 log_max_ra_res_qp[0x6];
184
185 u8 pad_cap[0x1];
186 u8 cc_query_allowed[0x1];
187 u8 cc_modify_allowed[0x1];
188 u8 reserved_15[0x1d];
189
190 u8 reserved_16[0x6];
191 u8 max_qp_cnt[0xa];
192 u8 pkey_table_size[0x10];
193
194 u8 eswitch_owner[0x1];
195 u8 reserved_17[0xa];
196 u8 local_ca_ack_delay[0x5];
197 u8 reserved_18[0x8];
198 u8 num_ports[0x8];
199
200 u8 reserved_19[0x3];
201 u8 log_max_msg[0x5];
202 u8 reserved_20[0x18];
203
204 u8 stat_rate_support[0x10];
205 u8 reserved_21[0x10];
206
207 u8 reserved_22[0x10];
208 u8 cmdif_checksum[0x2];
209 u8 sigerr_cqe[0x1];
210 u8 reserved_23[0x1];
211 u8 wq_signature[0x1];
212 u8 sctr_data_cqe[0x1];
213 u8 reserved_24[0x1];
214 u8 sho[0x1];
215 u8 tph[0x1];
216 u8 rf[0x1];
217 u8 dc[0x1];
218 u8 reserved_25[0x2];
219 u8 roce[0x1];
220 u8 atomic[0x1];
221 u8 rsz_srq[0x1];
222
223 u8 cq_oi[0x1];
224 u8 cq_resize[0x1];
225 u8 cq_moderation[0x1];
226 u8 sniffer_rule_flow[0x1];
227 u8 sniffer_rule_vport[0x1];
228 u8 sniffer_rule_phy[0x1];
229 u8 reserved_26[0x1];
230 u8 pg[0x1];
231 u8 block_lb_mc[0x1];
232 u8 reserved_27[0x3];
233 u8 cd[0x1];
234 u8 reserved_28[0x1];
235 u8 apm[0x1];
236 u8 reserved_29[0x7];
237 u8 qkv[0x1];
238 u8 pkv[0x1];
239 u8 reserved_30[0x4];
240 u8 xrc[0x1];
241 u8 ud[0x1];
242 u8 uc[0x1];
243 u8 rc[0x1];
244
245 u8 reserved_31[0xa];
246 u8 uar_sz[0x6];
247 u8 reserved_32[0x8];
248 u8 log_pg_sz[0x8];
249
250 u8 bf[0x1];
251 u8 reserved_33[0xa];
252 u8 log_bf_reg_size[0x5];
253 u8 reserved_34[0x10];
254
255 u8 reserved_35[0x10];
256 u8 max_wqe_sz_sq[0x10];
257
258 u8 reserved_36[0x10];
259 u8 max_wqe_sz_rq[0x10];
260
261 u8 reserved_37[0x10];
262 u8 max_wqe_sz_sq_dc[0x10];
263
264 u8 reserved_38[0x7];
265 u8 max_qp_mcg[0x19];
266
267 u8 reserved_39[0x18];
268 u8 log_max_mcg[0x8];
269
270 u8 reserved_40[0xb];
271 u8 log_max_pd[0x5];
272 u8 reserved_41[0xb];
273 u8 log_max_xrcd[0x5];
274
275 u8 reserved_42[0x20];
276
277 u8 reserved_43[0x3];
278 u8 log_max_rq[0x5];
279 u8 reserved_44[0x3];
280 u8 log_max_sq[0x5];
281 u8 reserved_45[0x3];
282 u8 log_max_tir[0x5];
283 u8 reserved_46[0x3];
284 u8 log_max_tis[0x5];
285
286 u8 reserved_47[0x13];
287 u8 log_max_rq_per_tir[0x5];
288 u8 reserved_48[0x3];
289 u8 log_max_tis_per_sq[0x5];
290
291 u8 reserved_49[0xe0];
292
293 u8 reserved_50[0x10];
294 u8 log_uar_page_sz[0x10];
295
296 u8 reserved_51[0x100];
297
298 u8 reserved_52[0x1f];
299 u8 cqe_zip[0x1];
300
301 u8 cqe_zip_timeout[0x10];
302 u8 cqe_zip_max_num[0x10];
303
304 u8 reserved_53[0x220];
305};
306
307struct mlx5_ifc_set_hca_cap_in_bits {
308 u8 opcode[0x10];
309 u8 reserved_0[0x10];
310
311 u8 reserved_1[0x10];
312 u8 op_mod[0x10];
313
314 u8 reserved_2[0x40];
315
316 struct mlx5_ifc_cmd_hca_cap_bits hca_capability_struct;
317};
318
319struct mlx5_ifc_query_hca_cap_in_bits {
320 u8 opcode[0x10];
321 u8 reserved_0[0x10];
322
323 u8 reserved_1[0x10];
324 u8 op_mod[0x10];
325
326 u8 reserved_2[0x40];
327};
328
329struct mlx5_ifc_query_hca_cap_out_bits {
330 u8 status[0x8];
331 u8 reserved_0[0x18];
332
333 u8 syndrome[0x20];
334
335 u8 reserved_1[0x40];
336
337 u8 capability_struct[256][0x8];
338};
339
340struct mlx5_ifc_set_hca_cap_out_bits {
341 u8 status[0x8];
342 u8 reserved_0[0x18];
343
344 u8 syndrome[0x20];
345
346 u8 reserved_1[0x40];
347};
348
349#endif
350
