LXR linux/arch/alpha/kernel/machvec

   1/*
   2 *      linux/arch/alpha/kernel/machvec_impl.h
   3 *
   4 *      Copyright (C) 1997, 1998  Richard Henderson
   5 *
   6 * This file has goodies to help simplify instantiation of machine vectors.
   7 */
   8
   9#include <asm/pgalloc.h>
  10
  11/* Whee.  These systems don't have an HAE:
  12       IRONGATE, MARVEL, POLARIS, TSUNAMI, TITAN, WILDFIRE
  13   Fix things up for the GENERIC kernel by defining the HAE address
  14   to be that of the cache. Now we can read and write it as we like.  ;-)  */
  15#define IRONGATE_HAE_ADDRESS    (&alpha_mv.hae_cache)
  16#define MARVEL_HAE_ADDRESS      (&alpha_mv.hae_cache)
  17#define POLARIS_HAE_ADDRESS     (&alpha_mv.hae_cache)
  18#define TSUNAMI_HAE_ADDRESS     (&alpha_mv.hae_cache)
  19#define TITAN_HAE_ADDRESS       (&alpha_mv.hae_cache)
  20#define WILDFIRE_HAE_ADDRESS    (&alpha_mv.hae_cache)
  21
  22#ifdef CIA_ONE_HAE_WINDOW
  23#define CIA_HAE_ADDRESS         (&alpha_mv.hae_cache)
  24#endif
  25#ifdef MCPCIA_ONE_HAE_WINDOW
  26#define MCPCIA_HAE_ADDRESS      (&alpha_mv.hae_cache)
  27#endif
  28#ifdef T2_ONE_HAE_WINDOW
  29#define T2_HAE_ADDRESS          (&alpha_mv.hae_cache)
  30#endif
  31
  32/* Only a few systems don't define IACK_SC, handling all interrupts through
  33   the SRM console.  But splitting out that one case from IO() below
  34   seems like such a pain.  Define this to get things to compile.  */
  35#define JENSEN_IACK_SC          1
  36#define T2_IACK_SC              1
  37#define WILDFIRE_IACK_SC        1 /* FIXME */
  38
  39/*
  40 * Some helpful macros for filling in the blanks.
  41 */
  42
  43#define CAT1(x,y)  x##y
  44#define CAT(x,y)   CAT1(x,y)
  45
  46#define DO_DEFAULT_RTC                  .rtc_port = 0x70
  47
  48#define DO_EV4_MMU                                                      \
  49        .max_asn =                      EV4_MAX_ASN,                    \
  50        .mv_switch_mm =                 ev4_switch_mm,                  \
  51        .mv_activate_mm =               ev4_activate_mm,                \
  52        .mv_flush_tlb_current =         ev4_flush_tlb_current,          \
  53        .mv_flush_tlb_current_page =    ev4_flush_tlb_current_page
  54
  55#define DO_EV5_MMU                                                      \
  56        .max_asn =                      EV5_MAX_ASN,                    \
  57        .mv_switch_mm =                 ev5_switch_mm,                  \
  58        .mv_activate_mm =               ev5_activate_mm,                \
  59        .mv_flush_tlb_current =         ev5_flush_tlb_current,          \
  60        .mv_flush_tlb_current_page =    ev5_flush_tlb_current_page
  61
  62#define DO_EV6_MMU                                                      \
  63        .max_asn =                      EV6_MAX_ASN,                    \
  64        .mv_switch_mm =                 ev5_switch_mm,                  \
  65        .mv_activate_mm =               ev5_activate_mm,                \
  66        .mv_flush_tlb_current =         ev5_flush_tlb_current,          \
  67        .mv_flush_tlb_current_page =    ev5_flush_tlb_current_page
  68
  69#define DO_EV7_MMU                                                      \
  70        .max_asn =                      EV6_MAX_ASN,                    \
  71        .mv_switch_mm =                 ev5_switch_mm,                  \
  72        .mv_activate_mm =               ev5_activate_mm,                \
  73        .mv_flush_tlb_current =         ev5_flush_tlb_current,          \
  74        .mv_flush_tlb_current_page =    ev5_flush_tlb_current_page
  75
  76#define IO_LITE(UP,low)                                                 \
  77        .hae_register =         (unsigned long *) CAT(UP,_HAE_ADDRESS), \
  78        .iack_sc =              CAT(UP,_IACK_SC),                       \
  79        .mv_ioread8 =           CAT(low,_ioread8),                      \
  80        .mv_ioread16 =          CAT(low,_ioread16),                     \
  81        .mv_ioread32 =          CAT(low,_ioread32),                     \
  82        .mv_iowrite8 =          CAT(low,_iowrite8),                     \
  83        .mv_iowrite16 =         CAT(low,_iowrite16),                    \
  84        .mv_iowrite32 =         CAT(low,_iowrite32),                    \
  85        .mv_readb =             CAT(low,_readb),                        \
  86        .mv_readw =             CAT(low,_readw),                        \
  87        .mv_readl =             CAT(low,_readl),                        \
  88        .mv_readq =             CAT(low,_readq),                        \
  89        .mv_writeb =            CAT(low,_writeb),                       \
  90        .mv_writew =            CAT(low,_writew),                       \
  91        .mv_writel =            CAT(low,_writel),                       \
  92        .mv_writeq =            CAT(low,_writeq),                       \
  93        .mv_ioportmap =         CAT(low,_ioportmap),                    \
  94        .mv_ioremap =           CAT(low,_ioremap),                      \
  95        .mv_iounmap =           CAT(low,_iounmap),                      \
  96        .mv_is_ioaddr =         CAT(low,_is_ioaddr),                    \
  97        .mv_is_mmio =           CAT(low,_is_mmio)                       \
  98
  99#define IO(UP,low)                                                      \
 100        IO_LITE(UP,low),                                                \
 101        .pci_ops =              &CAT(low,_pci_ops),                     \
 102        .mv_pci_tbi =           CAT(low,_pci_tbi)
 103
 104#define DO_APECS_IO     IO(APECS,apecs)
 105#define DO_CIA_IO       IO(CIA,cia)
 106#define DO_IRONGATE_IO  IO(IRONGATE,irongate)
 107#define DO_LCA_IO       IO(LCA,lca)
 108#define DO_MARVEL_IO    IO(MARVEL,marvel)
 109#define DO_MCPCIA_IO    IO(MCPCIA,mcpcia)
 110#define DO_POLARIS_IO   IO(POLARIS,polaris)
 111#define DO_T2_IO        IO(T2,t2)
 112#define DO_TSUNAMI_IO   IO(TSUNAMI,tsunami)
 113#define DO_TITAN_IO     IO(TITAN,titan)
 114#define DO_WILDFIRE_IO  IO(WILDFIRE,wildfire)
 115
 116#define DO_PYXIS_IO     IO_LITE(CIA,cia_bwx), \
 117                        .pci_ops = &cia_pci_ops, \
 118                        .mv_pci_tbi = cia_pci_tbi
 119
 120/*
 121 * In a GENERIC kernel, we have lots of these vectors floating about,
 122 * all but one of which we want to go away.  In a non-GENERIC kernel,
 123 * we want only one, ever.
 124 *
 125 * Accomplish this in the GENERIC kernel by putting all of the vectors
 126 * in the .init.data section where they'll go away.  We'll copy the
 127 * one we want to the real alpha_mv vector in setup_arch.
 128 *
 129 * Accomplish this in a non-GENERIC kernel by ifdef'ing out all but
 130 * one of the vectors, which will not reside in .init.data.  We then
 131 * alias this one vector to alpha_mv, so no copy is needed.
 132 *
 133 * Upshot: set __initdata to nothing for non-GENERIC kernels.
 134 */
 135
 136#ifdef CONFIG_ALPHA_GENERIC
 137#define __initmv __initdata
 138#define ALIAS_MV(x)
 139#else
 140#define __initmv __refdata
 141
 142/* GCC actually has a syntax for defining aliases, but is under some
 143   delusion that you shouldn't be able to declare it extern somewhere
 144   else beforehand.  Fine.  We'll do it ourselves.  */
 145#if 0
 146#define ALIAS_MV(system) \
 147  struct alpha_machine_vector alpha_mv __attribute__((alias(#system "_mv"))); \
 148  EXPORT_SYMBOL(alpha_mv);
 149#else
 150#define ALIAS_MV(system) \
 151  asm(".global alpha_mv\nalpha_mv = " #system "_mv"); \
 152  EXPORT_SYMBOL(alpha_mv);
 153#endif
 154#endif /* GENERIC */
 155