1#ifndef __iop_sw_mpu_defs_h
2#define __iop_sw_mpu_defs_h
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17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85
86
87
88typedef struct {
89 unsigned int cfg : 2;
90 unsigned int dummy1 : 30;
91} reg_iop_sw_mpu_rw_sw_cfg_owner;
92#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
93#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
94
95
96typedef struct {
97 unsigned int keep_owner : 1;
98 unsigned int cmd : 2;
99 unsigned int size : 3;
100 unsigned int wr_spu0_mem : 1;
101 unsigned int wr_spu1_mem : 1;
102 unsigned int dummy1 : 24;
103} reg_iop_sw_mpu_rw_mc_ctrl;
104#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4
105#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4
106
107
108typedef struct {
109 unsigned int val : 32;
110} reg_iop_sw_mpu_rw_mc_data;
111#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8
112#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8
113
114
115typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
116#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12
117#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12
118
119
120typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
121#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16
122
123
124typedef unsigned int reg_iop_sw_mpu_r_mc_data;
125#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20
126
127
128typedef struct {
129 unsigned int busy_cpu : 1;
130 unsigned int busy_mpu : 1;
131 unsigned int busy_spu0 : 1;
132 unsigned int busy_spu1 : 1;
133 unsigned int owned_by_cpu : 1;
134 unsigned int owned_by_mpu : 1;
135 unsigned int owned_by_spu0 : 1;
136 unsigned int owned_by_spu1 : 1;
137 unsigned int dummy1 : 24;
138} reg_iop_sw_mpu_r_mc_stat;
139#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24
140
141
142typedef struct {
143 unsigned int byte0 : 8;
144 unsigned int byte1 : 8;
145 unsigned int byte2 : 8;
146 unsigned int byte3 : 8;
147} reg_iop_sw_mpu_rw_bus0_clr_mask;
148#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
149#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
150
151
152typedef struct {
153 unsigned int byte0 : 8;
154 unsigned int byte1 : 8;
155 unsigned int byte2 : 8;
156 unsigned int byte3 : 8;
157} reg_iop_sw_mpu_rw_bus0_set_mask;
158#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
159#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
160
161
162typedef struct {
163 unsigned int byte0 : 1;
164 unsigned int byte1 : 1;
165 unsigned int byte2 : 1;
166 unsigned int byte3 : 1;
167 unsigned int dummy1 : 28;
168} reg_iop_sw_mpu_rw_bus0_oe_clr_mask;
169#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
170#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
171
172
173typedef struct {
174 unsigned int byte0 : 1;
175 unsigned int byte1 : 1;
176 unsigned int byte2 : 1;
177 unsigned int byte3 : 1;
178 unsigned int dummy1 : 28;
179} reg_iop_sw_mpu_rw_bus0_oe_set_mask;
180#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
181#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
182
183
184typedef unsigned int reg_iop_sw_mpu_r_bus0_in;
185#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44
186
187
188typedef struct {
189 unsigned int byte0 : 8;
190 unsigned int byte1 : 8;
191 unsigned int byte2 : 8;
192 unsigned int byte3 : 8;
193} reg_iop_sw_mpu_rw_bus1_clr_mask;
194#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
195#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
196
197
198typedef struct {
199 unsigned int byte0 : 8;
200 unsigned int byte1 : 8;
201 unsigned int byte2 : 8;
202 unsigned int byte3 : 8;
203} reg_iop_sw_mpu_rw_bus1_set_mask;
204#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
205#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
206
207
208typedef struct {
209 unsigned int byte0 : 1;
210 unsigned int byte1 : 1;
211 unsigned int byte2 : 1;
212 unsigned int byte3 : 1;
213 unsigned int dummy1 : 28;
214} reg_iop_sw_mpu_rw_bus1_oe_clr_mask;
215#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
216#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
217
218
219typedef struct {
220 unsigned int byte0 : 1;
221 unsigned int byte1 : 1;
222 unsigned int byte2 : 1;
223 unsigned int byte3 : 1;
224 unsigned int dummy1 : 28;
225} reg_iop_sw_mpu_rw_bus1_oe_set_mask;
226#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
227#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
228
229
230typedef unsigned int reg_iop_sw_mpu_r_bus1_in;
231#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64
232
233
234typedef struct {
235 unsigned int val : 32;
236} reg_iop_sw_mpu_rw_gio_clr_mask;
237#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
238#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
239
240
241typedef struct {
242 unsigned int val : 32;
243} reg_iop_sw_mpu_rw_gio_set_mask;
244#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72
245#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72
246
247
248typedef struct {
249 unsigned int val : 32;
250} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
251#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
252#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
253
254
255typedef struct {
256 unsigned int val : 32;
257} reg_iop_sw_mpu_rw_gio_oe_set_mask;
258#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
259#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
260
261
262typedef unsigned int reg_iop_sw_mpu_r_gio_in;
263#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84
264
265
266typedef struct {
267 unsigned int intr0 : 1;
268 unsigned int intr1 : 1;
269 unsigned int intr2 : 1;
270 unsigned int intr3 : 1;
271 unsigned int intr4 : 1;
272 unsigned int intr5 : 1;
273 unsigned int intr6 : 1;
274 unsigned int intr7 : 1;
275 unsigned int intr8 : 1;
276 unsigned int intr9 : 1;
277 unsigned int intr10 : 1;
278 unsigned int intr11 : 1;
279 unsigned int intr12 : 1;
280 unsigned int intr13 : 1;
281 unsigned int intr14 : 1;
282 unsigned int intr15 : 1;
283 unsigned int intr16 : 1;
284 unsigned int intr17 : 1;
285 unsigned int intr18 : 1;
286 unsigned int intr19 : 1;
287 unsigned int intr20 : 1;
288 unsigned int intr21 : 1;
289 unsigned int intr22 : 1;
290 unsigned int intr23 : 1;
291 unsigned int intr24 : 1;
292 unsigned int intr25 : 1;
293 unsigned int intr26 : 1;
294 unsigned int intr27 : 1;
295 unsigned int intr28 : 1;
296 unsigned int intr29 : 1;
297 unsigned int intr30 : 1;
298 unsigned int intr31 : 1;
299} reg_iop_sw_mpu_rw_cpu_intr;
300#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88
301#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88
302
303
304typedef struct {
305 unsigned int intr0 : 1;
306 unsigned int intr1 : 1;
307 unsigned int intr2 : 1;
308 unsigned int intr3 : 1;
309 unsigned int intr4 : 1;
310 unsigned int intr5 : 1;
311 unsigned int intr6 : 1;
312 unsigned int intr7 : 1;
313 unsigned int intr8 : 1;
314 unsigned int intr9 : 1;
315 unsigned int intr10 : 1;
316 unsigned int intr11 : 1;
317 unsigned int intr12 : 1;
318 unsigned int intr13 : 1;
319 unsigned int intr14 : 1;
320 unsigned int intr15 : 1;
321 unsigned int intr16 : 1;
322 unsigned int intr17 : 1;
323 unsigned int intr18 : 1;
324 unsigned int intr19 : 1;
325 unsigned int intr20 : 1;
326 unsigned int intr21 : 1;
327 unsigned int intr22 : 1;
328 unsigned int intr23 : 1;
329 unsigned int intr24 : 1;
330 unsigned int intr25 : 1;
331 unsigned int intr26 : 1;
332 unsigned int intr27 : 1;
333 unsigned int intr28 : 1;
334 unsigned int intr29 : 1;
335 unsigned int intr30 : 1;
336 unsigned int intr31 : 1;
337} reg_iop_sw_mpu_r_cpu_intr;
338#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92
339
340
341typedef struct {
342 unsigned int spu0_intr0 : 1;
343 unsigned int spu1_intr0 : 1;
344 unsigned int trigger_grp0 : 1;
345 unsigned int trigger_grp4 : 1;
346 unsigned int timer_grp0 : 1;
347 unsigned int fifo_out0 : 1;
348 unsigned int fifo_out0_extra : 1;
349 unsigned int dmc_out0 : 1;
350 unsigned int spu0_intr1 : 1;
351 unsigned int spu1_intr1 : 1;
352 unsigned int trigger_grp1 : 1;
353 unsigned int trigger_grp5 : 1;
354 unsigned int timer_grp1 : 1;
355 unsigned int fifo_in0 : 1;
356 unsigned int fifo_in0_extra : 1;
357 unsigned int dmc_in0 : 1;
358 unsigned int spu0_intr2 : 1;
359 unsigned int spu1_intr2 : 1;
360 unsigned int trigger_grp2 : 1;
361 unsigned int trigger_grp6 : 1;
362 unsigned int timer_grp2 : 1;
363 unsigned int fifo_out1 : 1;
364 unsigned int fifo_out1_extra : 1;
365 unsigned int dmc_out1 : 1;
366 unsigned int spu0_intr3 : 1;
367 unsigned int spu1_intr3 : 1;
368 unsigned int trigger_grp3 : 1;
369 unsigned int trigger_grp7 : 1;
370 unsigned int timer_grp3 : 1;
371 unsigned int fifo_in1 : 1;
372 unsigned int fifo_in1_extra : 1;
373 unsigned int dmc_in1 : 1;
374} reg_iop_sw_mpu_rw_intr_grp0_mask;
375#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
376#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
377
378
379typedef struct {
380 unsigned int spu0_intr0 : 1;
381 unsigned int spu1_intr0 : 1;
382 unsigned int dummy1 : 6;
383 unsigned int spu0_intr1 : 1;
384 unsigned int spu1_intr1 : 1;
385 unsigned int dummy2 : 6;
386 unsigned int spu0_intr2 : 1;
387 unsigned int spu1_intr2 : 1;
388 unsigned int dummy3 : 6;
389 unsigned int spu0_intr3 : 1;
390 unsigned int spu1_intr3 : 1;
391 unsigned int dummy4 : 6;
392} reg_iop_sw_mpu_rw_ack_intr_grp0;
393#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
394#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
395
396
397typedef struct {
398 unsigned int spu0_intr0 : 1;
399 unsigned int spu1_intr0 : 1;
400 unsigned int trigger_grp0 : 1;
401 unsigned int trigger_grp4 : 1;
402 unsigned int timer_grp0 : 1;
403 unsigned int fifo_out0 : 1;
404 unsigned int fifo_out0_extra : 1;
405 unsigned int dmc_out0 : 1;
406 unsigned int spu0_intr1 : 1;
407 unsigned int spu1_intr1 : 1;
408 unsigned int trigger_grp1 : 1;
409 unsigned int trigger_grp5 : 1;
410 unsigned int timer_grp1 : 1;
411 unsigned int fifo_in0 : 1;
412 unsigned int fifo_in0_extra : 1;
413 unsigned int dmc_in0 : 1;
414 unsigned int spu0_intr2 : 1;
415 unsigned int spu1_intr2 : 1;
416 unsigned int trigger_grp2 : 1;
417 unsigned int trigger_grp6 : 1;
418 unsigned int timer_grp2 : 1;
419 unsigned int fifo_out1 : 1;
420 unsigned int fifo_out1_extra : 1;
421 unsigned int dmc_out1 : 1;
422 unsigned int spu0_intr3 : 1;
423 unsigned int spu1_intr3 : 1;
424 unsigned int trigger_grp3 : 1;
425 unsigned int trigger_grp7 : 1;
426 unsigned int timer_grp3 : 1;
427 unsigned int fifo_in1 : 1;
428 unsigned int fifo_in1_extra : 1;
429 unsigned int dmc_in1 : 1;
430} reg_iop_sw_mpu_r_intr_grp0;
431#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104
432
433
434typedef struct {
435 unsigned int spu0_intr0 : 1;
436 unsigned int spu1_intr0 : 1;
437 unsigned int trigger_grp0 : 1;
438 unsigned int trigger_grp4 : 1;
439 unsigned int timer_grp0 : 1;
440 unsigned int fifo_out0 : 1;
441 unsigned int fifo_out0_extra : 1;
442 unsigned int dmc_out0 : 1;
443 unsigned int spu0_intr1 : 1;
444 unsigned int spu1_intr1 : 1;
445 unsigned int trigger_grp1 : 1;
446 unsigned int trigger_grp5 : 1;
447 unsigned int timer_grp1 : 1;
448 unsigned int fifo_in0 : 1;
449 unsigned int fifo_in0_extra : 1;
450 unsigned int dmc_in0 : 1;
451 unsigned int spu0_intr2 : 1;
452 unsigned int spu1_intr2 : 1;
453 unsigned int trigger_grp2 : 1;
454 unsigned int trigger_grp6 : 1;
455 unsigned int timer_grp2 : 1;
456 unsigned int fifo_out1 : 1;
457 unsigned int fifo_out1_extra : 1;
458 unsigned int dmc_out1 : 1;
459 unsigned int spu0_intr3 : 1;
460 unsigned int spu1_intr3 : 1;
461 unsigned int trigger_grp3 : 1;
462 unsigned int trigger_grp7 : 1;
463 unsigned int timer_grp3 : 1;
464 unsigned int fifo_in1 : 1;
465 unsigned int fifo_in1_extra : 1;
466 unsigned int dmc_in1 : 1;
467} reg_iop_sw_mpu_r_masked_intr_grp0;
468#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108
469
470
471typedef struct {
472 unsigned int spu0_intr4 : 1;
473 unsigned int spu1_intr4 : 1;
474 unsigned int trigger_grp0 : 1;
475 unsigned int trigger_grp5 : 1;
476 unsigned int timer_grp0 : 1;
477 unsigned int fifo_in0 : 1;
478 unsigned int fifo_in0_extra : 1;
479 unsigned int dmc_out0 : 1;
480 unsigned int spu0_intr5 : 1;
481 unsigned int spu1_intr5 : 1;
482 unsigned int trigger_grp1 : 1;
483 unsigned int trigger_grp6 : 1;
484 unsigned int timer_grp1 : 1;
485 unsigned int fifo_out1 : 1;
486 unsigned int fifo_out0_extra : 1;
487 unsigned int dmc_in0 : 1;
488 unsigned int spu0_intr6 : 1;
489 unsigned int spu1_intr6 : 1;
490 unsigned int trigger_grp2 : 1;
491 unsigned int trigger_grp7 : 1;
492 unsigned int timer_grp2 : 1;
493 unsigned int fifo_in1 : 1;
494 unsigned int fifo_in1_extra : 1;
495 unsigned int dmc_out1 : 1;
496 unsigned int spu0_intr7 : 1;
497 unsigned int spu1_intr7 : 1;
498 unsigned int trigger_grp3 : 1;
499 unsigned int trigger_grp4 : 1;
500 unsigned int timer_grp3 : 1;
501 unsigned int fifo_out0 : 1;
502 unsigned int fifo_out1_extra : 1;
503 unsigned int dmc_in1 : 1;
504} reg_iop_sw_mpu_rw_intr_grp1_mask;
505#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
506#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
507
508
509typedef struct {
510 unsigned int spu0_intr4 : 1;
511 unsigned int spu1_intr4 : 1;
512 unsigned int dummy1 : 6;
513 unsigned int spu0_intr5 : 1;
514 unsigned int spu1_intr5 : 1;
515 unsigned int dummy2 : 6;
516 unsigned int spu0_intr6 : 1;
517 unsigned int spu1_intr6 : 1;
518 unsigned int dummy3 : 6;
519 unsigned int spu0_intr7 : 1;
520 unsigned int spu1_intr7 : 1;
521 unsigned int dummy4 : 6;
522} reg_iop_sw_mpu_rw_ack_intr_grp1;
523#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
524#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
525
526
527typedef struct {
528 unsigned int spu0_intr4 : 1;
529 unsigned int spu1_intr4 : 1;
530 unsigned int trigger_grp0 : 1;
531 unsigned int trigger_grp5 : 1;
532 unsigned int timer_grp0 : 1;
533 unsigned int fifo_in0 : 1;
534 unsigned int fifo_in0_extra : 1;
535 unsigned int dmc_out0 : 1;
536 unsigned int spu0_intr5 : 1;
537 unsigned int spu1_intr5 : 1;
538 unsigned int trigger_grp1 : 1;
539 unsigned int trigger_grp6 : 1;
540 unsigned int timer_grp1 : 1;
541 unsigned int fifo_out1 : 1;
542 unsigned int fifo_out0_extra : 1;
543 unsigned int dmc_in0 : 1;
544 unsigned int spu0_intr6 : 1;
545 unsigned int spu1_intr6 : 1;
546 unsigned int trigger_grp2 : 1;
547 unsigned int trigger_grp7 : 1;
548 unsigned int timer_grp2 : 1;
549 unsigned int fifo_in1 : 1;
550 unsigned int fifo_in1_extra : 1;
551 unsigned int dmc_out1 : 1;
552 unsigned int spu0_intr7 : 1;
553 unsigned int spu1_intr7 : 1;
554 unsigned int trigger_grp3 : 1;
555 unsigned int trigger_grp4 : 1;
556 unsigned int timer_grp3 : 1;
557 unsigned int fifo_out0 : 1;
558 unsigned int fifo_out1_extra : 1;
559 unsigned int dmc_in1 : 1;
560} reg_iop_sw_mpu_r_intr_grp1;
561#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120
562
563
564typedef struct {
565 unsigned int spu0_intr4 : 1;
566 unsigned int spu1_intr4 : 1;
567 unsigned int trigger_grp0 : 1;
568 unsigned int trigger_grp5 : 1;
569 unsigned int timer_grp0 : 1;
570 unsigned int fifo_in0 : 1;
571 unsigned int fifo_in0_extra : 1;
572 unsigned int dmc_out0 : 1;
573 unsigned int spu0_intr5 : 1;
574 unsigned int spu1_intr5 : 1;
575 unsigned int trigger_grp1 : 1;
576 unsigned int trigger_grp6 : 1;
577 unsigned int timer_grp1 : 1;
578 unsigned int fifo_out1 : 1;
579 unsigned int fifo_out0_extra : 1;
580 unsigned int dmc_in0 : 1;
581 unsigned int spu0_intr6 : 1;
582 unsigned int spu1_intr6 : 1;
583 unsigned int trigger_grp2 : 1;
584 unsigned int trigger_grp7 : 1;
585 unsigned int timer_grp2 : 1;
586 unsigned int fifo_in1 : 1;
587 unsigned int fifo_in1_extra : 1;
588 unsigned int dmc_out1 : 1;
589 unsigned int spu0_intr7 : 1;
590 unsigned int spu1_intr7 : 1;
591 unsigned int trigger_grp3 : 1;
592 unsigned int trigger_grp4 : 1;
593 unsigned int timer_grp3 : 1;
594 unsigned int fifo_out0 : 1;
595 unsigned int fifo_out1_extra : 1;
596 unsigned int dmc_in1 : 1;
597} reg_iop_sw_mpu_r_masked_intr_grp1;
598#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124
599
600
601typedef struct {
602 unsigned int spu0_intr8 : 1;
603 unsigned int spu1_intr8 : 1;
604 unsigned int trigger_grp0 : 1;
605 unsigned int trigger_grp6 : 1;
606 unsigned int timer_grp0 : 1;
607 unsigned int fifo_out1 : 1;
608 unsigned int fifo_out1_extra : 1;
609 unsigned int dmc_out0 : 1;
610 unsigned int spu0_intr9 : 1;
611 unsigned int spu1_intr9 : 1;
612 unsigned int trigger_grp1 : 1;
613 unsigned int trigger_grp7 : 1;
614 unsigned int timer_grp1 : 1;
615 unsigned int fifo_in1 : 1;
616 unsigned int fifo_in1_extra : 1;
617 unsigned int dmc_in0 : 1;
618 unsigned int spu0_intr10 : 1;
619 unsigned int spu1_intr10 : 1;
620 unsigned int trigger_grp2 : 1;
621 unsigned int trigger_grp4 : 1;
622 unsigned int timer_grp2 : 1;
623 unsigned int fifo_out0 : 1;
624 unsigned int fifo_out0_extra : 1;
625 unsigned int dmc_out1 : 1;
626 unsigned int spu0_intr11 : 1;
627 unsigned int spu1_intr11 : 1;
628 unsigned int trigger_grp3 : 1;
629 unsigned int trigger_grp5 : 1;
630 unsigned int timer_grp3 : 1;
631 unsigned int fifo_in0 : 1;
632 unsigned int fifo_in0_extra : 1;
633 unsigned int dmc_in1 : 1;
634} reg_iop_sw_mpu_rw_intr_grp2_mask;
635#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
636#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
637
638
639typedef struct {
640 unsigned int spu0_intr8 : 1;
641 unsigned int spu1_intr8 : 1;
642 unsigned int dummy1 : 6;
643 unsigned int spu0_intr9 : 1;
644 unsigned int spu1_intr9 : 1;
645 unsigned int dummy2 : 6;
646 unsigned int spu0_intr10 : 1;
647 unsigned int spu1_intr10 : 1;
648 unsigned int dummy3 : 6;
649 unsigned int spu0_intr11 : 1;
650 unsigned int spu1_intr11 : 1;
651 unsigned int dummy4 : 6;
652} reg_iop_sw_mpu_rw_ack_intr_grp2;
653#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
654#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
655
656
657typedef struct {
658 unsigned int spu0_intr8 : 1;
659 unsigned int spu1_intr8 : 1;
660 unsigned int trigger_grp0 : 1;
661 unsigned int trigger_grp6 : 1;
662 unsigned int timer_grp0 : 1;
663 unsigned int fifo_out1 : 1;
664 unsigned int fifo_out1_extra : 1;
665 unsigned int dmc_out0 : 1;
666 unsigned int spu0_intr9 : 1;
667 unsigned int spu1_intr9 : 1;
668 unsigned int trigger_grp1 : 1;
669 unsigned int trigger_grp7 : 1;
670 unsigned int timer_grp1 : 1;
671 unsigned int fifo_in1 : 1;
672 unsigned int fifo_in1_extra : 1;
673 unsigned int dmc_in0 : 1;
674 unsigned int spu0_intr10 : 1;
675 unsigned int spu1_intr10 : 1;
676 unsigned int trigger_grp2 : 1;
677 unsigned int trigger_grp4 : 1;
678 unsigned int timer_grp2 : 1;
679 unsigned int fifo_out0 : 1;
680 unsigned int fifo_out0_extra : 1;
681 unsigned int dmc_out1 : 1;
682 unsigned int spu0_intr11 : 1;
683 unsigned int spu1_intr11 : 1;
684 unsigned int trigger_grp3 : 1;
685 unsigned int trigger_grp5 : 1;
686 unsigned int timer_grp3 : 1;
687 unsigned int fifo_in0 : 1;
688 unsigned int fifo_in0_extra : 1;
689 unsigned int dmc_in1 : 1;
690} reg_iop_sw_mpu_r_intr_grp2;
691#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136
692
693
694typedef struct {
695 unsigned int spu0_intr8 : 1;
696 unsigned int spu1_intr8 : 1;
697 unsigned int trigger_grp0 : 1;
698 unsigned int trigger_grp6 : 1;
699 unsigned int timer_grp0 : 1;
700 unsigned int fifo_out1 : 1;
701 unsigned int fifo_out1_extra : 1;
702 unsigned int dmc_out0 : 1;
703 unsigned int spu0_intr9 : 1;
704 unsigned int spu1_intr9 : 1;
705 unsigned int trigger_grp1 : 1;
706 unsigned int trigger_grp7 : 1;
707 unsigned int timer_grp1 : 1;
708 unsigned int fifo_in1 : 1;
709 unsigned int fifo_in1_extra : 1;
710 unsigned int dmc_in0 : 1;
711 unsigned int spu0_intr10 : 1;
712 unsigned int spu1_intr10 : 1;
713 unsigned int trigger_grp2 : 1;
714 unsigned int trigger_grp4 : 1;
715 unsigned int timer_grp2 : 1;
716 unsigned int fifo_out0 : 1;
717 unsigned int fifo_out0_extra : 1;
718 unsigned int dmc_out1 : 1;
719 unsigned int spu0_intr11 : 1;
720 unsigned int spu1_intr11 : 1;
721 unsigned int trigger_grp3 : 1;
722 unsigned int trigger_grp5 : 1;
723 unsigned int timer_grp3 : 1;
724 unsigned int fifo_in0 : 1;
725 unsigned int fifo_in0_extra : 1;
726 unsigned int dmc_in1 : 1;
727} reg_iop_sw_mpu_r_masked_intr_grp2;
728#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140
729
730
731typedef struct {
732 unsigned int spu0_intr12 : 1;
733 unsigned int spu1_intr12 : 1;
734 unsigned int trigger_grp0 : 1;
735 unsigned int trigger_grp7 : 1;
736 unsigned int timer_grp0 : 1;
737 unsigned int fifo_in1 : 1;
738 unsigned int fifo_in1_extra : 1;
739 unsigned int dmc_out0 : 1;
740 unsigned int spu0_intr13 : 1;
741 unsigned int spu1_intr13 : 1;
742 unsigned int trigger_grp1 : 1;
743 unsigned int trigger_grp4 : 1;
744 unsigned int timer_grp1 : 1;
745 unsigned int fifo_out0 : 1;
746 unsigned int fifo_out0_extra : 1;
747 unsigned int dmc_in0 : 1;
748 unsigned int spu0_intr14 : 1;
749 unsigned int spu1_intr14 : 1;
750 unsigned int trigger_grp2 : 1;
751 unsigned int trigger_grp5 : 1;
752 unsigned int timer_grp2 : 1;
753 unsigned int fifo_in0 : 1;
754 unsigned int fifo_in0_extra : 1;
755 unsigned int dmc_out1 : 1;
756 unsigned int spu0_intr15 : 1;
757 unsigned int spu1_intr15 : 1;
758 unsigned int trigger_grp3 : 1;
759 unsigned int trigger_grp6 : 1;
760 unsigned int timer_grp3 : 1;
761 unsigned int fifo_out1 : 1;
762 unsigned int fifo_out1_extra : 1;
763 unsigned int dmc_in1 : 1;
764} reg_iop_sw_mpu_rw_intr_grp3_mask;
765#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
766#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
767
768
769typedef struct {
770 unsigned int spu0_intr12 : 1;
771 unsigned int spu1_intr12 : 1;
772 unsigned int dummy1 : 6;
773 unsigned int spu0_intr13 : 1;
774 unsigned int spu1_intr13 : 1;
775 unsigned int dummy2 : 6;
776 unsigned int spu0_intr14 : 1;
777 unsigned int spu1_intr14 : 1;
778 unsigned int dummy3 : 6;
779 unsigned int spu0_intr15 : 1;
780 unsigned int spu1_intr15 : 1;
781 unsigned int dummy4 : 6;
782} reg_iop_sw_mpu_rw_ack_intr_grp3;
783#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
784#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
785
786
787typedef struct {
788 unsigned int spu0_intr12 : 1;
789 unsigned int spu1_intr12 : 1;
790 unsigned int trigger_grp0 : 1;
791 unsigned int trigger_grp7 : 1;
792 unsigned int timer_grp0 : 1;
793 unsigned int fifo_in1 : 1;
794 unsigned int fifo_in1_extra : 1;
795 unsigned int dmc_out0 : 1;
796 unsigned int spu0_intr13 : 1;
797 unsigned int spu1_intr13 : 1;
798 unsigned int trigger_grp1 : 1;
799 unsigned int trigger_grp4 : 1;
800 unsigned int timer_grp1 : 1;
801 unsigned int fifo_out0 : 1;
802 unsigned int fifo_out0_extra : 1;
803 unsigned int dmc_in0 : 1;
804 unsigned int spu0_intr14 : 1;
805 unsigned int spu1_intr14 : 1;
806 unsigned int trigger_grp2 : 1;
807 unsigned int trigger_grp5 : 1;
808 unsigned int timer_grp2 : 1;
809 unsigned int fifo_in0 : 1;
810 unsigned int fifo_in0_extra : 1;
811 unsigned int dmc_out1 : 1;
812 unsigned int spu0_intr15 : 1;
813 unsigned int spu1_intr15 : 1;
814 unsigned int trigger_grp3 : 1;
815 unsigned int trigger_grp6 : 1;
816 unsigned int timer_grp3 : 1;
817 unsigned int fifo_out1 : 1;
818 unsigned int fifo_out1_extra : 1;
819 unsigned int dmc_in1 : 1;
820} reg_iop_sw_mpu_r_intr_grp3;
821#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152
822
823
824typedef struct {
825 unsigned int spu0_intr12 : 1;
826 unsigned int spu1_intr12 : 1;
827 unsigned int trigger_grp0 : 1;
828 unsigned int trigger_grp7 : 1;
829 unsigned int timer_grp0 : 1;
830 unsigned int fifo_in1 : 1;
831 unsigned int fifo_in1_extra : 1;
832 unsigned int dmc_out0 : 1;
833 unsigned int spu0_intr13 : 1;
834 unsigned int spu1_intr13 : 1;
835 unsigned int trigger_grp1 : 1;
836 unsigned int trigger_grp4 : 1;
837 unsigned int timer_grp1 : 1;
838 unsigned int fifo_out0 : 1;
839 unsigned int fifo_out0_extra : 1;
840 unsigned int dmc_in0 : 1;
841 unsigned int spu0_intr14 : 1;
842 unsigned int spu1_intr14 : 1;
843 unsigned int trigger_grp2 : 1;
844 unsigned int trigger_grp5 : 1;
845 unsigned int timer_grp2 : 1;
846 unsigned int fifo_in0 : 1;
847 unsigned int fifo_in0_extra : 1;
848 unsigned int dmc_out1 : 1;
849 unsigned int spu0_intr15 : 1;
850 unsigned int spu1_intr15 : 1;
851 unsigned int trigger_grp3 : 1;
852 unsigned int trigger_grp6 : 1;
853 unsigned int timer_grp3 : 1;
854 unsigned int fifo_out1 : 1;
855 unsigned int fifo_out1_extra : 1;
856 unsigned int dmc_in1 : 1;
857} reg_iop_sw_mpu_r_masked_intr_grp3;
858#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156
859
860
861
862enum {
863 regk_iop_sw_mpu_copy = 0x00000000,
864 regk_iop_sw_mpu_cpu = 0x00000000,
865 regk_iop_sw_mpu_mpu = 0x00000001,
866 regk_iop_sw_mpu_no = 0x00000000,
867 regk_iop_sw_mpu_nop = 0x00000000,
868 regk_iop_sw_mpu_rd = 0x00000002,
869 regk_iop_sw_mpu_reg_copy = 0x00000001,
870 regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000,
871 regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000,
872 regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000,
873 regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000,
874 regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000,
875 regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000,
876 regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000,
877 regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000,
878 regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
879 regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
880 regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
881 regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
882 regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
883 regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
884 regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
885 regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
886 regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
887 regk_iop_sw_mpu_set = 0x00000001,
888 regk_iop_sw_mpu_spu0 = 0x00000002,
889 regk_iop_sw_mpu_spu1 = 0x00000003,
890 regk_iop_sw_mpu_wr = 0x00000003,
891 regk_iop_sw_mpu_yes = 0x00000001
892};
893#endif
894
