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19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29#include <linux/slab.h>
30#include <linux/of.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/of_pci.h>
34#include <linux/export.h>
35
36#include <asm/processor.h>
37#include <linux/io.h>
38#include <asm/pci-bridge.h>
39#include <asm/byteorder.h>
40
41static DEFINE_SPINLOCK(hose_spinlock);
42LIST_HEAD(hose_list);
43
44
45static int global_phb_number;
46
47
48resource_size_t isa_mem_base;
49
50unsigned long isa_io_base;
51EXPORT_SYMBOL(isa_io_base);
52
53static int pci_bus_count;
54
55struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
56{
57 struct pci_controller *phb;
58
59 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
60 if (!phb)
61 return NULL;
62 spin_lock(&hose_spinlock);
63 phb->global_number = global_phb_number++;
64 list_add_tail(&phb->list_node, &hose_list);
65 spin_unlock(&hose_spinlock);
66 phb->dn = dev;
67 phb->is_dynamic = mem_init_done;
68 return phb;
69}
70
71void pcibios_free_controller(struct pci_controller *phb)
72{
73 spin_lock(&hose_spinlock);
74 list_del(&phb->list_node);
75 spin_unlock(&hose_spinlock);
76
77 if (phb->is_dynamic)
78 kfree(phb);
79}
80
81static resource_size_t pcibios_io_size(const struct pci_controller *hose)
82{
83 return resource_size(&hose->io_resource);
84}
85
86int pcibios_vaddr_is_ioport(void __iomem *address)
87{
88 int ret = 0;
89 struct pci_controller *hose;
90 resource_size_t size;
91
92 spin_lock(&hose_spinlock);
93 list_for_each_entry(hose, &hose_list, list_node) {
94 size = pcibios_io_size(hose);
95 if (address >= hose->io_base_virt &&
96 address < (hose->io_base_virt + size)) {
97 ret = 1;
98 break;
99 }
100 }
101 spin_unlock(&hose_spinlock);
102 return ret;
103}
104
105unsigned long pci_address_to_pio(phys_addr_t address)
106{
107 struct pci_controller *hose;
108 resource_size_t size;
109 unsigned long ret = ~0;
110
111 spin_lock(&hose_spinlock);
112 list_for_each_entry(hose, &hose_list, list_node) {
113 size = pcibios_io_size(hose);
114 if (address >= hose->io_base_phys &&
115 address < (hose->io_base_phys + size)) {
116 unsigned long base =
117 (unsigned long)hose->io_base_virt - _IO_BASE;
118 ret = base + (address - hose->io_base_phys);
119 break;
120 }
121 }
122 spin_unlock(&hose_spinlock);
123
124 return ret;
125}
126EXPORT_SYMBOL_GPL(pci_address_to_pio);
127
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132
133
134
135struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
136{
137 while (node) {
138 struct pci_controller *hose, *tmp;
139 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
140 if (hose->dn == node)
141 return hose;
142 node = node->parent;
143 }
144 return NULL;
145}
146
147void pcibios_set_master(struct pci_dev *dev)
148{
149
150}
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168
169static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
170 resource_size_t *offset,
171 enum pci_mmap_state mmap_state)
172{
173 struct pci_controller *hose = pci_bus_to_host(dev->bus);
174 unsigned long io_offset = 0;
175 int i, res_bit;
176
177 if (!hose)
178 return NULL;
179
180
181 if (mmap_state == pci_mmap_mem) {
182#if 0
183 *offset += hose->pci_mem_offset;
184#endif
185 res_bit = IORESOURCE_MEM;
186 } else {
187 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
188 *offset += io_offset;
189 res_bit = IORESOURCE_IO;
190 }
191
192
193
194
195
196 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
197 struct resource *rp = &dev->resource[i];
198 int flags = rp->flags;
199
200
201 if (i == PCI_ROM_RESOURCE)
202 flags |= IORESOURCE_MEM;
203
204
205 if ((flags & res_bit) == 0)
206 continue;
207
208
209 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
210 continue;
211
212
213 if (mmap_state == pci_mmap_io)
214 *offset += hose->io_base_phys - io_offset;
215 return rp;
216 }
217
218 return NULL;
219}
220
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224
225
226pgprot_t pci_phys_mem_access_prot(struct file *file,
227 unsigned long pfn,
228 unsigned long size,
229 pgprot_t prot)
230{
231 struct pci_dev *pdev = NULL;
232 struct resource *found = NULL;
233 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
234 int i;
235
236 if (page_is_ram(pfn))
237 return prot;
238
239 prot = pgprot_noncached(prot);
240 for_each_pci_dev(pdev) {
241 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
242 struct resource *rp = &pdev->resource[i];
243 int flags = rp->flags;
244
245
246 if ((flags & IORESOURCE_MEM) == 0)
247 continue;
248
249 if (offset < (rp->start & PAGE_MASK) ||
250 offset > rp->end)
251 continue;
252 found = rp;
253 break;
254 }
255 if (found)
256 break;
257 }
258 if (found) {
259 if (found->flags & IORESOURCE_PREFETCH)
260 prot = pgprot_noncached_wc(prot);
261 pci_dev_put(pdev);
262 }
263
264 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
265 (unsigned long long)offset, pgprot_val(prot));
266
267 return prot;
268}
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279
280int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
281 enum pci_mmap_state mmap_state, int write_combine)
282{
283 resource_size_t offset =
284 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
285 struct resource *rp;
286 int ret;
287
288 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
289 if (rp == NULL)
290 return -EINVAL;
291
292 vma->vm_pgoff = offset >> PAGE_SHIFT;
293 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
294
295 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
296 vma->vm_end - vma->vm_start, vma->vm_page_prot);
297
298 return ret;
299}
300
301
302int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
303{
304 unsigned long offset;
305 struct pci_controller *hose = pci_bus_to_host(bus);
306 struct resource *rp = &hose->io_resource;
307 void __iomem *addr;
308
309
310
311
312
313
314 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
315 offset += port;
316
317 if (!(rp->flags & IORESOURCE_IO))
318 return -ENXIO;
319 if (offset < rp->start || (offset + size) > rp->end)
320 return -ENXIO;
321 addr = hose->io_base_virt + port;
322
323 switch (size) {
324 case 1:
325 *((u8 *)val) = in_8(addr);
326 return 1;
327 case 2:
328 if (port & 1)
329 return -EINVAL;
330 *((u16 *)val) = in_le16(addr);
331 return 2;
332 case 4:
333 if (port & 3)
334 return -EINVAL;
335 *((u32 *)val) = in_le32(addr);
336 return 4;
337 }
338 return -EINVAL;
339}
340
341
342int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
343{
344 unsigned long offset;
345 struct pci_controller *hose = pci_bus_to_host(bus);
346 struct resource *rp = &hose->io_resource;
347 void __iomem *addr;
348
349
350
351
352
353
354 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
355 offset += port;
356
357 if (!(rp->flags & IORESOURCE_IO))
358 return -ENXIO;
359 if (offset < rp->start || (offset + size) > rp->end)
360 return -ENXIO;
361 addr = hose->io_base_virt + port;
362
363
364
365
366
367
368 switch (size) {
369 case 1:
370 out_8(addr, val >> 24);
371 return 1;
372 case 2:
373 if (port & 1)
374 return -EINVAL;
375 out_le16(addr, val >> 16);
376 return 2;
377 case 4:
378 if (port & 3)
379 return -EINVAL;
380 out_le32(addr, val);
381 return 4;
382 }
383 return -EINVAL;
384}
385
386
387int pci_mmap_legacy_page_range(struct pci_bus *bus,
388 struct vm_area_struct *vma,
389 enum pci_mmap_state mmap_state)
390{
391 struct pci_controller *hose = pci_bus_to_host(bus);
392 resource_size_t offset =
393 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
394 resource_size_t size = vma->vm_end - vma->vm_start;
395 struct resource *rp;
396
397 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
398 pci_domain_nr(bus), bus->number,
399 mmap_state == pci_mmap_mem ? "MEM" : "IO",
400 (unsigned long long)offset,
401 (unsigned long long)(offset + size - 1));
402
403 if (mmap_state == pci_mmap_mem) {
404
405
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409
410
411 if ((offset + size) > hose->isa_mem_size) {
412#ifdef CONFIG_MMU
413 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
414 current->comm, current->pid);
415 pr_debug("legacy memory for 0%04x:%02x\n",
416 pci_domain_nr(bus), bus->number);
417#endif
418 if (vma->vm_flags & VM_SHARED)
419 return shmem_zero_setup(vma);
420 return 0;
421 }
422 offset += hose->isa_mem_phys;
423 } else {
424 unsigned long io_offset = (unsigned long)hose->io_base_virt -
425 _IO_BASE;
426 unsigned long roffset = offset + io_offset;
427 rp = &hose->io_resource;
428 if (!(rp->flags & IORESOURCE_IO))
429 return -ENXIO;
430 if (roffset < rp->start || (roffset + size) > rp->end)
431 return -ENXIO;
432 offset += hose->io_base_phys;
433 }
434 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
435
436 vma->vm_pgoff = offset >> PAGE_SHIFT;
437 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
438 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
439 vma->vm_end - vma->vm_start,
440 vma->vm_page_prot);
441}
442
443void pci_resource_to_user(const struct pci_dev *dev, int bar,
444 const struct resource *rsrc,
445 resource_size_t *start, resource_size_t *end)
446{
447 struct pci_bus_region region;
448
449 if (rsrc->flags & IORESOURCE_IO) {
450 pcibios_resource_to_bus(dev->bus, ®ion,
451 (struct resource *) rsrc);
452 *start = region.start;
453 *end = region.end;
454 return;
455 }
456
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459
460
461
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463
464 *start = rsrc->start;
465 *end = rsrc->end;
466}
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501void pci_process_bridge_OF_ranges(struct pci_controller *hose,
502 struct device_node *dev, int primary)
503{
504 int memno = 0, isa_hole = -1;
505 unsigned long long isa_mb = 0;
506 struct resource *res;
507 struct of_pci_range range;
508 struct of_pci_range_parser parser;
509
510 pr_info("PCI host bridge %s %s ranges:\n",
511 dev->full_name, primary ? "(primary)" : "");
512
513
514 if (of_pci_range_parser_init(&parser, dev))
515 return;
516
517 pr_debug("Parsing ranges property...\n");
518 for_each_of_pci_range(&parser, &range) {
519
520 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
521 range.pci_space, range.pci_addr);
522 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
523 range.cpu_addr, range.size);
524
525
526
527
528
529
530 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
531 continue;
532
533
534 res = NULL;
535 switch (range.flags & IORESOURCE_TYPE_BITS) {
536 case IORESOURCE_IO:
537 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
538 range.cpu_addr, range.cpu_addr + range.size - 1,
539 range.pci_addr);
540
541
542 if (hose->pci_io_size) {
543 pr_info(" \\--> Skipped (too many) !\n");
544 continue;
545 }
546
547 if (range.size > 0x01000000)
548 range.size = 0x01000000;
549
550
551 hose->io_base_virt = ioremap(range.cpu_addr,
552 range.size);
553
554
555 if (primary)
556 isa_io_base =
557 (unsigned long)hose->io_base_virt;
558
559
560
561 hose->pci_io_size = range.pci_addr + range.size;
562 hose->io_base_phys = range.cpu_addr - range.pci_addr;
563
564
565 res = &hose->io_resource;
566 range.cpu_addr = range.pci_addr;
567
568 break;
569 case IORESOURCE_MEM:
570 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
571 range.cpu_addr, range.cpu_addr + range.size - 1,
572 range.pci_addr,
573 (range.pci_space & 0x40000000) ?
574 "Prefetch" : "");
575
576
577 if (memno >= 3) {
578 pr_info(" \\--> Skipped (too many) !\n");
579 continue;
580 }
581
582 if (range.pci_addr == 0) {
583 isa_mb = range.cpu_addr;
584 isa_hole = memno;
585 if (primary || isa_mem_base == 0)
586 isa_mem_base = range.cpu_addr;
587 hose->isa_mem_phys = range.cpu_addr;
588 hose->isa_mem_size = range.size;
589 }
590
591
592
593
594
595 if (memno == 0 ||
596 (isa_hole >= 0 && range.pci_addr != 0 &&
597 hose->pci_mem_offset == isa_mb))
598 hose->pci_mem_offset = range.cpu_addr -
599 range.pci_addr;
600 else if (range.pci_addr != 0 &&
601 hose->pci_mem_offset != range.cpu_addr -
602 range.pci_addr) {
603 pr_info(" \\--> Skipped (offset mismatch) !\n");
604 continue;
605 }
606
607
608 res = &hose->mem_resources[memno++];
609 break;
610 }
611 if (res != NULL) {
612 res->name = dev->full_name;
613 res->flags = range.flags;
614 res->start = range.cpu_addr;
615 res->end = range.cpu_addr + range.size - 1;
616 res->parent = res->child = res->sibling = NULL;
617 }
618 }
619
620
621
622
623
624 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
625 unsigned int next = isa_hole + 1;
626 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
627 if (next < memno)
628 memmove(&hose->mem_resources[isa_hole],
629 &hose->mem_resources[next],
630 sizeof(struct resource) * (memno - next));
631 hose->mem_resources[--memno].flags = 0;
632 }
633}
634
635
636int pci_proc_domain(struct pci_bus *bus)
637{
638 return pci_domain_nr(bus);
639}
640
641
642
643
644static void pcibios_fixup_resources(struct pci_dev *dev)
645{
646 struct pci_controller *hose = pci_bus_to_host(dev->bus);
647 int i;
648
649 if (!hose) {
650 pr_err("No host bridge for PCI dev %s !\n",
651 pci_name(dev));
652 return;
653 }
654 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
655 struct resource *res = dev->resource + i;
656 if (!res->flags)
657 continue;
658 if (res->start == 0) {
659 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
660 pci_name(dev), i,
661 (unsigned long long)res->start,
662 (unsigned long long)res->end,
663 (unsigned int)res->flags);
664 pr_debug("is unassigned\n");
665 res->end -= res->start;
666 res->start = 0;
667 res->flags |= IORESOURCE_UNSET;
668 continue;
669 }
670
671 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
672 pci_name(dev), i,
673 (unsigned long long)res->start,
674 (unsigned long long)res->end,
675 (unsigned int)res->flags);
676 }
677}
678DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
679
680
681
682
683
684
685static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
686 struct resource *res)
687{
688 struct pci_controller *hose = pci_bus_to_host(bus);
689 struct pci_dev *dev = bus->self;
690 resource_size_t offset;
691 u16 command;
692 int i;
693
694
695 if (res->flags & IORESOURCE_MEM) {
696
697
698
699 if (res->start != hose->pci_mem_offset)
700 return 0;
701
702
703
704
705 pci_read_config_word(dev, PCI_COMMAND, &command);
706 if ((command & PCI_COMMAND_MEMORY) == 0)
707 return 1;
708
709
710
711
712
713 for (i = 0; i < 3; i++) {
714 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
715 hose->mem_resources[i].start == hose->pci_mem_offset)
716 return 0;
717 }
718
719
720
721
722 return 1;
723 } else {
724
725 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
726 if (((res->start - offset) & 0xfffffffful) != 0)
727 return 0;
728
729
730
731
732
733
734
735 pci_read_config_word(dev, PCI_COMMAND, &command);
736 if (command & PCI_COMMAND_IO)
737 return 0;
738
739
740
741
742 return 1;
743 }
744}
745
746
747static void pcibios_fixup_bridge(struct pci_bus *bus)
748{
749 struct resource *res;
750 int i;
751
752 struct pci_dev *dev = bus->self;
753
754 pci_bus_for_each_resource(bus, res, i) {
755 if (!res)
756 continue;
757 if (!res->flags)
758 continue;
759 if (i >= 3 && bus->self->transparent)
760 continue;
761
762 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
763 pci_name(dev), i,
764 (unsigned long long)res->start,
765 (unsigned long long)res->end,
766 (unsigned int)res->flags);
767
768
769
770
771 if (pcibios_uninitialized_bridge_resource(bus, res)) {
772 res->flags = 0;
773 pr_debug("PCI:%s (unassigned)\n",
774 pci_name(dev));
775 } else {
776 pr_debug("PCI:%s %016llx-%016llx\n",
777 pci_name(dev),
778 (unsigned long long)res->start,
779 (unsigned long long)res->end);
780 }
781 }
782}
783
784void pcibios_setup_bus_self(struct pci_bus *bus)
785{
786
787 if (bus->self != NULL)
788 pcibios_fixup_bridge(bus);
789}
790
791void pcibios_setup_bus_devices(struct pci_bus *bus)
792{
793 struct pci_dev *dev;
794
795 pr_debug("PCI: Fixup bus devices %d (%s)\n",
796 bus->number, bus->self ? pci_name(bus->self) : "PHB");
797
798 list_for_each_entry(dev, &bus->devices, bus_list) {
799
800 dev->dev.of_node = pci_device_to_OF_node(dev);
801
802
803
804
805 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
806
807
808 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
809 }
810}
811
812void pcibios_fixup_bus(struct pci_bus *bus)
813{
814
815}
816EXPORT_SYMBOL(pcibios_fixup_bus);
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830
831resource_size_t pcibios_align_resource(void *data, const struct resource *res,
832 resource_size_t size, resource_size_t align)
833{
834 return res->start;
835}
836EXPORT_SYMBOL(pcibios_align_resource);
837
838int pcibios_add_device(struct pci_dev *dev)
839{
840 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
841
842 return 0;
843}
844EXPORT_SYMBOL(pcibios_add_device);
845
846
847
848
849
850static int __init reparent_resources(struct resource *parent,
851 struct resource *res)
852{
853 struct resource *p, **pp;
854 struct resource **firstpp = NULL;
855
856 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
857 if (p->end < res->start)
858 continue;
859 if (res->end < p->start)
860 break;
861 if (p->start < res->start || p->end > res->end)
862 return -1;
863 if (firstpp == NULL)
864 firstpp = pp;
865 }
866 if (firstpp == NULL)
867 return -1;
868 res->parent = parent;
869 res->child = *firstpp;
870 res->sibling = *pp;
871 *firstpp = res;
872 *pp = NULL;
873 for (p = res->child; p != NULL; p = p->sibling) {
874 p->parent = res;
875 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
876 p->name,
877 (unsigned long long)p->start,
878 (unsigned long long)p->end, res->name);
879 }
880 return 0;
881}
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912
913
914
915
916static void pcibios_allocate_bus_resources(struct pci_bus *bus)
917{
918 struct pci_bus *b;
919 int i;
920 struct resource *res, *pr;
921
922 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
923 pci_domain_nr(bus), bus->number);
924
925 pci_bus_for_each_resource(bus, res, i) {
926 if (!res || !res->flags
927 || res->start > res->end || res->parent)
928 continue;
929 if (bus->parent == NULL)
930 pr = (res->flags & IORESOURCE_IO) ?
931 &ioport_resource : &iomem_resource;
932 else {
933
934
935
936
937
938
939 pr = pci_find_parent_resource(bus->self, res);
940 if (pr == res) {
941
942
943
944
945 continue;
946 }
947 }
948
949 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
950 bus->self ? pci_name(bus->self) : "PHB",
951 bus->number, i,
952 (unsigned long long)res->start,
953 (unsigned long long)res->end);
954 pr_debug("[0x%x], parent %p (%s)\n",
955 (unsigned int)res->flags,
956 pr, (pr && pr->name) ? pr->name : "nil");
957
958 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
959 struct pci_dev *dev = bus->self;
960
961 if (request_resource(pr, res) == 0)
962 continue;
963
964
965
966
967
968 if (reparent_resources(pr, res) == 0)
969 continue;
970
971 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
972 pci_claim_bridge_resource(dev,
973 i + PCI_BRIDGE_RESOURCES) == 0)
974 continue;
975
976 }
977 pr_warn("PCI: Cannot allocate resource region ");
978 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
979 res->start = res->end = 0;
980 res->flags = 0;
981 }
982
983 list_for_each_entry(b, &bus->children, node)
984 pcibios_allocate_bus_resources(b);
985}
986
987static inline void alloc_resource(struct pci_dev *dev, int idx)
988{
989 struct resource *pr, *r = &dev->resource[idx];
990
991 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
992 pci_name(dev), idx,
993 (unsigned long long)r->start,
994 (unsigned long long)r->end,
995 (unsigned int)r->flags);
996
997 pr = pci_find_parent_resource(dev, r);
998 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
999 request_resource(pr, r) < 0) {
1000 pr_warn("PCI: Cannot allocate resource region %d ", idx);
1001 pr_cont("of device %s, will remap\n", pci_name(dev));
1002 if (pr)
1003 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1004 pr,
1005 (unsigned long long)pr->start,
1006 (unsigned long long)pr->end,
1007 (unsigned int)pr->flags);
1008
1009 r->flags |= IORESOURCE_UNSET;
1010 r->end -= r->start;
1011 r->start = 0;
1012 }
1013}
1014
1015static void __init pcibios_allocate_resources(int pass)
1016{
1017 struct pci_dev *dev = NULL;
1018 int idx, disabled;
1019 u16 command;
1020 struct resource *r;
1021
1022 for_each_pci_dev(dev) {
1023 pci_read_config_word(dev, PCI_COMMAND, &command);
1024 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1025 r = &dev->resource[idx];
1026 if (r->parent)
1027 continue;
1028 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1029 continue;
1030
1031
1032
1033 if (idx == PCI_ROM_RESOURCE)
1034 disabled = 1;
1035 if (r->flags & IORESOURCE_IO)
1036 disabled = !(command & PCI_COMMAND_IO);
1037 else
1038 disabled = !(command & PCI_COMMAND_MEMORY);
1039 if (pass == disabled)
1040 alloc_resource(dev, idx);
1041 }
1042 if (pass)
1043 continue;
1044 r = &dev->resource[PCI_ROM_RESOURCE];
1045 if (r->flags) {
1046
1047
1048
1049 u32 reg;
1050 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1051 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1052 pr_debug("PCI: Switching off ROM of %s\n",
1053 pci_name(dev));
1054 r->flags &= ~IORESOURCE_ROM_ENABLE;
1055 pci_write_config_dword(dev, dev->rom_base_reg,
1056 reg & ~PCI_ROM_ADDRESS_ENABLE);
1057 }
1058 }
1059 }
1060}
1061
1062static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1063{
1064 struct pci_controller *hose = pci_bus_to_host(bus);
1065 resource_size_t offset;
1066 struct resource *res, *pres;
1067 int i;
1068
1069 pr_debug("Reserving legacy ranges for domain %04x\n",
1070 pci_domain_nr(bus));
1071
1072
1073 if (!(hose->io_resource.flags & IORESOURCE_IO))
1074 goto no_io;
1075 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1076 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1077 BUG_ON(res == NULL);
1078 res->name = "Legacy IO";
1079 res->flags = IORESOURCE_IO;
1080 res->start = offset;
1081 res->end = (offset + 0xfff) & 0xfffffffful;
1082 pr_debug("Candidate legacy IO: %pR\n", res);
1083 if (request_resource(&hose->io_resource, res)) {
1084 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1085 pci_domain_nr(bus), bus->number, res);
1086 kfree(res);
1087 }
1088
1089 no_io:
1090
1091 offset = hose->pci_mem_offset;
1092 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1093 for (i = 0; i < 3; i++) {
1094 pres = &hose->mem_resources[i];
1095 if (!(pres->flags & IORESOURCE_MEM))
1096 continue;
1097 pr_debug("hose mem res: %pR\n", pres);
1098 if ((pres->start - offset) <= 0xa0000 &&
1099 (pres->end - offset) >= 0xbffff)
1100 break;
1101 }
1102 if (i >= 3)
1103 return;
1104 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1105 BUG_ON(res == NULL);
1106 res->name = "Legacy VGA memory";
1107 res->flags = IORESOURCE_MEM;
1108 res->start = 0xa0000 + offset;
1109 res->end = 0xbffff + offset;
1110 pr_debug("Candidate VGA memory: %pR\n", res);
1111 if (request_resource(pres, res)) {
1112 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1113 pci_domain_nr(bus), bus->number, res);
1114 kfree(res);
1115 }
1116}
1117
1118void __init pcibios_resource_survey(void)
1119{
1120 struct pci_bus *b;
1121
1122
1123
1124
1125 list_for_each_entry(b, &pci_root_buses, node)
1126 pcibios_allocate_bus_resources(b);
1127
1128 pcibios_allocate_resources(0);
1129 pcibios_allocate_resources(1);
1130
1131
1132
1133
1134
1135 list_for_each_entry(b, &pci_root_buses, node)
1136 pcibios_reserve_legacy_regions(b);
1137
1138
1139 pr_debug("PCI: Assigning unassigned resources...\n");
1140 pci_assign_unassigned_resources();
1141}
1142
1143
1144
1145
1146
1147
1148void pcibios_claim_one_bus(struct pci_bus *bus)
1149{
1150 struct pci_dev *dev;
1151 struct pci_bus *child_bus;
1152
1153 list_for_each_entry(dev, &bus->devices, bus_list) {
1154 int i;
1155
1156 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1157 struct resource *r = &dev->resource[i];
1158
1159 if (r->parent || !r->start || !r->flags)
1160 continue;
1161
1162 pr_debug("PCI: Claiming %s: ", pci_name(dev));
1163 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1164 i, (unsigned long long)r->start,
1165 (unsigned long long)r->end,
1166 (unsigned int)r->flags);
1167
1168 if (pci_claim_resource(dev, i) == 0)
1169 continue;
1170
1171 pci_claim_bridge_resource(dev, i);
1172 }
1173 }
1174
1175 list_for_each_entry(child_bus, &bus->children, node)
1176 pcibios_claim_one_bus(child_bus);
1177}
1178EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1179
1180
1181
1182
1183
1184
1185
1186
1187void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1188{
1189 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1190 pci_domain_nr(bus), bus->number);
1191
1192
1193 pcibios_allocate_bus_resources(bus);
1194 pcibios_claim_one_bus(bus);
1195
1196
1197 pci_bus_add_devices(bus);
1198
1199
1200
1201}
1202EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1203
1204static void pcibios_setup_phb_resources(struct pci_controller *hose,
1205 struct list_head *resources)
1206{
1207 unsigned long io_offset;
1208 struct resource *res;
1209 int i;
1210
1211
1212 res = &hose->io_resource;
1213
1214
1215 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1216 res->start = (res->start + io_offset) & 0xffffffffu;
1217 res->end = (res->end + io_offset) & 0xffffffffu;
1218
1219 if (!res->flags) {
1220 pr_warn("PCI: I/O resource not set for host ");
1221 pr_cont("bridge %s (domain %d)\n",
1222 hose->dn->full_name, hose->global_number);
1223
1224 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1225 res->end = res->start + IO_SPACE_LIMIT;
1226 res->flags = IORESOURCE_IO;
1227 }
1228 pci_add_resource_offset(resources, res,
1229 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1230
1231 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1232 (unsigned long long)res->start,
1233 (unsigned long long)res->end,
1234 (unsigned long)res->flags);
1235
1236
1237 for (i = 0; i < 3; ++i) {
1238 res = &hose->mem_resources[i];
1239 if (!res->flags) {
1240 if (i > 0)
1241 continue;
1242 pr_err("PCI: Memory resource 0 not set for ");
1243 pr_cont("host bridge %s (domain %d)\n",
1244 hose->dn->full_name, hose->global_number);
1245
1246
1247 res->start = hose->pci_mem_offset;
1248 res->end = (resource_size_t)-1LL;
1249 res->flags = IORESOURCE_MEM;
1250
1251 }
1252 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1253
1254 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1255 i, (unsigned long long)res->start,
1256 (unsigned long long)res->end,
1257 (unsigned long)res->flags);
1258 }
1259
1260 pr_debug("PCI: PHB MEM offset = %016llx\n",
1261 (unsigned long long)hose->pci_mem_offset);
1262 pr_debug("PCI: PHB IO offset = %08lx\n",
1263 (unsigned long)hose->io_base_virt - _IO_BASE);
1264}
1265
1266static void pcibios_scan_phb(struct pci_controller *hose)
1267{
1268 LIST_HEAD(resources);
1269 struct pci_bus *bus;
1270 struct device_node *node = hose->dn;
1271
1272 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1273
1274 pcibios_setup_phb_resources(hose, &resources);
1275
1276 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1277 hose->ops, hose, &resources);
1278 if (bus == NULL) {
1279 pr_err("Failed to create bus for PCI domain %04x\n",
1280 hose->global_number);
1281 pci_free_resource_list(&resources);
1282 return;
1283 }
1284 bus->busn_res.start = hose->first_busno;
1285 hose->bus = bus;
1286
1287 hose->last_busno = bus->busn_res.end;
1288}
1289
1290static int __init pcibios_init(void)
1291{
1292 struct pci_controller *hose, *tmp;
1293 int next_busno = 0;
1294
1295 pr_info("PCI: Probing PCI hardware\n");
1296
1297
1298 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1299 hose->last_busno = 0xff;
1300 pcibios_scan_phb(hose);
1301 if (next_busno <= hose->last_busno)
1302 next_busno = hose->last_busno + 1;
1303 }
1304 pci_bus_count = next_busno;
1305
1306
1307 pcibios_resource_survey();
1308 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1309 if (hose->bus)
1310 pci_bus_add_devices(hose->bus);
1311 }
1312
1313 return 0;
1314}
1315
1316subsys_initcall(pcibios_init);
1317
1318static struct pci_controller *pci_bus_to_hose(int bus)
1319{
1320 struct pci_controller *hose, *tmp;
1321
1322 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1323 if (bus >= hose->first_busno && bus <= hose->last_busno)
1324 return hose;
1325 return NULL;
1326}
1327
1328
1329
1330
1331
1332
1333
1334long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1335{
1336 struct pci_controller *hose;
1337 long result = -EOPNOTSUPP;
1338
1339 hose = pci_bus_to_hose(bus);
1340 if (!hose)
1341 return -ENODEV;
1342
1343 switch (which) {
1344 case IOBASE_BRIDGE_NUMBER:
1345 return (long)hose->first_busno;
1346 case IOBASE_MEMORY:
1347 return (long)hose->pci_mem_offset;
1348 case IOBASE_IO:
1349 return (long)hose->io_base_phys;
1350 case IOBASE_ISA_IO:
1351 return (long)isa_io_base;
1352 case IOBASE_ISA_MEM:
1353 return (long)isa_mem_base;
1354 }
1355
1356 return result;
1357}
1358
1359
1360
1361
1362
1363#define NULL_PCI_OP(rw, size, type) \
1364static int \
1365null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1366{ \
1367 return PCIBIOS_DEVICE_NOT_FOUND; \
1368}
1369
1370static int
1371null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1372 int len, u32 *val)
1373{
1374 return PCIBIOS_DEVICE_NOT_FOUND;
1375}
1376
1377static int
1378null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1379 int len, u32 val)
1380{
1381 return PCIBIOS_DEVICE_NOT_FOUND;
1382}
1383
1384static struct pci_ops null_pci_ops = {
1385 .read = null_read_config,
1386 .write = null_write_config,
1387};
1388
1389
1390
1391
1392
1393static struct pci_bus *
1394fake_pci_bus(struct pci_controller *hose, int busnr)
1395{
1396 static struct pci_bus bus;
1397
1398 if (!hose)
1399 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1400
1401 bus.number = busnr;
1402 bus.sysdata = hose;
1403 bus.ops = hose ? hose->ops : &null_pci_ops;
1404 return &bus;
1405}
1406
1407#define EARLY_PCI_OP(rw, size, type) \
1408int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1409 int devfn, int offset, type value) \
1410{ \
1411 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1412 devfn, offset, value); \
1413}
1414
1415EARLY_PCI_OP(read, byte, u8 *)
1416EARLY_PCI_OP(read, word, u16 *)
1417EARLY_PCI_OP(read, dword, u32 *)
1418EARLY_PCI_OP(write, byte, u8)
1419EARLY_PCI_OP(write, word, u16)
1420EARLY_PCI_OP(write, dword, u32)
1421
1422int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1423 int cap)
1424{
1425 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1426}
1427
1428