LXR linux/arch/mips/kernel/smp-cmp.c

   1/*
   2 *  This program is free software; you can distribute it and/or modify it
   3 *  under the terms of the GNU General Public License (Version 2) as
   4 *  published by the Free Software Foundation.
   5 *
   6 *  This program is distributed in the hope it will be useful, but WITHOUT
   7 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   8 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   9 *  for more details.
  10 *
  11 *  You should have received a copy of the GNU General Public License along
  12 *  with this program; if not, write to the Free Software Foundation, Inc.,
  13 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  14 *
  15 * Copyright (C) 2007 MIPS Technologies, Inc.
  16 *    Chris Dearman (chris@mips.com)
  17 */
  18
  19#undef DEBUG
  20
  21#include <linux/kernel.h>
  22#include <linux/sched.h>
  23#include <linux/smp.h>
  24#include <linux/cpumask.h>
  25#include <linux/interrupt.h>
  26#include <linux/compiler.h>
  27#include <linux/irqchip/mips-gic.h>
  28
  29#include <linux/atomic.h>
  30#include <asm/cacheflush.h>
  31#include <asm/cpu.h>
  32#include <asm/processor.h>
  33#include <asm/hardirq.h>
  34#include <asm/mmu_context.h>
  35#include <asm/smp.h>
  36#include <asm/time.h>
  37#include <asm/mipsregs.h>
  38#include <asm/mipsmtregs.h>
  39#include <asm/mips_mt.h>
  40#include <asm/amon.h>
  41
  42static void cmp_init_secondary(void)
  43{
  44        struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;
  45
  46        /* Assume GIC is present */
  47        change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
  48                                 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
  49
  50        /* Enable per-cpu interrupts: platform specific */
  51
  52#ifdef CONFIG_MIPS_MT_SMP
  53        if (cpu_has_mipsmt)
  54                c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
  55                        TCBIND_CURVPE;
  56#endif
  57}
  58
  59static void cmp_smp_finish(void)
  60{
  61        pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
  62
  63        /* CDFIXME: remove this? */
  64        write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
  65
  66#ifdef CONFIG_MIPS_MT_FPAFF
  67        /* If we have an FPU, enroll ourselves in the FPU-full mask */
  68        if (cpu_has_fpu)
  69                cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
  70#endif /* CONFIG_MIPS_MT_FPAFF */
  71
  72        local_irq_enable();
  73}
  74
  75/*
  76 * Setup the PC, SP, and GP of a secondary processor and start it running
  77 * smp_bootstrap is the place to resume from
  78 * __KSTK_TOS(idle) is apparently the stack pointer
  79 * (unsigned long)idle->thread_info the gp
  80 */
  81static void cmp_boot_secondary(int cpu, struct task_struct *idle)
  82{
  83        struct thread_info *gp = task_thread_info(idle);
  84        unsigned long sp = __KSTK_TOS(idle);
  85        unsigned long pc = (unsigned long)&smp_bootstrap;
  86        unsigned long a0 = 0;
  87
  88        pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
  89                __func__, cpu);
  90
  91#if 0
  92        /* Needed? */
  93        flush_icache_range((unsigned long)gp,
  94                           (unsigned long)(gp + sizeof(struct thread_info)));
  95#endif
  96
  97        amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
  98}
  99
 100/*
 101 * Common setup before any secondaries are started
 102 */
 103void __init cmp_smp_setup(void)
 104{
 105        int i;
 106        int ncpu = 0;
 107
 108        pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
 109
 110#ifdef CONFIG_MIPS_MT_FPAFF
 111        /* If we have an FPU, enroll ourselves in the FPU-full mask */
 112        if (cpu_has_fpu)
 113                cpumask_set_cpu(0, &mt_fpu_cpumask);
 114#endif /* CONFIG_MIPS_MT_FPAFF */
 115
 116        for (i = 1; i < NR_CPUS; i++) {
 117                if (amon_cpu_avail(i)) {
 118                        set_cpu_possible(i, true);
 119                        __cpu_number_map[i]     = ++ncpu;
 120                        __cpu_logical_map[ncpu] = i;
 121                }
 122        }
 123
 124        if (cpu_has_mipsmt) {
 125                unsigned int nvpe = 1;
 126#ifdef CONFIG_MIPS_MT_SMP
 127                unsigned int mvpconf0 = read_c0_mvpconf0();
 128
 129                nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
 130#endif
 131                smp_num_siblings = nvpe;
 132        }
 133        pr_info("Detected %i available secondary CPU(s)\n", ncpu);
 134}
 135
 136void __init cmp_prepare_cpus(unsigned int max_cpus)
 137{
 138        pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
 139                 smp_processor_id(), __func__, max_cpus);
 140
 141#ifdef CONFIG_MIPS_MT
 142        /*
 143         * FIXME: some of these options are per-system, some per-core and
 144         * some per-cpu
 145         */
 146        mips_mt_set_cpuoptions();
 147#endif
 148
 149}
 150
 151struct plat_smp_ops cmp_smp_ops = {
 152        .send_ipi_single        = mips_smp_send_ipi_single,
 153        .send_ipi_mask          = mips_smp_send_ipi_mask,
 154        .init_secondary         = cmp_init_secondary,
 155        .smp_finish             = cmp_smp_finish,
 156        .boot_secondary         = cmp_boot_secondary,
 157        .smp_setup              = cmp_smp_setup,
 158        .prepare_cpus           = cmp_prepare_cpus,
 159};
 160