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8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14#include <linux/platform_device.h>
15#include <linux/swiotlb.h>
16
17#include <asm/time.h>
18
19#include <asm/octeon/octeon.h>
20#include <asm/octeon/cvmx-npi-defs.h>
21#include <asm/octeon/cvmx-pci-defs.h>
22#include <asm/octeon/pci-octeon.h>
23
24#include <dma-coherence.h>
25
26#define USE_OCTEON_INTERNAL_ARBITER
27
28
29
30
31
32
33#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
34#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
35
36
37#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
38
39u64 octeon_bar1_pci_phys;
40
41
42
43
44union octeon_pci_address {
45 uint64_t u64;
46 struct {
47 uint64_t upper:2;
48 uint64_t reserved:13;
49 uint64_t io:1;
50 uint64_t did:5;
51 uint64_t subdid:3;
52 uint64_t reserved2:4;
53 uint64_t endian_swap:2;
54 uint64_t reserved3:10;
55 uint64_t bus:8;
56 uint64_t dev:5;
57 uint64_t func:3;
58 uint64_t reg:8;
59 } s;
60};
61
62int __initconst (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
63 u8 slot, u8 pin);
64enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
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76
77int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
78{
79 if (octeon_pcibios_map_irq)
80 return octeon_pcibios_map_irq(dev, slot, pin);
81 else
82 panic("octeon_pcibios_map_irq not set.");
83}
84
85
86
87
88
89int pcibios_plat_dev_init(struct pci_dev *dev)
90{
91 uint16_t config;
92 uint32_t dconfig;
93 int pos;
94
95
96
97
98
99
100
101 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
102
103 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
104
105
106
107 pci_read_config_word(dev, PCI_COMMAND, &config);
108 config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
109 pci_write_config_word(dev, PCI_COMMAND, config);
110
111 if (dev->subordinate) {
112
113 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
114
115 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
116 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
117 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
118 }
119
120
121 config = PCI_EXP_DEVCTL_CERE;
122 config |= PCI_EXP_DEVCTL_NFERE;
123 config |= PCI_EXP_DEVCTL_FERE;
124 config |= PCI_EXP_DEVCTL_URRE;
125 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
126
127
128 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
129 if (pos) {
130
131 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
132 &dconfig);
133 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
134 dconfig);
135
136
137 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
138
139
140
141
142
143
144
145 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
146 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
147
148
149 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
150
151 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
152
153 if (config & PCI_ERR_CAP_ECRC_GENC)
154 config |= PCI_ERR_CAP_ECRC_GENE;
155
156 if (config & PCI_ERR_CAP_ECRC_CHKC)
157 config |= PCI_ERR_CAP_ECRC_CHKE;
158 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
159
160
161 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
162 PCI_ERR_ROOT_CMD_COR_EN |
163 PCI_ERR_ROOT_CMD_NONFATAL_EN |
164 PCI_ERR_ROOT_CMD_FATAL_EN);
165
166 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
167 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
168 }
169
170 dev->dev.archdata.dma_ops = octeon_pci_dma_map_ops;
171
172 return 0;
173}
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182
183
184const char *octeon_get_pci_interrupts(void)
185{
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206
207 if (of_machine_is_compatible("dlink,dsr-500n"))
208 return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
209 switch (octeon_bootinfo->board_type) {
210 case CVMX_BOARD_TYPE_NAO38:
211
212 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
213 case CVMX_BOARD_TYPE_EBH3100:
214 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
215 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
216 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
217 case CVMX_BOARD_TYPE_BBGW_REF:
218 return "AABCD";
219 case CVMX_BOARD_TYPE_CUST_DSR1000N:
220 return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
221 case CVMX_BOARD_TYPE_THUNDER:
222 case CVMX_BOARD_TYPE_EBH3000:
223 default:
224 return "";
225 }
226}
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238
239int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
240 u8 slot, u8 pin)
241{
242 int irq_num;
243 const char *interrupts;
244 int dev_num;
245
246
247 interrupts = octeon_get_pci_interrupts();
248
249 dev_num = dev->devfn >> 3;
250 if (dev_num < strlen(interrupts))
251 irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
252 OCTEON_IRQ_PCI_INT0;
253 else
254 irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
255 return irq_num;
256}
257
258
259
260
261
262static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
263 int reg, int size, u32 *val)
264{
265 union octeon_pci_address pci_addr;
266
267 pci_addr.u64 = 0;
268 pci_addr.s.upper = 2;
269 pci_addr.s.io = 1;
270 pci_addr.s.did = 3;
271 pci_addr.s.subdid = 1;
272 pci_addr.s.endian_swap = 1;
273 pci_addr.s.bus = bus->number;
274 pci_addr.s.dev = devfn >> 3;
275 pci_addr.s.func = devfn & 0x7;
276 pci_addr.s.reg = reg;
277
278 switch (size) {
279 case 4:
280 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
281 return PCIBIOS_SUCCESSFUL;
282 case 2:
283 *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
284 return PCIBIOS_SUCCESSFUL;
285 case 1:
286 *val = cvmx_read64_uint8(pci_addr.u64);
287 return PCIBIOS_SUCCESSFUL;
288 }
289 return PCIBIOS_FUNC_NOT_SUPPORTED;
290}
291
292
293
294
295
296static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
297 int reg, int size, u32 val)
298{
299 union octeon_pci_address pci_addr;
300
301 pci_addr.u64 = 0;
302 pci_addr.s.upper = 2;
303 pci_addr.s.io = 1;
304 pci_addr.s.did = 3;
305 pci_addr.s.subdid = 1;
306 pci_addr.s.endian_swap = 1;
307 pci_addr.s.bus = bus->number;
308 pci_addr.s.dev = devfn >> 3;
309 pci_addr.s.func = devfn & 0x7;
310 pci_addr.s.reg = reg;
311
312 switch (size) {
313 case 4:
314 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
315 return PCIBIOS_SUCCESSFUL;
316 case 2:
317 cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
318 return PCIBIOS_SUCCESSFUL;
319 case 1:
320 cvmx_write64_uint8(pci_addr.u64, val);
321 return PCIBIOS_SUCCESSFUL;
322 }
323 return PCIBIOS_FUNC_NOT_SUPPORTED;
324}
325
326
327static struct pci_ops octeon_pci_ops = {
328 .read = octeon_read_config,
329 .write = octeon_write_config,
330};
331
332static struct resource octeon_pci_mem_resource = {
333 .start = 0,
334 .end = 0,
335 .name = "Octeon PCI MEM",
336 .flags = IORESOURCE_MEM,
337};
338
339
340
341
342
343static struct resource octeon_pci_io_resource = {
344 .start = 0x4000,
345 .end = OCTEON_PCI_IOSPACE_SIZE - 1,
346 .name = "Octeon PCI IO",
347 .flags = IORESOURCE_IO,
348};
349
350static struct pci_controller octeon_pci_controller = {
351 .pci_ops = &octeon_pci_ops,
352 .mem_resource = &octeon_pci_mem_resource,
353 .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
354 .io_resource = &octeon_pci_io_resource,
355 .io_offset = 0,
356 .io_map_base = OCTEON_PCI_IOSPACE_BASE,
357};
358
359
360
361
362
363static void octeon_pci_initialize(void)
364{
365 union cvmx_pci_cfg01 cfg01;
366 union cvmx_npi_ctl_status ctl_status;
367 union cvmx_pci_ctl_status_2 ctl_status_2;
368 union cvmx_pci_cfg19 cfg19;
369 union cvmx_pci_cfg16 cfg16;
370 union cvmx_pci_cfg22 cfg22;
371 union cvmx_pci_cfg56 cfg56;
372
373
374 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
375 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
376
377 udelay(2000);
378
379 ctl_status.u64 = 0;
380 ctl_status.s.max_word = 1;
381 ctl_status.s.timer = 1;
382 cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
383
384
385
386 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
387 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
388
389 udelay(2000);
390
391 ctl_status_2.u32 = 0;
392 ctl_status_2.s.tsr_hwm = 1;
393
394 ctl_status_2.s.bar2pres = 1;
395 ctl_status_2.s.bar2_enb = 1;
396 ctl_status_2.s.bar2_cax = 1;
397 ctl_status_2.s.bar2_esx = 1;
398 ctl_status_2.s.pmo_amod = 1;
399 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
400
401 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
402 ctl_status_2.s.bb1_siz = 1;
403 ctl_status_2.s.bb_ca = 1;
404 ctl_status_2.s.bb_es = 1;
405 ctl_status_2.s.bb1 = 1;
406 ctl_status_2.s.bb0 = 1;
407 }
408
409 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
410 udelay(2000);
411
412 ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
413 pr_notice("PCI Status: %s %s-bit\n",
414 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
415 ctl_status_2.s.ap_64ad ? "64" : "32");
416
417 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
418 union cvmx_pci_cnt_reg cnt_reg_start;
419 union cvmx_pci_cnt_reg cnt_reg_end;
420 unsigned long cycles, pci_clock;
421
422 cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
423 cycles = read_c0_cvmcount();
424 udelay(1000);
425 cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
426 cycles = read_c0_cvmcount() - cycles;
427 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
428 (cycles / (mips_hpt_frequency / 1000000));
429 pr_notice("PCI Clock: %lu MHz\n", pci_clock);
430 }
431
432
433
434
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437
438
439
440 if (ctl_status_2.s.ap_pcix) {
441 cfg19.u32 = 0;
442
443
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450
451
452
453
454 cfg19.s.tdomc = 4;
455
456
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463
464
465
466 cfg19.s.mdrrmc = 2;
467
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475
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477
478 cfg19.s.mrbcm = 1;
479 octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
480 }
481
482
483 cfg01.u32 = 0;
484 cfg01.s.msae = 1;
485 cfg01.s.me = 1;
486 cfg01.s.pee = 1;
487 cfg01.s.see = 1;
488 cfg01.s.fbbe = 1;
489
490 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
491
492#ifdef USE_OCTEON_INTERNAL_ARBITER
493
494
495
496
497
498 {
499 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
500
501 pci_int_arb_cfg.u64 = 0;
502 pci_int_arb_cfg.s.en = 1;
503 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
504 }
505#endif
506
507
508
509
510
511
512 cfg16.u32 = 0;
513 cfg16.s.mltd = 1;
514 octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
515
516
517
518
519
520 cfg22.u32 = 0;
521
522 cfg22.s.mrv = 0xff;
523
524
525
526
527 cfg22.s.flush = 1;
528 octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
529
530
531
532
533
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535
536
537 cfg56.u32 = 0;
538 cfg56.s.pxcid = 7;
539 cfg56.s.ncp = 0xe8;
540 cfg56.s.dpere = 1;
541 cfg56.s.roe = 1;
542 cfg56.s.mmbc = 1;
543
544 cfg56.s.most = 3;
545
546
547 octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
548
549
550
551
552
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554
555
556
557
558 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
559 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
560 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
561}
562
563
564
565
566
567static int __init octeon_pci_setup(void)
568{
569 union cvmx_npi_mem_access_subidx mem_access;
570 int index;
571
572
573 if (octeon_has_feature(OCTEON_FEATURE_PCIE))
574 return 0;
575
576
577 octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
578
579
580 if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
581 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
582 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
583 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
584 else
585 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
586
587 if (!octeon_is_pci_host()) {
588 pr_notice("Not in host mode, PCI Controller not initialized\n");
589 return 0;
590 }
591
592
593 set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
594 ioport_resource.start = 0;
595 ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
596
597 pr_notice("%s Octeon big bar support\n",
598 (octeon_dma_bar_type ==
599 OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
600
601 octeon_pci_initialize();
602
603 mem_access.u64 = 0;
604 mem_access.s.esr = 1;
605 mem_access.s.esw = 1;
606 mem_access.s.nsr = 0;
607 mem_access.s.nsw = 0;
608 mem_access.s.ror = 0;
609 mem_access.s.row = 0;
610 mem_access.s.ba = 0;
611 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
612
613
614
615
616
617
618
619 octeon_npi_write32(CVMX_NPI_PCI_CFG08,
620 (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
621 octeon_npi_write32(CVMX_NPI_PCI_CFG09,
622 (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
623
624 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
625
626 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
627 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
628
629
630
631
632
633 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
634 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
635
636
637 octeon_bar1_pci_phys = 0x80000000ull;
638 for (index = 0; index < 32; index++) {
639 union cvmx_pci_bar1_indexx bar1_index;
640
641 bar1_index.u32 = 0;
642
643 bar1_index.s.addr_idx =
644 (octeon_bar1_pci_phys >> 22) + index;
645
646 bar1_index.s.ca = 1;
647
648 bar1_index.s.end_swp = 1;
649
650 bar1_index.s.addr_v = 1;
651 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
652 bar1_index.u32);
653 }
654
655
656 octeon_pci_mem_resource.start =
657 OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
658 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
659 octeon_pci_mem_resource.end =
660 octeon_pci_mem_resource.start + (1ul << 30);
661 } else {
662
663 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
664 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
665
666
667 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
668 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
669
670
671 octeon_bar1_pci_phys =
672 virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
673
674 for (index = 0; index < 32; index++) {
675 union cvmx_pci_bar1_indexx bar1_index;
676
677 bar1_index.u32 = 0;
678
679 bar1_index.s.addr_idx =
680 (octeon_bar1_pci_phys >> 22) + index;
681
682 bar1_index.s.ca = 1;
683
684 bar1_index.s.end_swp = 1;
685
686 bar1_index.s.addr_v = 1;
687 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
688 bar1_index.u32);
689 }
690
691
692 octeon_pci_mem_resource.start =
693 OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
694 (4ul << 10);
695 octeon_pci_mem_resource.end =
696 octeon_pci_mem_resource.start + (1ul << 30);
697 }
698
699 register_pci_controller(&octeon_pci_controller);
700
701
702
703
704
705 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
706
707 if (IS_ERR(platform_device_register_simple("octeon_pci_edac",
708 -1, NULL, 0)))
709 pr_err("Registration of co_pci_edac failed!\n");
710
711 octeon_pci_dma_init();
712
713 return 0;
714}
715
716arch_initcall(octeon_pci_setup);
717