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20#ifndef _POWERPC_EEH_H
21#define _POWERPC_EEH_H
22#ifdef __KERNEL__
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/string.h>
27#include <linux/time.h>
28#include <linux/atomic.h>
29
30#include <uapi/asm/eeh.h>
31
32struct pci_dev;
33struct pci_bus;
34struct pci_dn;
35
36#ifdef CONFIG_EEH
37
38
39#define EEH_ENABLED 0x01
40#define EEH_FORCE_DISABLED 0x02
41#define EEH_PROBE_MODE_DEV 0x04
42#define EEH_PROBE_MODE_DEVTREE 0x08
43#define EEH_VALID_PE_ZERO 0x10
44#define EEH_ENABLE_IO_FOR_LOG 0x20
45#define EEH_EARLY_DUMP_LOG 0x40
46
47
48
49
50
51
52
53
54#define EEH_PE_RST_HOLD_TIME 250
55#define EEH_PE_RST_SETTLE_TIME 1800
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71#define EEH_PE_INVALID (1 << 0)
72#define EEH_PE_PHB (1 << 1)
73#define EEH_PE_DEVICE (1 << 2)
74#define EEH_PE_BUS (1 << 3)
75#define EEH_PE_VF (1 << 4)
76
77#define EEH_PE_ISOLATED (1 << 0)
78#define EEH_PE_RECOVERING (1 << 1)
79#define EEH_PE_CFG_BLOCKED (1 << 2)
80#define EEH_PE_RESET (1 << 3)
81
82#define EEH_PE_KEEP (1 << 8)
83#define EEH_PE_CFG_RESTRICTED (1 << 9)
84#define EEH_PE_REMOVED (1 << 10)
85#define EEH_PE_PRI_BUS (1 << 11)
86
87struct eeh_pe {
88 int type;
89 int state;
90 int config_addr;
91 int addr;
92 struct pci_controller *phb;
93 struct pci_bus *bus;
94 int check_count;
95 int freeze_count;
96 struct timeval tstamp;
97 int false_positives;
98 atomic_t pass_dev_cnt;
99 struct eeh_pe *parent;
100 void *data;
101 struct list_head child_list;
102 struct list_head edevs;
103 struct list_head child;
104};
105
106#define eeh_pe_for_each_dev(pe, edev, tmp) \
107 list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
108
109static inline bool eeh_pe_passed(struct eeh_pe *pe)
110{
111 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
112}
113
114
115
116
117
118
119
120
121#define EEH_DEV_BRIDGE (1 << 0)
122#define EEH_DEV_ROOT_PORT (1 << 1)
123#define EEH_DEV_DS_PORT (1 << 2)
124#define EEH_DEV_IRQ_DISABLED (1 << 3)
125#define EEH_DEV_DISCONNECTED (1 << 4)
126
127#define EEH_DEV_NO_HANDLER (1 << 8)
128#define EEH_DEV_SYSFS (1 << 9)
129#define EEH_DEV_REMOVED (1 << 10)
130
131struct eeh_dev {
132 int mode;
133 int class_code;
134 int config_addr;
135 int pe_config_addr;
136 u32 config_space[16];
137 int pcix_cap;
138 int pcie_cap;
139 int aer_cap;
140 int af_cap;
141 struct eeh_pe *pe;
142 struct list_head list;
143 struct list_head rmv_list;
144 struct pci_controller *phb;
145 struct pci_dn *pdn;
146 struct pci_dev *pdev;
147 bool in_error;
148 struct pci_dev *physfn;
149 struct pci_bus *bus;
150};
151
152static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
153{
154 return edev ? edev->pdn : NULL;
155}
156
157static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
158{
159 return edev ? edev->pdev : NULL;
160}
161
162static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
163{
164 return edev ? edev->pe : NULL;
165}
166
167
168enum {
169 EEH_NEXT_ERR_NONE = 0,
170 EEH_NEXT_ERR_INF,
171 EEH_NEXT_ERR_FROZEN_PE,
172 EEH_NEXT_ERR_FENCED_PHB,
173 EEH_NEXT_ERR_DEAD_PHB,
174 EEH_NEXT_ERR_DEAD_IOC
175};
176
177
178
179
180
181
182
183
184#define EEH_OPT_DISABLE 0
185#define EEH_OPT_ENABLE 1
186#define EEH_OPT_THAW_MMIO 2
187#define EEH_OPT_THAW_DMA 3
188#define EEH_OPT_FREEZE_PE 4
189#define EEH_STATE_UNAVAILABLE (1 << 0)
190#define EEH_STATE_NOT_SUPPORT (1 << 1)
191#define EEH_STATE_RESET_ACTIVE (1 << 2)
192#define EEH_STATE_MMIO_ACTIVE (1 << 3)
193#define EEH_STATE_DMA_ACTIVE (1 << 4)
194#define EEH_STATE_MMIO_ENABLED (1 << 5)
195#define EEH_STATE_DMA_ENABLED (1 << 6)
196#define EEH_RESET_DEACTIVATE 0
197#define EEH_RESET_HOT 1
198#define EEH_RESET_FUNDAMENTAL 3
199#define EEH_LOG_TEMP 1
200#define EEH_LOG_PERM 2
201
202struct eeh_ops {
203 char *name;
204 int (*init)(void);
205 int (*post_init)(void);
206 void* (*probe)(struct pci_dn *pdn, void *data);
207 int (*set_option)(struct eeh_pe *pe, int option);
208 int (*get_pe_addr)(struct eeh_pe *pe);
209 int (*get_state)(struct eeh_pe *pe, int *state);
210 int (*reset)(struct eeh_pe *pe, int option);
211 int (*wait_state)(struct eeh_pe *pe, int max_wait);
212 int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
213 int (*configure_bridge)(struct eeh_pe *pe);
214 int (*err_inject)(struct eeh_pe *pe, int type, int func,
215 unsigned long addr, unsigned long mask);
216 int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
217 int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
218 int (*next_error)(struct eeh_pe **pe);
219 int (*restore_config)(struct pci_dn *pdn);
220};
221
222extern int eeh_subsystem_flags;
223extern int eeh_max_freezes;
224extern struct eeh_ops *eeh_ops;
225extern raw_spinlock_t confirm_error_lock;
226
227static inline void eeh_add_flag(int flag)
228{
229 eeh_subsystem_flags |= flag;
230}
231
232static inline void eeh_clear_flag(int flag)
233{
234 eeh_subsystem_flags &= ~flag;
235}
236
237static inline bool eeh_has_flag(int flag)
238{
239 return !!(eeh_subsystem_flags & flag);
240}
241
242static inline bool eeh_enabled(void)
243{
244 if (eeh_has_flag(EEH_FORCE_DISABLED) ||
245 !eeh_has_flag(EEH_ENABLED))
246 return false;
247
248 return true;
249}
250
251static inline void eeh_serialize_lock(unsigned long *flags)
252{
253 raw_spin_lock_irqsave(&confirm_error_lock, *flags);
254}
255
256static inline void eeh_serialize_unlock(unsigned long flags)
257{
258 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
259}
260
261typedef void *(*eeh_traverse_func)(void *data, void *flag);
262void eeh_set_pe_aux_size(int size);
263int eeh_phb_pe_create(struct pci_controller *phb);
264struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
265struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
266int eeh_add_to_parent_pe(struct eeh_dev *edev);
267int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
268void eeh_pe_update_time_stamp(struct eeh_pe *pe);
269void *eeh_pe_traverse(struct eeh_pe *root,
270 eeh_traverse_func fn, void *flag);
271void *eeh_pe_dev_traverse(struct eeh_pe *root,
272 eeh_traverse_func fn, void *flag);
273void eeh_pe_restore_bars(struct eeh_pe *pe);
274const char *eeh_pe_loc_get(struct eeh_pe *pe);
275struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
276
277struct eeh_dev *eeh_dev_init(struct pci_dn *pdn);
278void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
279int eeh_init(void);
280int __init eeh_ops_register(struct eeh_ops *ops);
281int __exit eeh_ops_unregister(const char *name);
282int eeh_check_failure(const volatile void __iomem *token);
283int eeh_dev_check_failure(struct eeh_dev *edev);
284void eeh_addr_cache_build(void);
285void eeh_add_device_early(struct pci_dn *);
286void eeh_add_device_tree_early(struct pci_dn *);
287void eeh_add_device_late(struct pci_dev *);
288void eeh_add_device_tree_late(struct pci_bus *);
289void eeh_add_sysfs_files(struct pci_bus *);
290void eeh_remove_device(struct pci_dev *);
291int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state);
292int eeh_pe_reset_and_recover(struct eeh_pe *pe);
293int eeh_dev_open(struct pci_dev *pdev);
294void eeh_dev_release(struct pci_dev *pdev);
295struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
296int eeh_pe_set_option(struct eeh_pe *pe, int option);
297int eeh_pe_get_state(struct eeh_pe *pe);
298int eeh_pe_reset(struct eeh_pe *pe, int option);
299int eeh_pe_configure(struct eeh_pe *pe);
300int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
301 unsigned long addr, unsigned long mask);
302
303
304
305
306
307
308
309#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
310
311
312
313
314
315
316#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
317
318#else
319
320static inline bool eeh_enabled(void)
321{
322 return false;
323}
324
325static inline int eeh_init(void)
326{
327 return 0;
328}
329
330static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
331{
332 return NULL;
333}
334
335static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
336
337static inline int eeh_check_failure(const volatile void __iomem *token)
338{
339 return 0;
340}
341
342#define eeh_dev_check_failure(x) (0)
343
344static inline void eeh_addr_cache_build(void) { }
345
346static inline void eeh_add_device_early(struct pci_dn *pdn) { }
347
348static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
349
350static inline void eeh_add_device_late(struct pci_dev *dev) { }
351
352static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
353
354static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
355
356static inline void eeh_remove_device(struct pci_dev *dev) { }
357
358#define EEH_POSSIBLE_ERROR(val, type) (0)
359#define EEH_IO_ERROR_VALUE(size) (-1UL)
360#endif
361
362#ifdef CONFIG_PPC64
363
364
365
366static inline u8 eeh_readb(const volatile void __iomem *addr)
367{
368 u8 val = in_8(addr);
369 if (EEH_POSSIBLE_ERROR(val, u8))
370 eeh_check_failure(addr);
371 return val;
372}
373
374static inline u16 eeh_readw(const volatile void __iomem *addr)
375{
376 u16 val = in_le16(addr);
377 if (EEH_POSSIBLE_ERROR(val, u16))
378 eeh_check_failure(addr);
379 return val;
380}
381
382static inline u32 eeh_readl(const volatile void __iomem *addr)
383{
384 u32 val = in_le32(addr);
385 if (EEH_POSSIBLE_ERROR(val, u32))
386 eeh_check_failure(addr);
387 return val;
388}
389
390static inline u64 eeh_readq(const volatile void __iomem *addr)
391{
392 u64 val = in_le64(addr);
393 if (EEH_POSSIBLE_ERROR(val, u64))
394 eeh_check_failure(addr);
395 return val;
396}
397
398static inline u16 eeh_readw_be(const volatile void __iomem *addr)
399{
400 u16 val = in_be16(addr);
401 if (EEH_POSSIBLE_ERROR(val, u16))
402 eeh_check_failure(addr);
403 return val;
404}
405
406static inline u32 eeh_readl_be(const volatile void __iomem *addr)
407{
408 u32 val = in_be32(addr);
409 if (EEH_POSSIBLE_ERROR(val, u32))
410 eeh_check_failure(addr);
411 return val;
412}
413
414static inline u64 eeh_readq_be(const volatile void __iomem *addr)
415{
416 u64 val = in_be64(addr);
417 if (EEH_POSSIBLE_ERROR(val, u64))
418 eeh_check_failure(addr);
419 return val;
420}
421
422static inline void eeh_memcpy_fromio(void *dest, const
423 volatile void __iomem *src,
424 unsigned long n)
425{
426 _memcpy_fromio(dest, src, n);
427
428
429
430
431 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
432 eeh_check_failure(src);
433}
434
435
436static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
437 int ns)
438{
439 _insb(addr, buf, ns);
440 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
441 eeh_check_failure(addr);
442}
443
444static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
445 int ns)
446{
447 _insw(addr, buf, ns);
448 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
449 eeh_check_failure(addr);
450}
451
452static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
453 int nl)
454{
455 _insl(addr, buf, nl);
456 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
457 eeh_check_failure(addr);
458}
459
460#endif
461#endif
462#endif
463