LXR linux/arch/powerpc/include/asm/eeh.h

   1/*
   2 * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
   3 * Copyright 2001-2012 IBM Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18 */
  19
  20#ifndef _POWERPC_EEH_H
  21#define _POWERPC_EEH_H
  22#ifdef __KERNEL__
  23
  24#include <linux/init.h>
  25#include <linux/list.h>
  26#include <linux/string.h>
  27#include <linux/time.h>
  28#include <linux/atomic.h>
  29
  30#include <uapi/asm/eeh.h>
  31
  32struct pci_dev;
  33struct pci_bus;
  34struct pci_dn;
  35
  36#ifdef CONFIG_EEH
  37
  38/* EEH subsystem flags */
  39#define EEH_ENABLED             0x01    /* EEH enabled          */
  40#define EEH_FORCE_DISABLED      0x02    /* EEH disabled         */
  41#define EEH_PROBE_MODE_DEV      0x04    /* From PCI device      */
  42#define EEH_PROBE_MODE_DEVTREE  0x08    /* From device tree     */
  43#define EEH_VALID_PE_ZERO       0x10    /* PE#0 is valid        */
  44#define EEH_ENABLE_IO_FOR_LOG   0x20    /* Enable IO for log    */
  45#define EEH_EARLY_DUMP_LOG      0x40    /* Dump log immediately */
  46
  47/*
  48 * Delay for PE reset, all in ms
  49 *
  50 * PCI specification has reset hold time of 100 milliseconds.
  51 * We have 250 milliseconds here. The PCI bus settlement time
  52 * is specified as 1.5 seconds and we have 1.8 seconds.
  53 */
  54#define EEH_PE_RST_HOLD_TIME            250
  55#define EEH_PE_RST_SETTLE_TIME          1800
  56
  57/*
  58 * The struct is used to trace PE related EEH functionality.
  59 * In theory, there will have one instance of the struct to
  60 * be created against particular PE. In nature, PEs correlate
  61 * to each other. the struct has to reflect that hierarchy in
  62 * order to easily pick up those affected PEs when one particular
  63 * PE has EEH errors.
  64 *
  65 * Also, one particular PE might be composed of PCI device, PCI
  66 * bus and its subordinate components. The struct also need ship
  67 * the information. Further more, one particular PE is only meaingful
  68 * in the corresponding PHB. Therefore, the root PEs should be created
  69 * against existing PHBs in on-to-one fashion.
  70 */
  71#define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
  72#define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
  73#define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
  74#define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
  75#define EEH_PE_VF       (1 << 4)        /* VF PE     */
  76
  77#define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
  78#define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
  79#define EEH_PE_CFG_BLOCKED      (1 << 2)        /* Block config access  */
  80#define EEH_PE_RESET            (1 << 3)        /* PE reset in progress */
  81
  82#define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
  83#define EEH_PE_CFG_RESTRICTED   (1 << 9)        /* Block config on error */
  84#define EEH_PE_REMOVED          (1 << 10)       /* Removed permanently  */
  85#define EEH_PE_PRI_BUS          (1 << 11)       /* Cached primary bus   */
  86
  87struct eeh_pe {
  88        int type;                       /* PE type: PHB/Bus/Device      */
  89        int state;                      /* PE EEH dependent mode        */
  90        int config_addr;                /* Traditional PCI address      */
  91        int addr;                       /* PE configuration address     */
  92        struct pci_controller *phb;     /* Associated PHB               */
  93        struct pci_bus *bus;            /* Top PCI bus for bus PE       */
  94        int check_count;                /* Times of ignored error       */
  95        int freeze_count;               /* Times of froze up            */
  96        struct timeval tstamp;          /* Time on first-time freeze    */
  97        int false_positives;            /* Times of reported #ff's      */
  98        atomic_t pass_dev_cnt;          /* Count of passed through devs */
  99        struct eeh_pe *parent;          /* Parent PE                    */
 100        void *data;                     /* PE auxillary data            */
 101        struct list_head child_list;    /* Link PE to the child list    */
 102        struct list_head edevs;         /* Link list of EEH devices     */
 103        struct list_head child;         /* Child PEs                    */
 104};
 105
 106#define eeh_pe_for_each_dev(pe, edev, tmp) \
 107                list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
 108
 109static inline bool eeh_pe_passed(struct eeh_pe *pe)
 110{
 111        return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
 112}
 113
 114/*
 115 * The struct is used to trace EEH state for the associated
 116 * PCI device node or PCI device. In future, it might
 117 * represent PE as well so that the EEH device to form
 118 * another tree except the currently existing tree of PCI
 119 * buses and PCI devices
 120 */
 121#define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
 122#define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
 123#define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
 124#define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
 125#define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
 126
 127#define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
 128#define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
 129#define EEH_DEV_REMOVED         (1 << 10)       /* Removed permanently  */
 130
 131struct eeh_dev {
 132        int mode;                       /* EEH mode                     */
 133        int class_code;                 /* Class code of the device     */
 134        int config_addr;                /* Config address               */
 135        int pe_config_addr;             /* PE config address            */
 136        u32 config_space[16];           /* Saved PCI config space       */
 137        int pcix_cap;                   /* Saved PCIx capability        */
 138        int pcie_cap;                   /* Saved PCIe capability        */
 139        int aer_cap;                    /* Saved AER capability         */
 140        int af_cap;                     /* Saved AF capability          */
 141        struct eeh_pe *pe;              /* Associated PE                */
 142        struct list_head list;          /* Form link list in the PE     */
 143        struct list_head rmv_list;      /* Record the removed edevs     */
 144        struct pci_controller *phb;     /* Associated PHB               */
 145        struct pci_dn *pdn;             /* Associated PCI device node   */
 146        struct pci_dev *pdev;           /* Associated PCI device        */
 147        bool in_error;                  /* Error flag for edev          */
 148        struct pci_dev *physfn;         /* Associated SRIOV PF          */
 149        struct pci_bus *bus;            /* PCI bus for partial hotplug  */
 150};
 151
 152static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
 153{
 154        return edev ? edev->pdn : NULL;
 155}
 156
 157static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 158{
 159        return edev ? edev->pdev : NULL;
 160}
 161
 162static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
 163{
 164        return edev ? edev->pe : NULL;
 165}
 166
 167/* Return values from eeh_ops::next_error */
 168enum {
 169        EEH_NEXT_ERR_NONE = 0,
 170        EEH_NEXT_ERR_INF,
 171        EEH_NEXT_ERR_FROZEN_PE,
 172        EEH_NEXT_ERR_FENCED_PHB,
 173        EEH_NEXT_ERR_DEAD_PHB,
 174        EEH_NEXT_ERR_DEAD_IOC
 175};
 176
 177/*
 178 * The struct is used to trace the registered EEH operation
 179 * callback functions. Actually, those operation callback
 180 * functions are heavily platform dependent. That means the
 181 * platform should register its own EEH operation callback
 182 * functions before any EEH further operations.
 183 */
 184#define EEH_OPT_DISABLE         0       /* EEH disable  */
 185#define EEH_OPT_ENABLE          1       /* EEH enable   */
 186#define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
 187#define EEH_OPT_THAW_DMA        3       /* DMA enable   */
 188#define EEH_OPT_FREEZE_PE       4       /* Freeze PE    */
 189#define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
 190#define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
 191#define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
 192#define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
 193#define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
 194#define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
 195#define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
 196#define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
 197#define EEH_RESET_HOT           1       /* Hot reset                    */
 198#define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
 199#define EEH_LOG_TEMP            1       /* EEH temporary error log      */
 200#define EEH_LOG_PERM            2       /* EEH permanent error log      */
 201
 202struct eeh_ops {
 203        char *name;
 204        int (*init)(void);
 205        int (*post_init)(void);
 206        void* (*probe)(struct pci_dn *pdn, void *data);
 207        int (*set_option)(struct eeh_pe *pe, int option);
 208        int (*get_pe_addr)(struct eeh_pe *pe);
 209        int (*get_state)(struct eeh_pe *pe, int *state);
 210        int (*reset)(struct eeh_pe *pe, int option);
 211        int (*wait_state)(struct eeh_pe *pe, int max_wait);
 212        int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
 213        int (*configure_bridge)(struct eeh_pe *pe);
 214        int (*err_inject)(struct eeh_pe *pe, int type, int func,
 215                          unsigned long addr, unsigned long mask);
 216        int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
 217        int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
 218        int (*next_error)(struct eeh_pe **pe);
 219        int (*restore_config)(struct pci_dn *pdn);
 220};
 221
 222extern int eeh_subsystem_flags;
 223extern int eeh_max_freezes;
 224extern struct eeh_ops *eeh_ops;
 225extern raw_spinlock_t confirm_error_lock;
 226
 227static inline void eeh_add_flag(int flag)
 228{
 229        eeh_subsystem_flags |= flag;
 230}
 231
 232static inline void eeh_clear_flag(int flag)
 233{
 234        eeh_subsystem_flags &= ~flag;
 235}
 236
 237static inline bool eeh_has_flag(int flag)
 238{
 239        return !!(eeh_subsystem_flags & flag);
 240}
 241
 242static inline bool eeh_enabled(void)
 243{
 244        if (eeh_has_flag(EEH_FORCE_DISABLED) ||
 245            !eeh_has_flag(EEH_ENABLED))
 246                return false;
 247
 248        return true;
 249}
 250
 251static inline void eeh_serialize_lock(unsigned long *flags)
 252{
 253        raw_spin_lock_irqsave(&confirm_error_lock, *flags);
 254}
 255
 256static inline void eeh_serialize_unlock(unsigned long flags)
 257{
 258        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 259}
 260
 261typedef void *(*eeh_traverse_func)(void *data, void *flag);
 262void eeh_set_pe_aux_size(int size);
 263int eeh_phb_pe_create(struct pci_controller *phb);
 264struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
 265struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
 266int eeh_add_to_parent_pe(struct eeh_dev *edev);
 267int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
 268void eeh_pe_update_time_stamp(struct eeh_pe *pe);
 269void *eeh_pe_traverse(struct eeh_pe *root,
 270                eeh_traverse_func fn, void *flag);
 271void *eeh_pe_dev_traverse(struct eeh_pe *root,
 272                eeh_traverse_func fn, void *flag);
 273void eeh_pe_restore_bars(struct eeh_pe *pe);
 274const char *eeh_pe_loc_get(struct eeh_pe *pe);
 275struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
 276
 277struct eeh_dev *eeh_dev_init(struct pci_dn *pdn);
 278void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
 279int eeh_init(void);
 280int __init eeh_ops_register(struct eeh_ops *ops);
 281int __exit eeh_ops_unregister(const char *name);
 282int eeh_check_failure(const volatile void __iomem *token);
 283int eeh_dev_check_failure(struct eeh_dev *edev);
 284void eeh_addr_cache_build(void);
 285void eeh_add_device_early(struct pci_dn *);
 286void eeh_add_device_tree_early(struct pci_dn *);
 287void eeh_add_device_late(struct pci_dev *);
 288void eeh_add_device_tree_late(struct pci_bus *);
 289void eeh_add_sysfs_files(struct pci_bus *);
 290void eeh_remove_device(struct pci_dev *);
 291int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state);
 292int eeh_pe_reset_and_recover(struct eeh_pe *pe);
 293int eeh_dev_open(struct pci_dev *pdev);
 294void eeh_dev_release(struct pci_dev *pdev);
 295struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
 296int eeh_pe_set_option(struct eeh_pe *pe, int option);
 297int eeh_pe_get_state(struct eeh_pe *pe);
 298int eeh_pe_reset(struct eeh_pe *pe, int option);
 299int eeh_pe_configure(struct eeh_pe *pe);
 300int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
 301                      unsigned long addr, unsigned long mask);
 302
 303/**
 304 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
 305 *
 306 * If this macro yields TRUE, the caller relays to eeh_check_failure()
 307 * which does further tests out of line.
 308 */
 309#define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
 310
 311/*
 312 * Reads from a device which has been isolated by EEH will return
 313 * all 1s.  This macro gives an all-1s value of the given size (in
 314 * bytes: 1, 2, or 4) for comparing with the result of a read.
 315 */
 316#define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
 317
 318#else /* !CONFIG_EEH */
 319
 320static inline bool eeh_enabled(void)
 321{
 322        return false;
 323}
 324
 325static inline int eeh_init(void)
 326{
 327        return 0;
 328}
 329
 330static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
 331{
 332        return NULL;
 333}
 334
 335static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
 336
 337static inline int eeh_check_failure(const volatile void __iomem *token)
 338{
 339        return 0;
 340}
 341
 342#define eeh_dev_check_failure(x) (0)
 343
 344static inline void eeh_addr_cache_build(void) { }
 345
 346static inline void eeh_add_device_early(struct pci_dn *pdn) { }
 347
 348static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
 349
 350static inline void eeh_add_device_late(struct pci_dev *dev) { }
 351
 352static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
 353
 354static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
 355
 356static inline void eeh_remove_device(struct pci_dev *dev) { }
 357
 358#define EEH_POSSIBLE_ERROR(val, type) (0)
 359#define EEH_IO_ERROR_VALUE(size) (-1UL)
 360#endif /* CONFIG_EEH */
 361
 362#ifdef CONFIG_PPC64
 363/*
 364 * MMIO read/write operations with EEH support.
 365 */
 366static inline u8 eeh_readb(const volatile void __iomem *addr)
 367{
 368        u8 val = in_8(addr);
 369        if (EEH_POSSIBLE_ERROR(val, u8))
 370                eeh_check_failure(addr);
 371        return val;
 372}
 373
 374static inline u16 eeh_readw(const volatile void __iomem *addr)
 375{
 376        u16 val = in_le16(addr);
 377        if (EEH_POSSIBLE_ERROR(val, u16))
 378                eeh_check_failure(addr);
 379        return val;
 380}
 381
 382static inline u32 eeh_readl(const volatile void __iomem *addr)
 383{
 384        u32 val = in_le32(addr);
 385        if (EEH_POSSIBLE_ERROR(val, u32))
 386                eeh_check_failure(addr);
 387        return val;
 388}
 389
 390static inline u64 eeh_readq(const volatile void __iomem *addr)
 391{
 392        u64 val = in_le64(addr);
 393        if (EEH_POSSIBLE_ERROR(val, u64))
 394                eeh_check_failure(addr);
 395        return val;
 396}
 397
 398static inline u16 eeh_readw_be(const volatile void __iomem *addr)
 399{
 400        u16 val = in_be16(addr);
 401        if (EEH_POSSIBLE_ERROR(val, u16))
 402                eeh_check_failure(addr);
 403        return val;
 404}
 405
 406static inline u32 eeh_readl_be(const volatile void __iomem *addr)
 407{
 408        u32 val = in_be32(addr);
 409        if (EEH_POSSIBLE_ERROR(val, u32))
 410                eeh_check_failure(addr);
 411        return val;
 412}
 413
 414static inline u64 eeh_readq_be(const volatile void __iomem *addr)
 415{
 416        u64 val = in_be64(addr);
 417        if (EEH_POSSIBLE_ERROR(val, u64))
 418                eeh_check_failure(addr);
 419        return val;
 420}
 421
 422static inline void eeh_memcpy_fromio(void *dest, const
 423                                     volatile void __iomem *src,
 424                                     unsigned long n)
 425{
 426        _memcpy_fromio(dest, src, n);
 427
 428        /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
 429         * were copied. Check all four bytes.
 430         */
 431        if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
 432                eeh_check_failure(src);
 433}
 434
 435/* in-string eeh macros */
 436static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
 437                              int ns)
 438{
 439        _insb(addr, buf, ns);
 440        if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
 441                eeh_check_failure(addr);
 442}
 443
 444static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
 445                              int ns)
 446{
 447        _insw(addr, buf, ns);
 448        if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
 449                eeh_check_failure(addr);
 450}
 451
 452static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
 453                              int nl)
 454{
 455        _insl(addr, buf, nl);
 456        if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
 457                eeh_check_failure(addr);
 458}
 459
 460#endif /* CONFIG_PPC64 */
 461#endif /* __KERNEL__ */
 462#endif /* _POWERPC_EEH_H */
 463