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25#include <linux/delay.h>
26#include <linux/export.h>
27#include <linux/gfp.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/string.h>
31
32#include <asm/pci-bridge.h>
33#include <asm/ppc-pci.h>
34
35static int eeh_pe_aux_size = 0;
36static LIST_HEAD(eeh_phb_pe);
37
38
39
40
41
42
43
44void eeh_set_pe_aux_size(int size)
45{
46 if (size < 0)
47 return;
48
49 eeh_pe_aux_size = size;
50}
51
52
53
54
55
56
57
58
59static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
60{
61 struct eeh_pe *pe;
62 size_t alloc_size;
63
64 alloc_size = sizeof(struct eeh_pe);
65 if (eeh_pe_aux_size) {
66 alloc_size = ALIGN(alloc_size, cache_line_size());
67 alloc_size += eeh_pe_aux_size;
68 }
69
70
71 pe = kzalloc(alloc_size, GFP_KERNEL);
72 if (!pe) return NULL;
73
74
75 pe->type = type;
76 pe->phb = phb;
77 INIT_LIST_HEAD(&pe->child_list);
78 INIT_LIST_HEAD(&pe->child);
79 INIT_LIST_HEAD(&pe->edevs);
80
81 pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
82 cache_line_size());
83 return pe;
84}
85
86
87
88
89
90
91
92
93int eeh_phb_pe_create(struct pci_controller *phb)
94{
95 struct eeh_pe *pe;
96
97
98 pe = eeh_pe_alloc(phb, EEH_PE_PHB);
99 if (!pe) {
100 pr_err("%s: out of memory!\n", __func__);
101 return -ENOMEM;
102 }
103
104
105 list_add_tail(&pe->child, &eeh_phb_pe);
106
107 pr_debug("EEH: Add PE for PHB#%x\n", phb->global_number);
108
109 return 0;
110}
111
112
113
114
115
116
117
118
119
120struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
121{
122 struct eeh_pe *pe;
123
124 list_for_each_entry(pe, &eeh_phb_pe, child) {
125
126
127
128
129
130 if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
131 return pe;
132 }
133
134 return NULL;
135}
136
137
138
139
140
141
142
143
144
145static struct eeh_pe *eeh_pe_next(struct eeh_pe *pe,
146 struct eeh_pe *root)
147{
148 struct list_head *next = pe->child_list.next;
149
150 if (next == &pe->child_list) {
151 while (1) {
152 if (pe == root)
153 return NULL;
154 next = pe->child.next;
155 if (next != &pe->parent->child_list)
156 break;
157 pe = pe->parent;
158 }
159 }
160
161 return list_entry(next, struct eeh_pe, child);
162}
163
164
165
166
167
168
169
170
171
172
173
174
175void *eeh_pe_traverse(struct eeh_pe *root,
176 eeh_traverse_func fn, void *flag)
177{
178 struct eeh_pe *pe;
179 void *ret;
180
181 for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
182 ret = fn(pe, flag);
183 if (ret) return ret;
184 }
185
186 return NULL;
187}
188
189
190
191
192
193
194
195
196
197
198void *eeh_pe_dev_traverse(struct eeh_pe *root,
199 eeh_traverse_func fn, void *flag)
200{
201 struct eeh_pe *pe;
202 struct eeh_dev *edev, *tmp;
203 void *ret;
204
205 if (!root) {
206 pr_warn("%s: Invalid PE %p\n",
207 __func__, root);
208 return NULL;
209 }
210
211
212 for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
213 eeh_pe_for_each_dev(pe, edev, tmp) {
214 ret = fn(edev, flag);
215 if (ret)
216 return ret;
217 }
218 }
219
220 return NULL;
221}
222
223
224
225
226
227
228
229
230
231
232
233static void *__eeh_pe_get(void *data, void *flag)
234{
235 struct eeh_pe *pe = (struct eeh_pe *)data;
236 struct eeh_dev *edev = (struct eeh_dev *)flag;
237
238
239 if (pe->type & EEH_PE_PHB)
240 return NULL;
241
242
243
244
245
246 if (eeh_has_flag(EEH_VALID_PE_ZERO)) {
247 if (edev->pe_config_addr == pe->addr)
248 return pe;
249 } else {
250 if (edev->pe_config_addr &&
251 (edev->pe_config_addr == pe->addr))
252 return pe;
253 }
254
255
256 if (edev->config_addr &&
257 (edev->config_addr == pe->config_addr))
258 return pe;
259
260 return NULL;
261}
262
263
264
265
266
267
268
269
270
271
272
273
274struct eeh_pe *eeh_pe_get(struct eeh_dev *edev)
275{
276 struct eeh_pe *root = eeh_phb_pe_get(edev->phb);
277 struct eeh_pe *pe;
278
279 pe = eeh_pe_traverse(root, __eeh_pe_get, edev);
280
281 return pe;
282}
283
284
285
286
287
288
289
290
291
292static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
293{
294 struct eeh_dev *parent;
295 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
296
297
298
299
300
301
302 if (edev->physfn)
303 pdn = pci_get_pdn(edev->physfn);
304 else
305 pdn = pdn ? pdn->parent : NULL;
306 while (pdn) {
307
308 parent = pdn_to_eeh_dev(pdn);
309 if (!parent)
310 return NULL;
311
312 if (parent->pe)
313 return parent->pe;
314
315 pdn = pdn->parent;
316 }
317
318 return NULL;
319}
320
321
322
323
324
325
326
327
328
329
330int eeh_add_to_parent_pe(struct eeh_dev *edev)
331{
332 struct eeh_pe *pe, *parent;
333
334
335 if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) {
336 pr_err("%s: Invalid PE#0 for edev 0x%x on PHB#%x\n",
337 __func__, edev->config_addr, edev->phb->global_number);
338 return -EINVAL;
339 }
340
341
342
343
344
345
346
347 pe = eeh_pe_get(edev);
348 if (pe && !(pe->type & EEH_PE_INVALID)) {
349
350 pe->type = EEH_PE_BUS;
351 edev->pe = pe;
352
353
354 list_add_tail(&edev->list, &pe->edevs);
355 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Bus PE#%x\n",
356 edev->phb->global_number,
357 edev->config_addr >> 8,
358 PCI_SLOT(edev->config_addr & 0xFF),
359 PCI_FUNC(edev->config_addr & 0xFF),
360 pe->addr);
361 return 0;
362 } else if (pe && (pe->type & EEH_PE_INVALID)) {
363 list_add_tail(&edev->list, &pe->edevs);
364 edev->pe = pe;
365
366
367
368
369 parent = pe;
370 while (parent) {
371 if (!(parent->type & EEH_PE_INVALID))
372 break;
373 parent->type &= ~(EEH_PE_INVALID | EEH_PE_KEEP);
374 parent = parent->parent;
375 }
376
377 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Device "
378 "PE#%x, Parent PE#%x\n",
379 edev->phb->global_number,
380 edev->config_addr >> 8,
381 PCI_SLOT(edev->config_addr & 0xFF),
382 PCI_FUNC(edev->config_addr & 0xFF),
383 pe->addr, pe->parent->addr);
384 return 0;
385 }
386
387
388 if (edev->physfn)
389 pe = eeh_pe_alloc(edev->phb, EEH_PE_VF);
390 else
391 pe = eeh_pe_alloc(edev->phb, EEH_PE_DEVICE);
392 if (!pe) {
393 pr_err("%s: out of memory!\n", __func__);
394 return -ENOMEM;
395 }
396 pe->addr = edev->pe_config_addr;
397 pe->config_addr = edev->config_addr;
398
399
400
401
402
403
404
405 parent = eeh_pe_get_parent(edev);
406 if (!parent) {
407 parent = eeh_phb_pe_get(edev->phb);
408 if (!parent) {
409 pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
410 __func__, edev->phb->global_number);
411 edev->pe = NULL;
412 kfree(pe);
413 return -EEXIST;
414 }
415 }
416 pe->parent = parent;
417
418
419
420
421
422 list_add_tail(&pe->child, &parent->child_list);
423 list_add_tail(&edev->list, &pe->edevs);
424 edev->pe = pe;
425 pr_debug("EEH: Add %04x:%02x:%02x.%01x to "
426 "Device PE#%x, Parent PE#%x\n",
427 edev->phb->global_number,
428 edev->config_addr >> 8,
429 PCI_SLOT(edev->config_addr & 0xFF),
430 PCI_FUNC(edev->config_addr & 0xFF),
431 pe->addr, pe->parent->addr);
432
433 return 0;
434}
435
436
437
438
439
440
441
442
443
444
445int eeh_rmv_from_parent_pe(struct eeh_dev *edev)
446{
447 struct eeh_pe *pe, *parent, *child;
448 int cnt;
449
450 if (!edev->pe) {
451 pr_debug("%s: No PE found for device %04x:%02x:%02x.%01x\n",
452 __func__, edev->phb->global_number,
453 edev->config_addr >> 8,
454 PCI_SLOT(edev->config_addr & 0xFF),
455 PCI_FUNC(edev->config_addr & 0xFF));
456 return -EEXIST;
457 }
458
459
460 pe = eeh_dev_to_pe(edev);
461 edev->pe = NULL;
462 list_del(&edev->list);
463
464
465
466
467
468
469
470 while (1) {
471 parent = pe->parent;
472 if (pe->type & EEH_PE_PHB)
473 break;
474
475 if (!(pe->state & EEH_PE_KEEP)) {
476 if (list_empty(&pe->edevs) &&
477 list_empty(&pe->child_list)) {
478 list_del(&pe->child);
479 kfree(pe);
480 } else {
481 break;
482 }
483 } else {
484 if (list_empty(&pe->edevs)) {
485 cnt = 0;
486 list_for_each_entry(child, &pe->child_list, child) {
487 if (!(child->type & EEH_PE_INVALID)) {
488 cnt++;
489 break;
490 }
491 }
492
493 if (!cnt)
494 pe->type |= EEH_PE_INVALID;
495 else
496 break;
497 }
498 }
499
500 pe = parent;
501 }
502
503 return 0;
504}
505
506
507
508
509
510
511
512
513
514
515void eeh_pe_update_time_stamp(struct eeh_pe *pe)
516{
517 struct timeval tstamp;
518
519 if (!pe) return;
520
521 if (pe->freeze_count <= 0) {
522 pe->freeze_count = 0;
523 do_gettimeofday(&pe->tstamp);
524 } else {
525 do_gettimeofday(&tstamp);
526 if (tstamp.tv_sec - pe->tstamp.tv_sec > 3600) {
527 pe->tstamp = tstamp;
528 pe->freeze_count = 0;
529 }
530 }
531}
532
533
534
535
536
537
538
539
540
541
542static void *__eeh_pe_state_mark(void *data, void *flag)
543{
544 struct eeh_pe *pe = (struct eeh_pe *)data;
545 int state = *((int *)flag);
546 struct eeh_dev *edev, *tmp;
547 struct pci_dev *pdev;
548
549
550 if (pe->state & EEH_PE_REMOVED)
551 return NULL;
552
553 pe->state |= state;
554
555
556 if (!(state & EEH_PE_ISOLATED))
557 return NULL;
558
559 eeh_pe_for_each_dev(pe, edev, tmp) {
560 pdev = eeh_dev_to_pci_dev(edev);
561 if (pdev)
562 pdev->error_state = pci_channel_io_frozen;
563 }
564
565
566 if (pe->state & EEH_PE_CFG_RESTRICTED)
567 pe->state |= EEH_PE_CFG_BLOCKED;
568
569 return NULL;
570}
571
572
573
574
575
576
577
578
579
580void eeh_pe_state_mark(struct eeh_pe *pe, int state)
581{
582 eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
583}
584EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
585
586static void *__eeh_pe_dev_mode_mark(void *data, void *flag)
587{
588 struct eeh_dev *edev = data;
589 int mode = *((int *)flag);
590
591 edev->mode |= mode;
592
593 return NULL;
594}
595
596
597
598
599
600
601
602void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
603{
604 eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
605}
606
607
608
609
610
611
612
613
614
615
616static void *__eeh_pe_state_clear(void *data, void *flag)
617{
618 struct eeh_pe *pe = (struct eeh_pe *)data;
619 int state = *((int *)flag);
620 struct eeh_dev *edev, *tmp;
621 struct pci_dev *pdev;
622
623
624 if (pe->state & EEH_PE_REMOVED)
625 return NULL;
626
627 pe->state &= ~state;
628
629
630
631
632
633
634 if (!(state & EEH_PE_ISOLATED))
635 return NULL;
636
637 pe->check_count = 0;
638 eeh_pe_for_each_dev(pe, edev, tmp) {
639 pdev = eeh_dev_to_pci_dev(edev);
640 if (!pdev)
641 continue;
642
643 pdev->error_state = pci_channel_io_normal;
644 }
645
646
647 if (pe->state & EEH_PE_CFG_RESTRICTED)
648 pe->state &= ~EEH_PE_CFG_BLOCKED;
649
650 return NULL;
651}
652
653
654
655
656
657
658
659
660
661
662void eeh_pe_state_clear(struct eeh_pe *pe, int state)
663{
664 eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
665}
666
667
668
669
670
671
672
673
674
675
676
677
678void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state)
679{
680 eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
681 if (!(state & EEH_PE_ISOLATED))
682 return;
683
684
685 state = EEH_PE_CFG_BLOCKED;
686 eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
687}
688
689
690
691
692
693
694
695
696
697
698
699
700static void eeh_bridge_check_link(struct eeh_dev *edev)
701{
702 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
703 int cap;
704 uint32_t val;
705 int timeout = 0;
706
707
708
709
710
711 if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
712 return;
713
714 pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
715 __func__, edev->phb->global_number,
716 edev->config_addr >> 8,
717 PCI_SLOT(edev->config_addr & 0xFF),
718 PCI_FUNC(edev->config_addr & 0xFF));
719
720
721 cap = edev->pcie_cap;
722 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
723 if (!(val & PCI_EXP_SLTSTA_PDS)) {
724 pr_debug(" No card in the slot (0x%04x) !\n", val);
725 return;
726 }
727
728
729 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
730 if (val & PCI_EXP_SLTCAP_PCP) {
731 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
732 if (val & PCI_EXP_SLTCTL_PCC) {
733 pr_debug(" In power-off state, power it on ...\n");
734 val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
735 val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
736 eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
737 msleep(2 * 1000);
738 }
739 }
740
741
742 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
743 val &= ~PCI_EXP_LNKCTL_LD;
744 eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
745
746
747 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
748 if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
749 pr_debug(" No link reporting capability (0x%08x) \n", val);
750 msleep(1000);
751 return;
752 }
753
754
755 timeout = 0;
756 while (timeout < 5000) {
757 msleep(20);
758 timeout += 20;
759
760 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
761 if (val & PCI_EXP_LNKSTA_DLLLA)
762 break;
763 }
764
765 if (val & PCI_EXP_LNKSTA_DLLLA)
766 pr_debug(" Link up (%s)\n",
767 (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
768 else
769 pr_debug(" Link not ready (0x%04x)\n", val);
770}
771
772#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
773#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
774
775static void eeh_restore_bridge_bars(struct eeh_dev *edev)
776{
777 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
778 int i;
779
780
781
782
783
784 for (i = 4; i < 13; i++)
785 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
786
787 eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
788
789
790 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
791 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
792 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
793 SAVED_BYTE(PCI_LATENCY_TIMER));
794
795 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
796
797
798 eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1]);
799
800
801 eeh_bridge_check_link(edev);
802}
803
804static void eeh_restore_device_bars(struct eeh_dev *edev)
805{
806 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
807 int i;
808 u32 cmd;
809
810 for (i = 4; i < 10; i++)
811 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
812
813 eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
814
815 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
816 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
817 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
818 SAVED_BYTE(PCI_LATENCY_TIMER));
819
820
821 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
822
823
824
825
826
827 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
828 if (edev->config_space[1] & PCI_COMMAND_PARITY)
829 cmd |= PCI_COMMAND_PARITY;
830 else
831 cmd &= ~PCI_COMMAND_PARITY;
832 if (edev->config_space[1] & PCI_COMMAND_SERR)
833 cmd |= PCI_COMMAND_SERR;
834 else
835 cmd &= ~PCI_COMMAND_SERR;
836 eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
837}
838
839
840
841
842
843
844
845
846
847
848static void *eeh_restore_one_device_bars(void *data, void *flag)
849{
850 struct eeh_dev *edev = (struct eeh_dev *)data;
851 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
852
853
854 if (edev->mode & EEH_DEV_BRIDGE)
855 eeh_restore_bridge_bars(edev);
856 else
857 eeh_restore_device_bars(edev);
858
859 if (eeh_ops->restore_config && pdn)
860 eeh_ops->restore_config(pdn);
861
862 return NULL;
863}
864
865
866
867
868
869
870
871
872void eeh_pe_restore_bars(struct eeh_pe *pe)
873{
874
875
876
877
878 eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
879}
880
881
882
883
884
885
886
887
888
889
890const char *eeh_pe_loc_get(struct eeh_pe *pe)
891{
892 struct pci_bus *bus = eeh_pe_bus_get(pe);
893 struct device_node *dn;
894 const char *loc = NULL;
895
896 while (bus) {
897 dn = pci_bus_to_OF_node(bus);
898 if (!dn) {
899 bus = bus->parent;
900 continue;
901 }
902
903 if (pci_is_root_bus(bus))
904 loc = of_get_property(dn, "ibm,io-base-loc-code", NULL);
905 else
906 loc = of_get_property(dn, "ibm,slot-location-code",
907 NULL);
908
909 if (loc)
910 return loc;
911
912 bus = bus->parent;
913 }
914
915 return "N/A";
916}
917
918
919
920
921
922
923
924
925
926
927
928struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
929{
930 struct eeh_dev *edev;
931 struct pci_dev *pdev;
932
933 if (pe->type & EEH_PE_PHB)
934 return pe->phb->bus;
935
936
937 if (pe->state & EEH_PE_PRI_BUS)
938 return pe->bus;
939
940
941 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
942 pdev = eeh_dev_to_pci_dev(edev);
943 if (pdev)
944 return pdev->bus;
945
946 return NULL;
947}
948