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13#include <linux/clk-provider.h>
14#include <mach/pxa2xx-regs.h>
15#include <linux/io.h>
16#include <linux/clk.h>
17#include <linux/clkdev.h>
18#include <linux/of.h>
19
20#include <mach/smemc.h>
21
22#include <dt-bindings/clock/pxa-clock.h>
23#include "clk-pxa.h"
24
25#define KHz 1000
26#define MHz (1000 * 1000)
27
28enum {
29 PXA_CORE_13Mhz = 0,
30 PXA_CORE_RUN,
31 PXA_CORE_TURBO,
32};
33
34enum {
35 PXA_BUS_13Mhz = 0,
36 PXA_BUS_RUN,
37};
38
39enum {
40 PXA_LCD_13Mhz = 0,
41 PXA_LCD_RUN,
42};
43
44enum {
45 PXA_MEM_13Mhz = 0,
46 PXA_MEM_SYSTEM_BUS,
47 PXA_MEM_RUN,
48};
49
50#define PXA27x_CLKCFG(B, HT, T) \
51 (CLKCFG_FCS | \
52 ((B) ? CLKCFG_FASTBUS : 0) | \
53 ((HT) ? CLKCFG_HALFTURBO : 0) | \
54 ((T) ? CLKCFG_TURBO : 0))
55#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
56
57#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
58#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
59
60
61#define SDRAM_TREF 64
62
63static const char * const get_freq_khz[] = {
64 "core", "run", "cpll", "memory",
65 "system_bus"
66};
67
68static int get_sdram_rows(void)
69{
70 static int sdram_rows;
71 unsigned int drac2 = 0, drac0 = 0;
72 u32 mdcnfg;
73
74 if (sdram_rows)
75 return sdram_rows;
76
77 mdcnfg = readl_relaxed(MDCNFG);
78
79 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
80 drac2 = MDCNFG_DRAC2(mdcnfg);
81
82 if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
83 drac0 = MDCNFG_DRAC0(mdcnfg);
84
85 sdram_rows = 1 << (11 + max(drac0, drac2));
86 return sdram_rows;
87}
88
89static u32 mdrefr_dri(unsigned int freq_khz)
90{
91 u32 interval = freq_khz * SDRAM_TREF / get_sdram_rows();
92
93 return (interval - 31) / 32;
94}
95
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100
101unsigned int pxa27x_get_clk_frequency_khz(int info)
102{
103 struct clk *clk;
104 unsigned long clks[5];
105 int i;
106
107 for (i = 0; i < 5; i++) {
108 clk = clk_get(NULL, get_freq_khz[i]);
109 if (IS_ERR(clk)) {
110 clks[i] = 0;
111 } else {
112 clks[i] = clk_get_rate(clk);
113 clk_put(clk);
114 }
115 }
116 if (info) {
117 pr_info("Run Mode clock: %ld.%02ldMHz\n",
118 clks[1] / 1000000, (clks[1] % 1000000) / 10000);
119 pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
120 clks[2] / 1000000, (clks[2] % 1000000) / 10000);
121 pr_info("Memory clock: %ld.%02ldMHz\n",
122 clks[3] / 1000000, (clks[3] % 1000000) / 10000);
123 pr_info("System bus clock: %ld.%02ldMHz\n",
124 clks[4] / 1000000, (clks[4] % 1000000) / 10000);
125 }
126 return (unsigned int)clks[0] / KHz;
127}
128
129bool pxa27x_is_ppll_disabled(void)
130{
131 unsigned long ccsr = readl(CCSR);
132
133 return ccsr & (1 << CCCR_PPDIS_BIT);
134}
135
136#define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \
137 bit, is_lp, flags) \
138 PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
139 is_lp, CKEN, CKEN_ ## bit, flags)
140#define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
141 PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \
142 div_hp, bit, pxa27x_is_ppll_disabled, 0)
143
144PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
145PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
146PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
147PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
148PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
149
150#define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
151 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
152 CKEN, CKEN_ ## bit, 0)
153#define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
154 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
155 CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
156
157static struct desc_clk_cken pxa27x_clocks[] __initdata = {
158 PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
159 PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
160 PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
161 PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0),
162 PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0),
163 PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5),
164 PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0),
165 PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0),
166 PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0),
167 PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0),
168 PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
169 PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0),
170 PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0),
171 PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
172 PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0),
173 PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0),
174 PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0),
175 PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0),
176 PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0),
177 PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0),
178 PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0),
179
180 PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
181 pxa27x_32Mhz_bus_parents, 0),
182 PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0),
183 PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0),
184 PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA,
185 pxa27x_lcd_bus_parents, 0),
186 PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
187 pxa27x_membus_parents, 0),
188
189};
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217static struct pxa2xx_freq pxa27x_freqs[] = {
218 {104000000, 104000, PXA27x_CCCR(1, 8, 2), 0, PXA27x_CLKCFG(1, 0, 1) },
219 {156000000, 104000, PXA27x_CCCR(1, 8, 3), 0, PXA27x_CLKCFG(1, 0, 1) },
220 {208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) },
221 {312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) },
222 {416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) },
223 {520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) },
224 {624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) },
225};
226
227static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
228 unsigned long parent_rate)
229{
230 unsigned long clkcfg;
231 unsigned int t, ht;
232 unsigned int l, L, n2, N;
233 unsigned long ccsr = readl(CCSR);
234
235 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
236 t = clkcfg & (1 << 0);
237 ht = clkcfg & (1 << 2);
238
239 l = ccsr & CCSR_L_MASK;
240 n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
241 L = l * parent_rate;
242 N = (L * n2) / 2;
243
244 return N;
245}
246
247static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw,
248 struct clk_rate_request *req)
249{
250 return pxa2xx_determine_rate(req, pxa27x_freqs,
251 ARRAY_SIZE(pxa27x_freqs));
252}
253
254static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
255 unsigned long parent_rate)
256{
257 int i;
258
259 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
260 for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
261 if (pxa27x_freqs[i].cpll == rate)
262 break;
263
264 if (i >= ARRAY_SIZE(pxa27x_freqs))
265 return -EINVAL;
266
267 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, MDREFR, CCCR);
268 return 0;
269}
270
271PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
272RATE_OPS(clk_pxa27x_cpll, "cpll");
273
274static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
275 unsigned long parent_rate)
276{
277 unsigned int l, osc_forced;
278 unsigned long ccsr = readl(CCSR);
279 unsigned long cccr = readl(CCCR);
280
281 l = ccsr & CCSR_L_MASK;
282 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
283 if (osc_forced) {
284 if (cccr & (1 << CCCR_LCD_26_BIT))
285 return parent_rate * 2;
286 else
287 return parent_rate;
288 }
289
290 if (l <= 7)
291 return parent_rate;
292 if (l <= 16)
293 return parent_rate / 2;
294 return parent_rate / 4;
295}
296
297static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
298{
299 unsigned int osc_forced;
300 unsigned long ccsr = readl(CCSR);
301
302 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
303 if (osc_forced)
304 return PXA_LCD_13Mhz;
305 else
306 return PXA_LCD_RUN;
307}
308
309PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" };
310MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");
311
312static void __init pxa27x_register_plls(void)
313{
314 clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
315 CLK_GET_RATE_NOCACHE,
316 13 * MHz);
317 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
318 CLK_GET_RATE_NOCACHE,
319 32768 * KHz);
320 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
321 clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
322}
323
324static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
325{
326 unsigned long clkcfg;
327 unsigned int t, ht, osc_forced;
328 unsigned long ccsr = readl(CCSR);
329
330 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
331 if (osc_forced)
332 return PXA_CORE_13Mhz;
333
334 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
335 t = clkcfg & (1 << 0);
336 ht = clkcfg & (1 << 2);
337
338 if (ht || t)
339 return PXA_CORE_TURBO;
340 return PXA_CORE_RUN;
341}
342
343static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index)
344{
345 if (index > PXA_CORE_TURBO)
346 return -EINVAL;
347
348 pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
349
350 return 0;
351}
352
353static int clk_pxa27x_core_determine_rate(struct clk_hw *hw,
354 struct clk_rate_request *req)
355{
356 return __clk_mux_determine_rate(hw, req);
357}
358
359PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
360MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);
361
362static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
363 unsigned long parent_rate)
364{
365 unsigned long ccsr = readl(CCSR);
366 unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
367
368 return (parent_rate / n2) * 2;
369}
370PARENTS(clk_pxa27x_run) = { "cpll" };
371RATE_RO_OPS(clk_pxa27x_run, "run");
372
373static void __init pxa27x_register_core(void)
374{
375 clkdev_pxa_register(CLK_NONE, "cpll", NULL,
376 clk_register_clk_pxa27x_cpll());
377 clkdev_pxa_register(CLK_NONE, "run", NULL,
378 clk_register_clk_pxa27x_run());
379 clkdev_pxa_register(CLK_CORE, "core", NULL,
380 clk_register_clk_pxa27x_core());
381}
382
383static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
384 unsigned long parent_rate)
385{
386 unsigned long clkcfg;
387 unsigned int b, osc_forced;
388 unsigned long ccsr = readl(CCSR);
389
390 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
391 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
392 b = clkcfg & (1 << 3);
393
394 if (osc_forced)
395 return parent_rate;
396 if (b)
397 return parent_rate;
398 else
399 return parent_rate / 2;
400}
401
402static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
403{
404 unsigned int osc_forced;
405 unsigned long ccsr = readl(CCSR);
406
407 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
408 if (osc_forced)
409 return PXA_BUS_13Mhz;
410 else
411 return PXA_BUS_RUN;
412}
413
414PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
415MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
416
417static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
418 unsigned long parent_rate)
419{
420 unsigned int a, l, osc_forced;
421 unsigned long cccr = readl(CCCR);
422 unsigned long ccsr = readl(CCSR);
423
424 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
425 a = cccr & (1 << CCCR_A_BIT);
426 l = ccsr & CCSR_L_MASK;
427
428 if (osc_forced || a)
429 return parent_rate;
430 if (l <= 10)
431 return parent_rate;
432 if (l <= 20)
433 return parent_rate / 2;
434 return parent_rate / 4;
435}
436
437static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
438{
439 unsigned int osc_forced, a;
440 unsigned long cccr = readl(CCCR);
441 unsigned long ccsr = readl(CCSR);
442
443 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
444 a = cccr & (1 << CCCR_A_BIT);
445 if (osc_forced)
446 return PXA_MEM_13Mhz;
447 if (a)
448 return PXA_MEM_SYSTEM_BUS;
449 else
450 return PXA_MEM_RUN;
451}
452
453PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
454MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
455
456#define DUMMY_CLK(_con_id, _dev_id, _parent) \
457 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
458struct dummy_clk {
459 const char *con_id;
460 const char *dev_id;
461 const char *parent;
462};
463static struct dummy_clk dummy_clks[] __initdata = {
464 DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
465 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
466 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
467};
468
469static void __init pxa27x_dummy_clocks_init(void)
470{
471 struct clk *clk;
472 struct dummy_clk *d;
473 const char *name;
474 int i;
475
476 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
477 d = &dummy_clks[i];
478 name = d->dev_id ? d->dev_id : d->con_id;
479 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
480 clk_register_clkdev(clk, d->con_id, d->dev_id);
481 }
482}
483
484static void __init pxa27x_base_clocks_init(void)
485{
486 pxa27x_register_plls();
487 pxa27x_register_core();
488 clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
489 clk_register_clk_pxa27x_system_bus());
490 clkdev_pxa_register(CLK_NONE, "memory", NULL,
491 clk_register_clk_pxa27x_memory());
492 clk_register_clk_pxa27x_lcd_base();
493}
494
495int __init pxa27x_clocks_init(void)
496{
497 pxa27x_base_clocks_init();
498 pxa27x_dummy_clocks_init();
499 return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
500}
501
502static void __init pxa27x_dt_clocks_init(struct device_node *np)
503{
504 pxa27x_clocks_init();
505 clk_pxa_dt_common_init(np);
506}
507CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);
508
