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23#ifndef __AMDGPU_UCODE_H__
24#define __AMDGPU_UCODE_H__
25
26struct common_firmware_header {
27 uint32_t size_bytes;
28 uint32_t header_size_bytes;
29 uint16_t header_version_major;
30 uint16_t header_version_minor;
31 uint16_t ip_version_major;
32 uint16_t ip_version_minor;
33 uint32_t ucode_version;
34 uint32_t ucode_size_bytes;
35 uint32_t ucode_array_offset_bytes;
36 uint32_t crc32;
37};
38
39
40struct mc_firmware_header_v1_0 {
41 struct common_firmware_header header;
42 uint32_t io_debug_size_bytes;
43 uint32_t io_debug_array_offset_bytes;
44};
45
46
47struct smc_firmware_header_v1_0 {
48 struct common_firmware_header header;
49 uint32_t ucode_start_addr;
50};
51
52
53struct gfx_firmware_header_v1_0 {
54 struct common_firmware_header header;
55 uint32_t ucode_feature_version;
56 uint32_t jt_offset;
57 uint32_t jt_size;
58};
59
60
61struct rlc_firmware_header_v1_0 {
62 struct common_firmware_header header;
63 uint32_t ucode_feature_version;
64 uint32_t save_and_restore_offset;
65 uint32_t clear_state_descriptor_offset;
66 uint32_t avail_scratch_ram_locations;
67 uint32_t master_pkt_description_offset;
68};
69
70
71struct rlc_firmware_header_v2_0 {
72 struct common_firmware_header header;
73 uint32_t ucode_feature_version;
74 uint32_t jt_offset;
75 uint32_t jt_size;
76 uint32_t save_and_restore_offset;
77 uint32_t clear_state_descriptor_offset;
78 uint32_t avail_scratch_ram_locations;
79 uint32_t reg_restore_list_size;
80 uint32_t reg_list_format_start;
81 uint32_t reg_list_format_separate_start;
82 uint32_t starting_offsets_start;
83 uint32_t reg_list_format_size_bytes;
84 uint32_t reg_list_format_array_offset_bytes;
85 uint32_t reg_list_size_bytes;
86 uint32_t reg_list_array_offset_bytes;
87 uint32_t reg_list_format_separate_size_bytes;
88 uint32_t reg_list_format_separate_array_offset_bytes;
89 uint32_t reg_list_separate_size_bytes;
90 uint32_t reg_list_separate_array_offset_bytes;
91};
92
93
94struct sdma_firmware_header_v1_0 {
95 struct common_firmware_header header;
96 uint32_t ucode_feature_version;
97 uint32_t ucode_change_version;
98 uint32_t jt_offset;
99 uint32_t jt_size;
100};
101
102
103struct sdma_firmware_header_v1_1 {
104 struct sdma_firmware_header_v1_0 v1_0;
105 uint32_t digest_size;
106};
107
108
109union amdgpu_firmware_header {
110 struct common_firmware_header common;
111 struct mc_firmware_header_v1_0 mc;
112 struct smc_firmware_header_v1_0 smc;
113 struct gfx_firmware_header_v1_0 gfx;
114 struct rlc_firmware_header_v1_0 rlc;
115 struct rlc_firmware_header_v2_0 rlc_v2_0;
116 struct sdma_firmware_header_v1_0 sdma;
117 struct sdma_firmware_header_v1_1 sdma_v1_1;
118 uint8_t raw[0x100];
119};
120
121
122
123
124enum AMDGPU_UCODE_ID {
125 AMDGPU_UCODE_ID_SDMA0 = 0,
126 AMDGPU_UCODE_ID_SDMA1,
127 AMDGPU_UCODE_ID_CP_CE,
128 AMDGPU_UCODE_ID_CP_PFP,
129 AMDGPU_UCODE_ID_CP_ME,
130 AMDGPU_UCODE_ID_CP_MEC1,
131 AMDGPU_UCODE_ID_CP_MEC2,
132 AMDGPU_UCODE_ID_RLC_G,
133 AMDGPU_UCODE_ID_STORAGE,
134 AMDGPU_UCODE_ID_MAXIMUM,
135};
136
137
138enum AMDGPU_UCODE_STATUS {
139 AMDGPU_UCODE_STATUS_INVALID,
140 AMDGPU_UCODE_STATUS_NOT_LOADED,
141 AMDGPU_UCODE_STATUS_LOADED,
142};
143
144
145#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001
146#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002
147#define AMDGPU_CPCE_UCODE_LOADED 0x00000004
148#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008
149#define AMDGPU_CPME_UCODE_LOADED 0x00000010
150#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020
151#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040
152#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100
153
154
155struct amdgpu_firmware_info {
156
157 enum AMDGPU_UCODE_ID ucode_id;
158
159 const struct firmware *fw;
160
161 uint64_t mc_addr;
162
163 void *kaddr;
164};
165
166void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
167void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
168void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
169void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
170void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
171int amdgpu_ucode_validate(const struct firmware *fw);
172bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
173 uint16_t hdr_major, uint16_t hdr_minor);
174int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
175int amdgpu_ucode_fini_bo(struct amdgpu_device *adev);
176
177#endif
178