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16#include <linux/clk.h>
17#include <linux/clk-provider.h>
18#include <linux/component.h>
19#include <linux/module.h>
20#include <linux/i2c.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/spinlock.h>
24#include <linux/videodev2.h>
25#include <drm/drmP.h>
26#include <drm/drm_atomic_helper.h>
27#include <drm/drm_fb_helper.h>
28#include <drm/drm_crtc_helper.h>
29#include <video/imx-ipu-v3.h>
30
31#include "imx-drm.h"
32
33#define TVE_COM_CONF_REG 0x00
34#define TVE_TVDAC0_CONT_REG 0x28
35#define TVE_TVDAC1_CONT_REG 0x2c
36#define TVE_TVDAC2_CONT_REG 0x30
37#define TVE_CD_CONT_REG 0x34
38#define TVE_INT_CONT_REG 0x64
39#define TVE_STAT_REG 0x68
40#define TVE_TST_MODE_REG 0x6c
41#define TVE_MV_CONT_REG 0xdc
42
43
44#define TVE_SYNC_CH_2_EN BIT(22)
45#define TVE_SYNC_CH_1_EN BIT(21)
46#define TVE_SYNC_CH_0_EN BIT(20)
47#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
48#define TVE_TV_OUT_DISABLE (0x0 << 12)
49#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
50#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
51#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
52#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
53#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
54#define TVE_TV_OUT_YPBPR (0x6 << 12)
55#define TVE_TV_OUT_RGB (0x7 << 12)
56#define TVE_TV_STAND_MASK (0xf << 8)
57#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
58#define TVE_P2I_CONV_EN BIT(7)
59#define TVE_INP_VIDEO_FORM BIT(6)
60#define TVE_INP_YCBCR_422 (0x0 << 6)
61#define TVE_INP_YCBCR_444 (0x1 << 6)
62#define TVE_DATA_SOURCE_MASK (0x3 << 4)
63#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
64#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
65#define TVE_DATA_SOURCE_EXT (0x2 << 4)
66#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
67#define TVE_IPU_CLK_EN_OFS 3
68#define TVE_IPU_CLK_EN BIT(3)
69#define TVE_DAC_SAMP_RATE_OFS 1
70#define TVE_DAC_SAMP_RATE_WIDTH 2
71#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
72#define TVE_DAC_FULL_RATE (0x0 << 1)
73#define TVE_DAC_DIV2_RATE (0x1 << 1)
74#define TVE_DAC_DIV4_RATE (0x2 << 1)
75#define TVE_EN BIT(0)
76
77
78#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
79
80
81#define TVE_CD_CH_2_SM_EN BIT(22)
82#define TVE_CD_CH_1_SM_EN BIT(21)
83#define TVE_CD_CH_0_SM_EN BIT(20)
84#define TVE_CD_CH_2_LM_EN BIT(18)
85#define TVE_CD_CH_1_LM_EN BIT(17)
86#define TVE_CD_CH_0_LM_EN BIT(16)
87#define TVE_CD_CH_2_REF_LVL BIT(10)
88#define TVE_CD_CH_1_REF_LVL BIT(9)
89#define TVE_CD_CH_0_REF_LVL BIT(8)
90#define TVE_CD_EN BIT(0)
91
92
93#define TVE_FRAME_END_IEN BIT(13)
94#define TVE_CD_MON_END_IEN BIT(2)
95#define TVE_CD_SM_IEN BIT(1)
96#define TVE_CD_LM_IEN BIT(0)
97
98
99#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
100
101enum {
102 TVE_MODE_TVOUT,
103 TVE_MODE_VGA,
104};
105
106struct imx_tve {
107 struct drm_connector connector;
108 struct drm_encoder encoder;
109 struct device *dev;
110 spinlock_t lock;
111 bool enabled;
112 int mode;
113 int di_hsync_pin;
114 int di_vsync_pin;
115
116 struct regmap *regmap;
117 struct regulator *dac_reg;
118 struct i2c_adapter *ddc;
119 struct clk *clk;
120 struct clk *di_sel_clk;
121 struct clk_hw clk_hw_di;
122 struct clk *di_clk;
123};
124
125static inline struct imx_tve *con_to_tve(struct drm_connector *c)
126{
127 return container_of(c, struct imx_tve, connector);
128}
129
130static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
131{
132 return container_of(e, struct imx_tve, encoder);
133}
134
135static void tve_lock(void *__tve)
136__acquires(&tve->lock)
137{
138 struct imx_tve *tve = __tve;
139
140 spin_lock(&tve->lock);
141}
142
143static void tve_unlock(void *__tve)
144__releases(&tve->lock)
145{
146 struct imx_tve *tve = __tve;
147
148 spin_unlock(&tve->lock);
149}
150
151static void tve_enable(struct imx_tve *tve)
152{
153 int ret;
154
155 if (!tve->enabled) {
156 tve->enabled = true;
157 clk_prepare_enable(tve->clk);
158 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
159 TVE_EN, TVE_EN);
160 }
161
162
163 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
164
165
166 if (tve->mode == TVE_MODE_VGA)
167 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
168 else
169 regmap_write(tve->regmap, TVE_INT_CONT_REG,
170 TVE_CD_SM_IEN |
171 TVE_CD_LM_IEN |
172 TVE_CD_MON_END_IEN);
173}
174
175static void tve_disable(struct imx_tve *tve)
176{
177 int ret;
178
179 if (tve->enabled) {
180 tve->enabled = false;
181 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
182 TVE_EN, 0);
183 clk_disable_unprepare(tve->clk);
184 }
185}
186
187static int tve_setup_tvout(struct imx_tve *tve)
188{
189 return -ENOTSUPP;
190}
191
192static int tve_setup_vga(struct imx_tve *tve)
193{
194 unsigned int mask;
195 unsigned int val;
196 int ret;
197
198
199 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
200 TVE_TVDAC_GAIN_MASK, 0x0a);
201 if (ret)
202 return ret;
203
204 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
205 TVE_TVDAC_GAIN_MASK, 0x0a);
206 if (ret)
207 return ret;
208
209 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
210 TVE_TVDAC_GAIN_MASK, 0x0a);
211 if (ret)
212 return ret;
213
214
215 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
216 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
217 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
218 val |= TVE_TV_STAND_HD_1080P30 | 0;
219 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
220 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
221 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
222 if (ret)
223 return ret;
224
225
226 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
227 TVE_TVDAC_TEST_MODE_MASK, 1);
228}
229
230static int imx_tve_connector_get_modes(struct drm_connector *connector)
231{
232 struct imx_tve *tve = con_to_tve(connector);
233 struct edid *edid;
234 int ret = 0;
235
236 if (!tve->ddc)
237 return 0;
238
239 edid = drm_get_edid(connector, tve->ddc);
240 if (edid) {
241 drm_mode_connector_update_edid_property(connector, edid);
242 ret = drm_add_edid_modes(connector, edid);
243 kfree(edid);
244 }
245
246 return ret;
247}
248
249static int imx_tve_connector_mode_valid(struct drm_connector *connector,
250 struct drm_display_mode *mode)
251{
252 struct imx_tve *tve = con_to_tve(connector);
253 unsigned long rate;
254
255
256 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
257 if (rate == mode->clock)
258 return MODE_OK;
259
260
261 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
262 if (rate == mode->clock)
263 return MODE_OK;
264
265 dev_warn(tve->dev, "ignoring mode %dx%d\n",
266 mode->hdisplay, mode->vdisplay);
267
268 return MODE_BAD;
269}
270
271static struct drm_encoder *imx_tve_connector_best_encoder(
272 struct drm_connector *connector)
273{
274 struct imx_tve *tve = con_to_tve(connector);
275
276 return &tve->encoder;
277}
278
279static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
280 struct drm_display_mode *orig_mode,
281 struct drm_display_mode *mode)
282{
283 struct imx_tve *tve = enc_to_tve(encoder);
284 unsigned long rounded_rate;
285 unsigned long rate;
286 int div = 1;
287 int ret;
288
289
290
291
292
293
294 rate = 2000UL * mode->clock;
295 clk_set_rate(tve->clk, rate);
296 rounded_rate = clk_get_rate(tve->clk);
297 if (rounded_rate >= rate)
298 div = 2;
299 clk_set_rate(tve->di_clk, rounded_rate / div);
300
301 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
302 if (ret < 0) {
303 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
304 ret);
305 }
306
307 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
308 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
309
310 if (tve->mode == TVE_MODE_VGA)
311 ret = tve_setup_vga(tve);
312 else
313 ret = tve_setup_tvout(tve);
314 if (ret)
315 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
316}
317
318static void imx_tve_encoder_enable(struct drm_encoder *encoder)
319{
320 struct imx_tve *tve = enc_to_tve(encoder);
321
322 tve_enable(tve);
323}
324
325static void imx_tve_encoder_disable(struct drm_encoder *encoder)
326{
327 struct imx_tve *tve = enc_to_tve(encoder);
328
329 tve_disable(tve);
330}
331
332static int imx_tve_atomic_check(struct drm_encoder *encoder,
333 struct drm_crtc_state *crtc_state,
334 struct drm_connector_state *conn_state)
335{
336 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
337 struct imx_tve *tve = enc_to_tve(encoder);
338
339 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
340 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
341 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
342
343 return 0;
344}
345
346static const struct drm_connector_funcs imx_tve_connector_funcs = {
347 .dpms = drm_atomic_helper_connector_dpms,
348 .fill_modes = drm_helper_probe_single_connector_modes,
349 .destroy = imx_drm_connector_destroy,
350 .reset = drm_atomic_helper_connector_reset,
351 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
352 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
353};
354
355static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
356 .get_modes = imx_tve_connector_get_modes,
357 .best_encoder = imx_tve_connector_best_encoder,
358 .mode_valid = imx_tve_connector_mode_valid,
359};
360
361static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
362 .destroy = imx_drm_encoder_destroy,
363};
364
365static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
366 .mode_set = imx_tve_encoder_mode_set,
367 .enable = imx_tve_encoder_enable,
368 .disable = imx_tve_encoder_disable,
369 .atomic_check = imx_tve_atomic_check,
370};
371
372static irqreturn_t imx_tve_irq_handler(int irq, void *data)
373{
374 struct imx_tve *tve = data;
375 unsigned int val;
376
377 regmap_read(tve->regmap, TVE_STAT_REG, &val);
378
379
380 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
381
382 return IRQ_HANDLED;
383}
384
385static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
386 unsigned long parent_rate)
387{
388 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
389 unsigned int val;
390 int ret;
391
392 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
393 if (ret < 0)
394 return 0;
395
396 switch (val & TVE_DAC_SAMP_RATE_MASK) {
397 case TVE_DAC_DIV4_RATE:
398 return parent_rate / 4;
399 case TVE_DAC_DIV2_RATE:
400 return parent_rate / 2;
401 case TVE_DAC_FULL_RATE:
402 default:
403 return parent_rate;
404 }
405
406 return 0;
407}
408
409static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
410 unsigned long *prate)
411{
412 unsigned long div;
413
414 div = *prate / rate;
415 if (div >= 4)
416 return *prate / 4;
417 else if (div >= 2)
418 return *prate / 2;
419 return *prate;
420}
421
422static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
423 unsigned long parent_rate)
424{
425 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
426 unsigned long div;
427 u32 val;
428 int ret;
429
430 div = parent_rate / rate;
431 if (div >= 4)
432 val = TVE_DAC_DIV4_RATE;
433 else if (div >= 2)
434 val = TVE_DAC_DIV2_RATE;
435 else
436 val = TVE_DAC_FULL_RATE;
437
438 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
439 TVE_DAC_SAMP_RATE_MASK, val);
440
441 if (ret < 0) {
442 dev_err(tve->dev, "failed to set divider: %d\n", ret);
443 return ret;
444 }
445
446 return 0;
447}
448
449static struct clk_ops clk_tve_di_ops = {
450 .round_rate = clk_tve_di_round_rate,
451 .set_rate = clk_tve_di_set_rate,
452 .recalc_rate = clk_tve_di_recalc_rate,
453};
454
455static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
456{
457 const char *tve_di_parent[1];
458 struct clk_init_data init = {
459 .name = "tve_di",
460 .ops = &clk_tve_di_ops,
461 .num_parents = 1,
462 .flags = 0,
463 };
464
465 tve_di_parent[0] = __clk_get_name(tve->clk);
466 init.parent_names = (const char **)&tve_di_parent;
467
468 tve->clk_hw_di.init = &init;
469 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
470 if (IS_ERR(tve->di_clk)) {
471 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
472 PTR_ERR(tve->di_clk));
473 return PTR_ERR(tve->di_clk);
474 }
475
476 return 0;
477}
478
479static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
480{
481 int encoder_type;
482 int ret;
483
484 encoder_type = tve->mode == TVE_MODE_VGA ?
485 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
486
487 ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
488 if (ret)
489 return ret;
490
491 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
492 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
493 encoder_type, NULL);
494
495 drm_connector_helper_add(&tve->connector,
496 &imx_tve_connector_helper_funcs);
497 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
498 DRM_MODE_CONNECTOR_VGA);
499
500 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
501
502 return 0;
503}
504
505static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
506{
507 return (reg % 4 == 0) && (reg <= 0xdc);
508}
509
510static struct regmap_config tve_regmap_config = {
511 .reg_bits = 32,
512 .val_bits = 32,
513 .reg_stride = 4,
514
515 .readable_reg = imx_tve_readable_reg,
516
517 .lock = tve_lock,
518 .unlock = tve_unlock,
519
520 .max_register = 0xdc,
521};
522
523static const char * const imx_tve_modes[] = {
524 [TVE_MODE_TVOUT] = "tvout",
525 [TVE_MODE_VGA] = "vga",
526};
527
528static const int of_get_tve_mode(struct device_node *np)
529{
530 const char *bm;
531 int ret, i;
532
533 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
534 if (ret < 0)
535 return ret;
536
537 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
538 if (!strcasecmp(bm, imx_tve_modes[i]))
539 return i;
540
541 return -EINVAL;
542}
543
544static int imx_tve_bind(struct device *dev, struct device *master, void *data)
545{
546 struct platform_device *pdev = to_platform_device(dev);
547 struct drm_device *drm = data;
548 struct device_node *np = dev->of_node;
549 struct device_node *ddc_node;
550 struct imx_tve *tve;
551 struct resource *res;
552 void __iomem *base;
553 unsigned int val;
554 int irq;
555 int ret;
556
557 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
558 if (!tve)
559 return -ENOMEM;
560
561 tve->dev = dev;
562 spin_lock_init(&tve->lock);
563
564 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
565 if (ddc_node) {
566 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
567 of_node_put(ddc_node);
568 }
569
570 tve->mode = of_get_tve_mode(np);
571 if (tve->mode != TVE_MODE_VGA) {
572 dev_err(dev, "only VGA mode supported, currently\n");
573 return -EINVAL;
574 }
575
576 if (tve->mode == TVE_MODE_VGA) {
577 ret = of_property_read_u32(np, "fsl,hsync-pin",
578 &tve->di_hsync_pin);
579
580 if (ret < 0) {
581 dev_err(dev, "failed to get hsync pin\n");
582 return ret;
583 }
584
585 ret = of_property_read_u32(np, "fsl,vsync-pin",
586 &tve->di_vsync_pin);
587
588 if (ret < 0) {
589 dev_err(dev, "failed to get vsync pin\n");
590 return ret;
591 }
592 }
593
594 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
595 base = devm_ioremap_resource(dev, res);
596 if (IS_ERR(base))
597 return PTR_ERR(base);
598
599 tve_regmap_config.lock_arg = tve;
600 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
601 &tve_regmap_config);
602 if (IS_ERR(tve->regmap)) {
603 dev_err(dev, "failed to init regmap: %ld\n",
604 PTR_ERR(tve->regmap));
605 return PTR_ERR(tve->regmap);
606 }
607
608 irq = platform_get_irq(pdev, 0);
609 if (irq < 0) {
610 dev_err(dev, "failed to get irq\n");
611 return irq;
612 }
613
614 ret = devm_request_threaded_irq(dev, irq, NULL,
615 imx_tve_irq_handler, IRQF_ONESHOT,
616 "imx-tve", tve);
617 if (ret < 0) {
618 dev_err(dev, "failed to request irq: %d\n", ret);
619 return ret;
620 }
621
622 tve->dac_reg = devm_regulator_get(dev, "dac");
623 if (!IS_ERR(tve->dac_reg)) {
624 ret = regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
625 if (ret)
626 return ret;
627 ret = regulator_enable(tve->dac_reg);
628 if (ret)
629 return ret;
630 }
631
632 tve->clk = devm_clk_get(dev, "tve");
633 if (IS_ERR(tve->clk)) {
634 dev_err(dev, "failed to get high speed tve clock: %ld\n",
635 PTR_ERR(tve->clk));
636 return PTR_ERR(tve->clk);
637 }
638
639
640 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
641 if (IS_ERR(tve->di_sel_clk)) {
642 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
643 PTR_ERR(tve->di_sel_clk));
644 return PTR_ERR(tve->di_sel_clk);
645 }
646
647 ret = tve_clk_init(tve, base);
648 if (ret < 0)
649 return ret;
650
651 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
652 if (ret < 0) {
653 dev_err(dev, "failed to read configuration register: %d\n",
654 ret);
655 return ret;
656 }
657 if (val != 0x00100000) {
658 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
659 return -ENODEV;
660 }
661
662
663 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
664 if (ret)
665 return ret;
666
667 ret = imx_tve_register(drm, tve);
668 if (ret)
669 return ret;
670
671 dev_set_drvdata(dev, tve);
672
673 return 0;
674}
675
676static void imx_tve_unbind(struct device *dev, struct device *master,
677 void *data)
678{
679 struct imx_tve *tve = dev_get_drvdata(dev);
680
681 if (!IS_ERR(tve->dac_reg))
682 regulator_disable(tve->dac_reg);
683}
684
685static const struct component_ops imx_tve_ops = {
686 .bind = imx_tve_bind,
687 .unbind = imx_tve_unbind,
688};
689
690static int imx_tve_probe(struct platform_device *pdev)
691{
692 return component_add(&pdev->dev, &imx_tve_ops);
693}
694
695static int imx_tve_remove(struct platform_device *pdev)
696{
697 component_del(&pdev->dev, &imx_tve_ops);
698 return 0;
699}
700
701static const struct of_device_id imx_tve_dt_ids[] = {
702 { .compatible = "fsl,imx53-tve", },
703 { }
704};
705MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
706
707static struct platform_driver imx_tve_driver = {
708 .probe = imx_tve_probe,
709 .remove = imx_tve_remove,
710 .driver = {
711 .of_match_table = imx_tve_dt_ids,
712 .name = "imx-tve",
713 },
714};
715
716module_platform_driver(imx_tve_driver);
717
718MODULE_DESCRIPTION("i.MX Television Encoder driver");
719MODULE_AUTHOR("Philipp Zabel, Pengutronix");
720MODULE_LICENSE("GPL");
721MODULE_ALIAS("platform:imx-tve");
722
