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24#include "rootnv50.h"
25#include "dmacnv50.h"
26
27#include <core/client.h>
28#include <core/ramht.h>
29#include <subdev/timer.h>
30
31#include <nvif/class.h>
32#include <nvif/cl5070.h>
33#include <nvif/unpack.h>
34
35int
36gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0)
37{
38 struct nvkm_device *device = disp->base.engine.subdev.device;
39 const u32 total = nvkm_rd32(device, 0x640414 + (head * 0x300));
40 const u32 blanke = nvkm_rd32(device, 0x64041c + (head * 0x300));
41 const u32 blanks = nvkm_rd32(device, 0x640420 + (head * 0x300));
42 union {
43 struct nv50_disp_scanoutpos_v0 v0;
44 } *args = data;
45 int ret = -ENOSYS;
46
47 nvif_ioctl(object, "disp scanoutpos size %d\n", size);
48 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
49 nvif_ioctl(object, "disp scanoutpos vers %d\n",
50 args->v0.version);
51 args->v0.vblanke = (blanke & 0xffff0000) >> 16;
52 args->v0.hblanke = (blanke & 0x0000ffff);
53 args->v0.vblanks = (blanks & 0xffff0000) >> 16;
54 args->v0.hblanks = (blanks & 0x0000ffff);
55 args->v0.vtotal = ( total & 0xffff0000) >> 16;
56 args->v0.htotal = ( total & 0x0000ffff);
57 args->v0.time[0] = ktime_to_ns(ktime_get());
58 args->v0.vline =
59 nvkm_rd32(device, 0x616340 + (head * 0x800)) & 0xffff;
60 args->v0.time[1] = ktime_to_ns(ktime_get());
61 args->v0.hline =
62 nvkm_rd32(device, 0x616344 + (head * 0x800)) & 0xffff;
63 } else
64 return ret;
65
66 return 0;
67}
68
69void
70gf119_disp_root_fini(struct nv50_disp_root *root)
71{
72 struct nvkm_device *device = root->disp->base.engine.subdev.device;
73
74 nvkm_wr32(device, 0x6100b0, 0x00000000);
75}
76
77int
78gf119_disp_root_init(struct nv50_disp_root *root)
79{
80 struct nv50_disp *disp = root->disp;
81 struct nvkm_device *device = disp->base.engine.subdev.device;
82 u32 tmp;
83 int i;
84
85
86
87
88
89
90
91 for (i = 0; i < disp->base.head.nr; i++) {
92 tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));
93 nvkm_wr32(device, 0x6101b4 + (i * 0x800), tmp);
94 tmp = nvkm_rd32(device, 0x616108 + (i * 0x800));
95 nvkm_wr32(device, 0x6101b8 + (i * 0x800), tmp);
96 tmp = nvkm_rd32(device, 0x61610c + (i * 0x800));
97 nvkm_wr32(device, 0x6101bc + (i * 0x800), tmp);
98 }
99
100
101 for (i = 0; i < disp->func->dac.nr; i++) {
102 tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
103 nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp);
104 }
105
106
107 for (i = 0; i < disp->func->sor.nr; i++) {
108 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
109 nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp);
110 }
111
112
113 if (nvkm_rd32(device, 0x6100ac) & 0x00000100) {
114 nvkm_wr32(device, 0x6100ac, 0x00000100);
115 nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000);
116 if (nvkm_msec(device, 2000,
117 if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002))
118 break;
119 ) < 0)
120 return -EBUSY;
121 }
122
123
124 nvkm_wr32(device, 0x610010, (root->instmem->addr >> 8) | 9);
125
126
127 nvkm_wr32(device, 0x610090, 0x00000000);
128 nvkm_wr32(device, 0x6100a0, 0x00000000);
129 nvkm_wr32(device, 0x6100b0, 0x00000307);
130
131
132
133
134
135
136
137 for (i = 0; i < disp->base.head.nr; i++)
138 nvkm_mask(device, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);
139
140 return 0;
141}
142
143static const struct nv50_disp_root_func
144gf119_disp_root = {
145 .init = gf119_disp_root_init,
146 .fini = gf119_disp_root_fini,
147 .dmac = {
148 &gf119_disp_core_oclass,
149 &gf119_disp_base_oclass,
150 &gf119_disp_ovly_oclass,
151 },
152 .pioc = {
153 &gf119_disp_oimm_oclass,
154 &gf119_disp_curs_oclass,
155 },
156};
157
158static int
159gf119_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
160 void *data, u32 size, struct nvkm_object **pobject)
161{
162 return nv50_disp_root_new_(&gf119_disp_root, disp, oclass,
163 data, size, pobject);
164}
165
166const struct nvkm_disp_oclass
167gf119_disp_root_oclass = {
168 .base.oclass = GF110_DISP,
169 .base.minver = -1,
170 .base.maxver = -1,
171 .ctor = gf119_disp_root_new,
172};
173