1/* 2 * Copyright (C) 2015 Free Electrons 3 * Copyright (C) 2015 NextThing Co 4 * 5 * Boris Brezillon <boris.brezillon@free-electrons.com> 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 */ 13 14#ifndef __SUN4I_TCON_H__ 15#define __SUN4I_TCON_H__ 16 17#include <drm/drm_crtc.h> 18 19#include <linux/kernel.h> 20#include <linux/reset.h> 21 22#define SUN4I_TCON_GCTL_REG 0x0 23#define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31) 24#define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0) 25#define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0) 26#define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0) 27 28#define SUN4I_TCON_GINT0_REG 0x4 29#define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe)) 30#define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe)) 31 32#define SUN4I_TCON_GINT1_REG 0x8 33#define SUN4I_TCON_FRM_CTL_REG 0x10 34 35#define SUN4I_TCON0_CTL_REG 0x40 36#define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31) 37#define SUN4I_TCON0_CTL_CLK_DELAY_MASK GENMASK(8, 4) 38#define SUN4I_TCON0_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK) 39 40#define SUN4I_TCON0_DCLK_REG 0x44 41#define SUN4I_TCON0_DCLK_GATE_BIT (31) 42#define SUN4I_TCON0_DCLK_DIV_SHIFT (0) 43#define SUN4I_TCON0_DCLK_DIV_WIDTH (7) 44 45#define SUN4I_TCON0_BASIC0_REG 0x48 46#define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16) 47#define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff) 48 49#define SUN4I_TCON0_BASIC1_REG 0x4c 50#define SUN4I_TCON0_BASIC1_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16) 51#define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff) 52 53#define SUN4I_TCON0_BASIC2_REG 0x50 54#define SUN4I_TCON0_BASIC2_V_TOTAL(total) ((((total) * 2) & 0x1fff) << 16) 55#define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff) 56 57#define SUN4I_TCON0_BASIC3_REG 0x54 58#define SUN4I_TCON0_BASIC3_H_SYNC(width) ((((width) - 1) & 0x7ff) << 16) 59#define SUN4I_TCON0_BASIC3_V_SYNC(height) (((height) - 1) & 0x7ff) 60 61#define SUN4I_TCON0_HV_IF_REG 0x58 62#define SUN4I_TCON0_CPU_IF_REG 0x60 63#define SUN4I_TCON0_CPU_WR_REG 0x64 64#define SUN4I_TCON0_CPU_RD0_REG 0x68 65#define SUN4I_TCON0_CPU_RDA_REG 0x6c 66#define SUN4I_TCON0_TTL0_REG 0x70 67#define SUN4I_TCON0_TTL1_REG 0x74 68#define SUN4I_TCON0_TTL2_REG 0x78 69#define SUN4I_TCON0_TTL3_REG 0x7c 70#define SUN4I_TCON0_TTL4_REG 0x80 71#define SUN4I_TCON0_LVDS_IF_REG 0x84 72#define SUN4I_TCON0_IO_POL_REG 0x88 73#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28) 74#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25) 75#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24) 76 77#define SUN4I_TCON0_IO_TRI_REG 0x8c 78#define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE BIT(25) 79#define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE BIT(24) 80#define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins) GENMASK(pins, 0) 81 82#define SUN4I_TCON1_CTL_REG 0x90 83#define SUN4I_TCON1_CTL_TCON_ENABLE BIT(31) 84#define SUN4I_TCON1_CTL_INTERLACE_ENABLE BIT(20) 85#define SUN4I_TCON1_CTL_CLK_DELAY_MASK GENMASK(8, 4) 86#define SUN4I_TCON1_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK) 87 88#define SUN4I_TCON1_BASIC0_REG 0x94 89#define SUN4I_TCON1_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16) 90#define SUN4I_TCON1_BASIC0_Y(height) (((height) - 1) & 0xfff) 91 92#define SUN4I_TCON1_BASIC1_REG 0x98 93#define SUN4I_TCON1_BASIC1_X(width) ((((width) - 1) & 0xfff) << 16) 94#define SUN4I_TCON1_BASIC1_Y(height) (((height) - 1) & 0xfff) 95 96#define SUN4I_TCON1_BASIC2_REG 0x9c 97#define SUN4I_TCON1_BASIC2_X(width) ((((width) - 1) & 0xfff) << 16) 98#define SUN4I_TCON1_BASIC2_Y(height) (((height) - 1) & 0xfff) 99 100#define SUN4I_TCON1_BASIC3_REG 0xa0 101#define SUN4I_TCON1_BASIC3_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16) 102#define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp) (((bp) - 1) & 0xfff) 103 104#define SUN4I_TCON1_BASIC4_REG 0xa4 105#define SUN4I_TCON1_BASIC4_V_TOTAL(total) (((total) & 0x1fff) << 16) 106#define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp) (((bp) - 1) & 0xfff) 107 108#define SUN4I_TCON1_BASIC5_REG 0xa8 109#define SUN4I_TCON1_BASIC5_H_SYNC(width) ((((width) - 1) & 0x3ff) << 16) 110#define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff) 111 112#define SUN4I_TCON1_IO_POL_REG 0xf0 113#define SUN4I_TCON1_IO_TRI_REG 0xf4 114#define SUN4I_TCON_CEU_CTL_REG 0x100 115#define SUN4I_TCON_CEU_MUL_RR_REG 0x110 116#define SUN4I_TCON_CEU_MUL_RG_REG 0x114 117#define SUN4I_TCON_CEU_MUL_RB_REG 0x118 118#define SUN4I_TCON_CEU_ADD_RC_REG 0x11c 119#define SUN4I_TCON_CEU_MUL_GR_REG 0x120 120#define SUN4I_TCON_CEU_MUL_GG_REG 0x124 121#define SUN4I_TCON_CEU_MUL_GB_REG 0x128 122#define SUN4I_TCON_CEU_ADD_GC_REG 0x12c 123#define SUN4I_TCON_CEU_MUL_BR_REG 0x130 124#define SUN4I_TCON_CEU_MUL_BG_REG 0x134 125#define SUN4I_TCON_CEU_MUL_BB_REG 0x138 126#define SUN4I_TCON_CEU_ADD_BC_REG 0x13c 127#define SUN4I_TCON_CEU_RANGE_R_REG 0x140 128#define SUN4I_TCON_CEU_RANGE_G_REG 0x144 129#define SUN4I_TCON_CEU_RANGE_B_REG 0x148 130#define SUN4I_TCON_MUX_CTRL_REG 0x200 131#define SUN4I_TCON1_FILL_CTL_REG 0x300 132#define SUN4I_TCON1_FILL_BEG0_REG 0x304 133#define SUN4I_TCON1_FILL_END0_REG 0x308 134#define SUN4I_TCON1_FILL_DATA0_REG 0x30c 135#define SUN4I_TCON1_FILL_BEG1_REG 0x310 136#define SUN4I_TCON1_FILL_END1_REG 0x314 137#define SUN4I_TCON1_FILL_DATA1_REG 0x318 138#define SUN4I_TCON1_FILL_BEG2_REG 0x31c 139#define SUN4I_TCON1_FILL_END2_REG 0x320 140#define SUN4I_TCON1_FILL_DATA2_REG 0x324 141#define SUN4I_TCON1_GAMMA_TABLE_REG 0x400 142 143#define SUN4I_TCON_MAX_CHANNELS 2 144 145struct sun4i_tcon_quirks { 146 bool has_unknown_mux; /* sun5i has undocumented mux */ 147 bool has_channel_1; /* a33 does not have channel 1 */ 148}; 149 150struct sun4i_tcon { 151 struct device *dev; 152 struct drm_device *drm; 153 struct regmap *regs; 154 155 /* Main bus clock */ 156 struct clk *clk; 157 158 /* Clocks for the TCON channels */ 159 struct clk *sclk0; 160 struct clk *sclk1; 161 162 /* Pixel clock */ 163 struct clk *dclk; 164 165 /* Reset control */ 166 struct reset_control *lcd_rst; 167 168 struct drm_panel *panel; 169 170 /* Platform adjustments */ 171 const struct sun4i_tcon_quirks *quirks; 172}; 173 174struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node); 175struct drm_panel *sun4i_tcon_find_panel(struct device_node *node); 176 177/* Global Control */ 178void sun4i_tcon_disable(struct sun4i_tcon *tcon); 179void sun4i_tcon_enable(struct sun4i_tcon *tcon); 180 181/* Channel Control */ 182void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel); 183void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel); 184 185void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable); 186 187/* Mode Related Controls */ 188void sun4i_tcon_switch_interlace(struct sun4i_tcon *tcon, 189 bool enable); 190void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon, 191 struct drm_display_mode *mode); 192void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, 193 struct drm_display_mode *mode); 194 195#endif /* __SUN4I_TCON_H__ */ 196