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17#include <linux/device.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/regmap.h>
23#include <linux/spi/spi.h>
24#include <linux/sysfs.h>
25#include <linux/regulator/consumer.h>
26
27#include <linux/iio/iio.h>
28#include <linux/iio/sysfs.h>
29#include <linux/iio/buffer.h>
30#include <linux/iio/trigger.h>
31#include <linux/iio/triggered_buffer.h>
32#include <linux/iio/trigger_consumer.h>
33
34#include "afe440x.h"
35
36#define AFE4403_DRIVER_NAME "afe4403"
37
38
39#define AFE4403_TIAGAIN 0x20
40#define AFE4403_TIA_AMB_GAIN 0x21
41
42enum afe4403_fields {
43
44 F_RF_LED1, F_CF_LED1,
45 F_RF_LED, F_CF_LED,
46
47
48 F_ILED1, F_ILED2,
49
50
51 F_MAX_FIELDS
52};
53
54static const struct reg_field afe4403_reg_fields[] = {
55
56 [F_RF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 0, 2),
57 [F_CF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 3, 7),
58 [F_RF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 0, 2),
59 [F_CF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 3, 7),
60
61 [F_ILED1] = REG_FIELD(AFE440X_LEDCNTRL, 0, 7),
62 [F_ILED2] = REG_FIELD(AFE440X_LEDCNTRL, 8, 15),
63};
64
65
66
67
68
69
70
71
72
73
74
75struct afe4403_data {
76 struct device *dev;
77 struct spi_device *spi;
78 struct regmap *regmap;
79 struct regmap_field *fields[F_MAX_FIELDS];
80 struct regulator *regulator;
81 struct iio_trigger *trig;
82 int irq;
83};
84
85enum afe4403_chan_id {
86 LED2 = 1,
87 ALED2,
88 LED1,
89 ALED1,
90 LED2_ALED2,
91 LED1_ALED1,
92};
93
94static const unsigned int afe4403_channel_values[] = {
95 [LED2] = AFE440X_LED2VAL,
96 [ALED2] = AFE440X_ALED2VAL,
97 [LED1] = AFE440X_LED1VAL,
98 [ALED1] = AFE440X_ALED1VAL,
99 [LED2_ALED2] = AFE440X_LED2_ALED2VAL,
100 [LED1_ALED1] = AFE440X_LED1_ALED1VAL,
101};
102
103static const unsigned int afe4403_channel_leds[] = {
104 [LED2] = F_ILED2,
105 [LED1] = F_ILED1,
106};
107
108static const struct iio_chan_spec afe4403_channels[] = {
109
110 AFE440X_INTENSITY_CHAN(LED2, 0),
111 AFE440X_INTENSITY_CHAN(ALED2, 0),
112 AFE440X_INTENSITY_CHAN(LED1, 0),
113 AFE440X_INTENSITY_CHAN(ALED1, 0),
114 AFE440X_INTENSITY_CHAN(LED2_ALED2, 0),
115 AFE440X_INTENSITY_CHAN(LED1_ALED1, 0),
116
117 AFE440X_CURRENT_CHAN(LED2),
118 AFE440X_CURRENT_CHAN(LED1),
119};
120
121static const struct afe440x_val_table afe4403_res_table[] = {
122 { 500000 }, { 250000 }, { 100000 }, { 50000 },
123 { 25000 }, { 10000 }, { 1000000 }, { 0 },
124};
125AFE440X_TABLE_ATTR(in_intensity_resistance_available, afe4403_res_table);
126
127static const struct afe440x_val_table afe4403_cap_table[] = {
128 { 0, 5000 }, { 0, 10000 }, { 0, 20000 }, { 0, 25000 },
129 { 0, 30000 }, { 0, 35000 }, { 0, 45000 }, { 0, 50000 },
130 { 0, 55000 }, { 0, 60000 }, { 0, 70000 }, { 0, 75000 },
131 { 0, 80000 }, { 0, 85000 }, { 0, 95000 }, { 0, 100000 },
132 { 0, 155000 }, { 0, 160000 }, { 0, 170000 }, { 0, 175000 },
133 { 0, 180000 }, { 0, 185000 }, { 0, 195000 }, { 0, 200000 },
134 { 0, 205000 }, { 0, 210000 }, { 0, 220000 }, { 0, 225000 },
135 { 0, 230000 }, { 0, 235000 }, { 0, 245000 }, { 0, 250000 },
136};
137AFE440X_TABLE_ATTR(in_intensity_capacitance_available, afe4403_cap_table);
138
139static ssize_t afe440x_show_register(struct device *dev,
140 struct device_attribute *attr,
141 char *buf)
142{
143 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
144 struct afe4403_data *afe = iio_priv(indio_dev);
145 struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
146 unsigned int reg_val;
147 int vals[2];
148 int ret;
149
150 ret = regmap_field_read(afe->fields[afe440x_attr->field], ®_val);
151 if (ret)
152 return ret;
153
154 if (reg_val >= afe440x_attr->table_size)
155 return -EINVAL;
156
157 vals[0] = afe440x_attr->val_table[reg_val].integer;
158 vals[1] = afe440x_attr->val_table[reg_val].fract;
159
160 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
161}
162
163static ssize_t afe440x_store_register(struct device *dev,
164 struct device_attribute *attr,
165 const char *buf, size_t count)
166{
167 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
168 struct afe4403_data *afe = iio_priv(indio_dev);
169 struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
170 int val, integer, fract, ret;
171
172 ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
173 if (ret)
174 return ret;
175
176 for (val = 0; val < afe440x_attr->table_size; val++)
177 if (afe440x_attr->val_table[val].integer == integer &&
178 afe440x_attr->val_table[val].fract == fract)
179 break;
180 if (val == afe440x_attr->table_size)
181 return -EINVAL;
182
183 ret = regmap_field_write(afe->fields[afe440x_attr->field], val);
184 if (ret)
185 return ret;
186
187 return count;
188}
189
190static AFE440X_ATTR(in_intensity1_resistance, F_RF_LED, afe4403_res_table);
191static AFE440X_ATTR(in_intensity1_capacitance, F_CF_LED, afe4403_cap_table);
192
193static AFE440X_ATTR(in_intensity2_resistance, F_RF_LED, afe4403_res_table);
194static AFE440X_ATTR(in_intensity2_capacitance, F_CF_LED, afe4403_cap_table);
195
196static AFE440X_ATTR(in_intensity3_resistance, F_RF_LED1, afe4403_res_table);
197static AFE440X_ATTR(in_intensity3_capacitance, F_CF_LED1, afe4403_cap_table);
198
199static AFE440X_ATTR(in_intensity4_resistance, F_RF_LED1, afe4403_res_table);
200static AFE440X_ATTR(in_intensity4_capacitance, F_CF_LED1, afe4403_cap_table);
201
202static struct attribute *afe440x_attributes[] = {
203 &dev_attr_in_intensity_resistance_available.attr,
204 &dev_attr_in_intensity_capacitance_available.attr,
205 &afe440x_attr_in_intensity1_resistance.dev_attr.attr,
206 &afe440x_attr_in_intensity1_capacitance.dev_attr.attr,
207 &afe440x_attr_in_intensity2_resistance.dev_attr.attr,
208 &afe440x_attr_in_intensity2_capacitance.dev_attr.attr,
209 &afe440x_attr_in_intensity3_resistance.dev_attr.attr,
210 &afe440x_attr_in_intensity3_capacitance.dev_attr.attr,
211 &afe440x_attr_in_intensity4_resistance.dev_attr.attr,
212 &afe440x_attr_in_intensity4_capacitance.dev_attr.attr,
213 NULL
214};
215
216static const struct attribute_group afe440x_attribute_group = {
217 .attrs = afe440x_attributes
218};
219
220static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val)
221{
222 u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
223 u8 rx[3];
224 int ret;
225
226
227 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
228 if (ret)
229 return ret;
230
231 ret = spi_write_then_read(afe->spi, ®, 1, rx, 3);
232 if (ret)
233 return ret;
234
235 *val = (rx[0] << 16) |
236 (rx[1] << 8) |
237 (rx[2]);
238
239
240 tx[3] = AFE440X_CONTROL0_WRITE;
241 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
242 if (ret)
243 return ret;
244
245 return 0;
246}
247
248static int afe4403_read_raw(struct iio_dev *indio_dev,
249 struct iio_chan_spec const *chan,
250 int *val, int *val2, long mask)
251{
252 struct afe4403_data *afe = iio_priv(indio_dev);
253 unsigned int reg = afe4403_channel_values[chan->address];
254 unsigned int field = afe4403_channel_leds[chan->address];
255 int ret;
256
257 switch (chan->type) {
258 case IIO_INTENSITY:
259 switch (mask) {
260 case IIO_CHAN_INFO_RAW:
261 ret = afe4403_read(afe, reg, val);
262 if (ret)
263 return ret;
264 return IIO_VAL_INT;
265 }
266 break;
267 case IIO_CURRENT:
268 switch (mask) {
269 case IIO_CHAN_INFO_RAW:
270 ret = regmap_field_read(afe->fields[field], val);
271 if (ret)
272 return ret;
273 return IIO_VAL_INT;
274 case IIO_CHAN_INFO_SCALE:
275 *val = 0;
276 *val2 = 800000;
277 return IIO_VAL_INT_PLUS_MICRO;
278 }
279 break;
280 default:
281 break;
282 }
283
284 return -EINVAL;
285}
286
287static int afe4403_write_raw(struct iio_dev *indio_dev,
288 struct iio_chan_spec const *chan,
289 int val, int val2, long mask)
290{
291 struct afe4403_data *afe = iio_priv(indio_dev);
292 unsigned int field = afe4403_channel_leds[chan->address];
293
294 switch (chan->type) {
295 case IIO_CURRENT:
296 switch (mask) {
297 case IIO_CHAN_INFO_RAW:
298 return regmap_field_write(afe->fields[field], val);
299 }
300 break;
301 default:
302 break;
303 }
304
305 return -EINVAL;
306}
307
308static const struct iio_info afe4403_iio_info = {
309 .attrs = &afe440x_attribute_group,
310 .read_raw = afe4403_read_raw,
311 .write_raw = afe4403_write_raw,
312 .driver_module = THIS_MODULE,
313};
314
315static irqreturn_t afe4403_trigger_handler(int irq, void *private)
316{
317 struct iio_poll_func *pf = private;
318 struct iio_dev *indio_dev = pf->indio_dev;
319 struct afe4403_data *afe = iio_priv(indio_dev);
320 int ret, bit, i = 0;
321 s32 buffer[8];
322 u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
323 u8 rx[3];
324
325
326 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
327 if (ret)
328 goto err;
329
330 for_each_set_bit(bit, indio_dev->active_scan_mask,
331 indio_dev->masklength) {
332 ret = spi_write_then_read(afe->spi,
333 &afe4403_channel_values[bit], 1,
334 rx, 3);
335 if (ret)
336 goto err;
337
338 buffer[i++] = (rx[0] << 16) |
339 (rx[1] << 8) |
340 (rx[2]);
341 }
342
343
344 tx[3] = AFE440X_CONTROL0_WRITE;
345 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
346 if (ret)
347 goto err;
348
349 iio_push_to_buffers_with_timestamp(indio_dev, buffer, pf->timestamp);
350err:
351 iio_trigger_notify_done(indio_dev->trig);
352
353 return IRQ_HANDLED;
354}
355
356static const struct iio_trigger_ops afe4403_trigger_ops = {
357 .owner = THIS_MODULE,
358};
359
360#define AFE4403_TIMING_PAIRS \
361 { AFE440X_LED2STC, 0x000050 }, \
362 { AFE440X_LED2ENDC, 0x0003e7 }, \
363 { AFE440X_LED1LEDSTC, 0x0007d0 }, \
364 { AFE440X_LED1LEDENDC, 0x000bb7 }, \
365 { AFE440X_ALED2STC, 0x000438 }, \
366 { AFE440X_ALED2ENDC, 0x0007cf }, \
367 { AFE440X_LED1STC, 0x000820 }, \
368 { AFE440X_LED1ENDC, 0x000bb7 }, \
369 { AFE440X_LED2LEDSTC, 0x000000 }, \
370 { AFE440X_LED2LEDENDC, 0x0003e7 }, \
371 { AFE440X_ALED1STC, 0x000c08 }, \
372 { AFE440X_ALED1ENDC, 0x000f9f }, \
373 { AFE440X_LED2CONVST, 0x0003ef }, \
374 { AFE440X_LED2CONVEND, 0x0007cf }, \
375 { AFE440X_ALED2CONVST, 0x0007d7 }, \
376 { AFE440X_ALED2CONVEND, 0x000bb7 }, \
377 { AFE440X_LED1CONVST, 0x000bbf }, \
378 { AFE440X_LED1CONVEND, 0x009c3f }, \
379 { AFE440X_ALED1CONVST, 0x000fa7 }, \
380 { AFE440X_ALED1CONVEND, 0x001387 }, \
381 { AFE440X_ADCRSTSTCT0, 0x0003e8 }, \
382 { AFE440X_ADCRSTENDCT0, 0x0003eb }, \
383 { AFE440X_ADCRSTSTCT1, 0x0007d0 }, \
384 { AFE440X_ADCRSTENDCT1, 0x0007d3 }, \
385 { AFE440X_ADCRSTSTCT2, 0x000bb8 }, \
386 { AFE440X_ADCRSTENDCT2, 0x000bbb }, \
387 { AFE440X_ADCRSTSTCT3, 0x000fa0 }, \
388 { AFE440X_ADCRSTENDCT3, 0x000fa3 }, \
389 { AFE440X_PRPCOUNT, 0x009c3f }, \
390 { AFE440X_PDNCYCLESTC, 0x001518 }, \
391 { AFE440X_PDNCYCLEENDC, 0x00991f }
392
393static const struct reg_sequence afe4403_reg_sequences[] = {
394 AFE4403_TIMING_PAIRS,
395 { AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN },
396 { AFE4403_TIAGAIN, AFE440X_TIAGAIN_ENSEPGAIN },
397};
398
399static const struct regmap_range afe4403_yes_ranges[] = {
400 regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
401};
402
403static const struct regmap_access_table afe4403_volatile_table = {
404 .yes_ranges = afe4403_yes_ranges,
405 .n_yes_ranges = ARRAY_SIZE(afe4403_yes_ranges),
406};
407
408static const struct regmap_config afe4403_regmap_config = {
409 .reg_bits = 8,
410 .val_bits = 24,
411
412 .max_register = AFE440X_PDNCYCLEENDC,
413 .cache_type = REGCACHE_RBTREE,
414 .volatile_table = &afe4403_volatile_table,
415};
416
417static const struct of_device_id afe4403_of_match[] = {
418 { .compatible = "ti,afe4403", },
419 { }
420};
421MODULE_DEVICE_TABLE(of, afe4403_of_match);
422
423static int __maybe_unused afe4403_suspend(struct device *dev)
424{
425 struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
426 struct afe4403_data *afe = iio_priv(indio_dev);
427 int ret;
428
429 ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
430 AFE440X_CONTROL2_PDN_AFE,
431 AFE440X_CONTROL2_PDN_AFE);
432 if (ret)
433 return ret;
434
435 ret = regulator_disable(afe->regulator);
436 if (ret) {
437 dev_err(dev, "Unable to disable regulator\n");
438 return ret;
439 }
440
441 return 0;
442}
443
444static int __maybe_unused afe4403_resume(struct device *dev)
445{
446 struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
447 struct afe4403_data *afe = iio_priv(indio_dev);
448 int ret;
449
450 ret = regulator_enable(afe->regulator);
451 if (ret) {
452 dev_err(dev, "Unable to enable regulator\n");
453 return ret;
454 }
455
456 ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
457 AFE440X_CONTROL2_PDN_AFE, 0);
458 if (ret)
459 return ret;
460
461 return 0;
462}
463
464static SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend, afe4403_resume);
465
466static int afe4403_probe(struct spi_device *spi)
467{
468 struct iio_dev *indio_dev;
469 struct afe4403_data *afe;
470 int i, ret;
471
472 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*afe));
473 if (!indio_dev)
474 return -ENOMEM;
475
476 afe = iio_priv(indio_dev);
477 spi_set_drvdata(spi, indio_dev);
478
479 afe->dev = &spi->dev;
480 afe->spi = spi;
481 afe->irq = spi->irq;
482
483 afe->regmap = devm_regmap_init_spi(spi, &afe4403_regmap_config);
484 if (IS_ERR(afe->regmap)) {
485 dev_err(afe->dev, "Unable to allocate register map\n");
486 return PTR_ERR(afe->regmap);
487 }
488
489 for (i = 0; i < F_MAX_FIELDS; i++) {
490 afe->fields[i] = devm_regmap_field_alloc(afe->dev, afe->regmap,
491 afe4403_reg_fields[i]);
492 if (IS_ERR(afe->fields[i])) {
493 dev_err(afe->dev, "Unable to allocate regmap fields\n");
494 return PTR_ERR(afe->fields[i]);
495 }
496 }
497
498 afe->regulator = devm_regulator_get(afe->dev, "tx_sup");
499 if (IS_ERR(afe->regulator)) {
500 dev_err(afe->dev, "Unable to get regulator\n");
501 return PTR_ERR(afe->regulator);
502 }
503 ret = regulator_enable(afe->regulator);
504 if (ret) {
505 dev_err(afe->dev, "Unable to enable regulator\n");
506 return ret;
507 }
508
509 ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
510 AFE440X_CONTROL0_SW_RESET);
511 if (ret) {
512 dev_err(afe->dev, "Unable to reset device\n");
513 goto err_disable_reg;
514 }
515
516 ret = regmap_multi_reg_write(afe->regmap, afe4403_reg_sequences,
517 ARRAY_SIZE(afe4403_reg_sequences));
518 if (ret) {
519 dev_err(afe->dev, "Unable to set register defaults\n");
520 goto err_disable_reg;
521 }
522
523 indio_dev->modes = INDIO_DIRECT_MODE;
524 indio_dev->dev.parent = afe->dev;
525 indio_dev->channels = afe4403_channels;
526 indio_dev->num_channels = ARRAY_SIZE(afe4403_channels);
527 indio_dev->name = AFE4403_DRIVER_NAME;
528 indio_dev->info = &afe4403_iio_info;
529
530 if (afe->irq > 0) {
531 afe->trig = devm_iio_trigger_alloc(afe->dev,
532 "%s-dev%d",
533 indio_dev->name,
534 indio_dev->id);
535 if (!afe->trig) {
536 dev_err(afe->dev, "Unable to allocate IIO trigger\n");
537 ret = -ENOMEM;
538 goto err_disable_reg;
539 }
540
541 iio_trigger_set_drvdata(afe->trig, indio_dev);
542
543 afe->trig->ops = &afe4403_trigger_ops;
544 afe->trig->dev.parent = afe->dev;
545
546 ret = iio_trigger_register(afe->trig);
547 if (ret) {
548 dev_err(afe->dev, "Unable to register IIO trigger\n");
549 goto err_disable_reg;
550 }
551
552 ret = devm_request_threaded_irq(afe->dev, afe->irq,
553 iio_trigger_generic_data_rdy_poll,
554 NULL, IRQF_ONESHOT,
555 AFE4403_DRIVER_NAME,
556 afe->trig);
557 if (ret) {
558 dev_err(afe->dev, "Unable to request IRQ\n");
559 goto err_trig;
560 }
561 }
562
563 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
564 afe4403_trigger_handler, NULL);
565 if (ret) {
566 dev_err(afe->dev, "Unable to setup buffer\n");
567 goto err_trig;
568 }
569
570 ret = iio_device_register(indio_dev);
571 if (ret) {
572 dev_err(afe->dev, "Unable to register IIO device\n");
573 goto err_buff;
574 }
575
576 return 0;
577
578err_buff:
579 iio_triggered_buffer_cleanup(indio_dev);
580err_trig:
581 if (afe->irq > 0)
582 iio_trigger_unregister(afe->trig);
583err_disable_reg:
584 regulator_disable(afe->regulator);
585
586 return ret;
587}
588
589static int afe4403_remove(struct spi_device *spi)
590{
591 struct iio_dev *indio_dev = spi_get_drvdata(spi);
592 struct afe4403_data *afe = iio_priv(indio_dev);
593 int ret;
594
595 iio_device_unregister(indio_dev);
596
597 iio_triggered_buffer_cleanup(indio_dev);
598
599 if (afe->irq > 0)
600 iio_trigger_unregister(afe->trig);
601
602 ret = regulator_disable(afe->regulator);
603 if (ret) {
604 dev_err(afe->dev, "Unable to disable regulator\n");
605 return ret;
606 }
607
608 return 0;
609}
610
611static const struct spi_device_id afe4403_ids[] = {
612 { "afe4403", 0 },
613 { }
614};
615MODULE_DEVICE_TABLE(spi, afe4403_ids);
616
617static struct spi_driver afe4403_spi_driver = {
618 .driver = {
619 .name = AFE4403_DRIVER_NAME,
620 .of_match_table = afe4403_of_match,
621 .pm = &afe4403_pm_ops,
622 },
623 .probe = afe4403_probe,
624 .remove = afe4403_remove,
625 .id_table = afe4403_ids,
626};
627module_spi_driver(afe4403_spi_driver);
628
629MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
630MODULE_DESCRIPTION("TI AFE4403 Heart Rate Monitor and Pulse Oximeter AFE");
631MODULE_LICENSE("GPL v2");
632
