LXR linux/drivers/media/dvb-frontends/helene.c

   1/*
   2 * helene.c
   3 *
   4 * Sony HELENE DVB-S/S2 DVB-T/T2 DVB-C/C2 ISDB-T/S tuner driver (CXD2858ER)
   5 *
   6 * Copyright 2012 Sony Corporation
   7 * Copyright (C) 2014 NetUP Inc.
   8 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation; either version 2 of the License, or
  13 * (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19  */
  20
  21#include <linux/slab.h>
  22#include <linux/module.h>
  23#include <linux/dvb/frontend.h>
  24#include <linux/types.h>
  25#include "helene.h"
  26#include "dvb_frontend.h"
  27
  28#define MAX_WRITE_REGSIZE 20
  29
  30enum helene_state {
  31        STATE_UNKNOWN,
  32        STATE_SLEEP,
  33        STATE_ACTIVE
  34};
  35
  36struct helene_priv {
  37        u32                     frequency;
  38        u8                      i2c_address;
  39        struct i2c_adapter      *i2c;
  40        enum helene_state       state;
  41        void                    *set_tuner_data;
  42        int                     (*set_tuner)(void *, int);
  43        enum helene_xtal xtal;
  44};
  45
  46#define TERR_INTERNAL_LOOPFILTER_AVAILABLE(tv_system) \
  47        (((tv_system) != SONY_HELENE_DTV_DVBC_6) && \
  48         ((tv_system) != SONY_HELENE_DTV_DVBC_8)\
  49         && ((tv_system) != SONY_HELENE_DTV_DVBC2_6) && \
  50         ((tv_system) != SONY_HELENE_DTV_DVBC2_8))
  51
  52#define HELENE_AUTO             0xff
  53#define HELENE_OFFSET(ofs)      ((u8)(ofs) & 0x1F)
  54#define HELENE_BW_6             0x00
  55#define HELENE_BW_7             0x01
  56#define HELENE_BW_8             0x02
  57#define HELENE_BW_1_7           0x03
  58
  59enum helene_tv_system_t {
  60        SONY_HELENE_TV_SYSTEM_UNKNOWN,
  61        /* Terrestrial Analog */
  62        SONY_HELENE_ATV_MN_EIAJ,
  63        /**< System-M (Japan) (IF: Fp=5.75MHz in default) */
  64        SONY_HELENE_ATV_MN_SAP,
  65        /**< System-M (US)    (IF: Fp=5.75MHz in default) */
  66        SONY_HELENE_ATV_MN_A2,
  67        /**< System-M (Korea) (IF: Fp=5.9MHz in default) */
  68        SONY_HELENE_ATV_BG,
  69        /**< System-B/G       (IF: Fp=7.3MHz in default) */
  70        SONY_HELENE_ATV_I,
  71        /**< System-I         (IF: Fp=7.85MHz in default) */
  72        SONY_HELENE_ATV_DK,
  73        /**< System-D/K       (IF: Fp=7.85MHz in default) */
  74        SONY_HELENE_ATV_L,
  75        /**< System-L         (IF: Fp=7.85MHz in default) */
  76        SONY_HELENE_ATV_L_DASH,
  77        /**< System-L DASH    (IF: Fp=2.2MHz in default) */
  78        /* Terrestrial/Cable Digital */
  79        SONY_HELENE_DTV_8VSB,
  80        /**< ATSC 8VSB        (IF: Fc=3.7MHz in default) */
  81        SONY_HELENE_DTV_QAM,
  82        /**< US QAM           (IF: Fc=3.7MHz in default) */
  83        SONY_HELENE_DTV_ISDBT_6,
  84        /**< ISDB-T 6MHzBW    (IF: Fc=3.55MHz in default) */
  85        SONY_HELENE_DTV_ISDBT_7,
  86        /**< ISDB-T 7MHzBW    (IF: Fc=4.15MHz in default) */
  87        SONY_HELENE_DTV_ISDBT_8,
  88        /**< ISDB-T 8MHzBW    (IF: Fc=4.75MHz in default) */
  89        SONY_HELENE_DTV_DVBT_5,
  90        /**< DVB-T 5MHzBW     (IF: Fc=3.6MHz in default) */
  91        SONY_HELENE_DTV_DVBT_6,
  92        /**< DVB-T 6MHzBW     (IF: Fc=3.6MHz in default) */
  93        SONY_HELENE_DTV_DVBT_7,
  94        /**< DVB-T 7MHzBW     (IF: Fc=4.2MHz in default) */
  95        SONY_HELENE_DTV_DVBT_8,
  96        /**< DVB-T 8MHzBW     (IF: Fc=4.8MHz in default) */
  97        SONY_HELENE_DTV_DVBT2_1_7,
  98        /**< DVB-T2 1.7MHzBW  (IF: Fc=3.5MHz in default) */
  99        SONY_HELENE_DTV_DVBT2_5,
 100        /**< DVB-T2 5MHzBW    (IF: Fc=3.6MHz in default) */
 101        SONY_HELENE_DTV_DVBT2_6,
 102        /**< DVB-T2 6MHzBW    (IF: Fc=3.6MHz in default) */
 103        SONY_HELENE_DTV_DVBT2_7,
 104        /**< DVB-T2 7MHzBW    (IF: Fc=4.2MHz in default) */
 105        SONY_HELENE_DTV_DVBT2_8,
 106        /**< DVB-T2 8MHzBW    (IF: Fc=4.8MHz in default) */
 107        SONY_HELENE_DTV_DVBC_6,
 108        /**< DVB-C 6MHzBW     (IF: Fc=3.7MHz in default) */
 109        SONY_HELENE_DTV_DVBC_8,
 110        /**< DVB-C 8MHzBW     (IF: Fc=4.9MHz in default) */
 111        SONY_HELENE_DTV_DVBC2_6,
 112        /**< DVB-C2 6MHzBW    (IF: Fc=3.7MHz in default) */
 113        SONY_HELENE_DTV_DVBC2_8,
 114        /**< DVB-C2 8MHzBW    (IF: Fc=4.9MHz in default) */
 115        SONY_HELENE_DTV_DTMB,
 116        /**< DTMB             (IF: Fc=5.1MHz in default) */
 117        /* Satellite */
 118        SONY_HELENE_STV_ISDBS,
 119        /**< ISDB-S */
 120        SONY_HELENE_STV_DVBS,
 121        /**< DVB-S */
 122        SONY_HELENE_STV_DVBS2,
 123        /**< DVB-S2 */
 124
 125        SONY_HELENE_ATV_MIN = SONY_HELENE_ATV_MN_EIAJ,
 126        /**< Minimum analog terrestrial system */
 127        SONY_HELENE_ATV_MAX = SONY_HELENE_ATV_L_DASH,
 128        /**< Maximum analog terrestrial system */
 129        SONY_HELENE_DTV_MIN = SONY_HELENE_DTV_8VSB,
 130        /**< Minimum digital terrestrial system */
 131        SONY_HELENE_DTV_MAX = SONY_HELENE_DTV_DTMB,
 132        /**< Maximum digital terrestrial system */
 133        SONY_HELENE_TERR_TV_SYSTEM_NUM,
 134        /**< Number of supported terrestrial broadcasting system */
 135        SONY_HELENE_STV_MIN = SONY_HELENE_STV_ISDBS,
 136        /**< Minimum satellite system */
 137        SONY_HELENE_STV_MAX = SONY_HELENE_STV_DVBS2
 138        /**< Maximum satellite system */
 139};
 140
 141struct helene_terr_adjust_param_t {
 142        /* < Addr:0x69 Bit[6:4] : RFVGA gain.
 143         * 0xFF means Auto. (RF_GAIN_SEL = 1)
 144         */
 145        uint8_t RF_GAIN;
 146        /* < Addr:0x69 Bit[3:0] : IF_BPF gain.
 147        */
 148        uint8_t IF_BPF_GC;
 149        /* < Addr:0x6B Bit[3:0] : RF overload
 150         * RF input detect level. (FRF <= 172MHz)
 151        */
 152        uint8_t RFOVLD_DET_LV1_VL;
 153        /* < Addr:0x6B Bit[3:0] : RF overload
 154         * RF input detect level. (172MHz < FRF <= 464MHz)
 155        */
 156        uint8_t RFOVLD_DET_LV1_VH;
 157        /* < Addr:0x6B Bit[3:0] : RF overload
 158         * RF input detect level. (FRF > 464MHz)
 159        */
 160        uint8_t RFOVLD_DET_LV1_U;
 161        /* < Addr:0x6C Bit[2:0] :
 162         * Internal RFAGC detect level. (FRF <= 172MHz)
 163        */
 164        uint8_t IFOVLD_DET_LV_VL;
 165        /* < Addr:0x6C Bit[2:0] :
 166         * Internal RFAGC detect level. (172MHz < FRF <= 464MHz)
 167        */
 168        uint8_t IFOVLD_DET_LV_VH;
 169        /* < Addr:0x6C Bit[2:0] :
 170         * Internal RFAGC detect level. (FRF > 464MHz)
 171        */
 172        uint8_t IFOVLD_DET_LV_U;
 173        /* < Addr:0x6D Bit[5:4] :
 174         * IF filter center offset.
 175        */
 176        uint8_t IF_BPF_F0;
 177        /* < Addr:0x6D Bit[1:0] :
 178         * 6MHzBW(0x00) or 7MHzBW(0x01)
 179         * or 8MHzBW(0x02) or 1.7MHzBW(0x03)
 180        */
 181        uint8_t BW;
 182        /* < Addr:0x6E Bit[4:0] :
 183         * 5bit signed. IF offset (kHz) = FIF_OFFSET x 50
 184        */
 185        uint8_t FIF_OFFSET;
 186        /* < Addr:0x6F Bit[4:0] :
 187         * 5bit signed. BW offset (kHz) =
 188         * BW_OFFSET x 50 (BW_OFFSET x 10 in 1.7MHzBW)
 189        */
 190        uint8_t BW_OFFSET;
 191        /* < Addr:0x9C Bit[0]   :
 192         * Local polarity. (0: Upper Local, 1: Lower Local)
 193        */
 194        uint8_t IS_LOWERLOCAL;
 195};
 196
 197static const struct helene_terr_adjust_param_t
 198terr_params[SONY_HELENE_TERR_TV_SYSTEM_NUM] = {
 199        /*< SONY_HELENE_TV_SYSTEM_UNKNOWN */
 200        {HELENE_AUTO, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 201                HELENE_BW_6, HELENE_OFFSET(0),  HELENE_OFFSET(0),  0x00},
 202        /* Analog */
 203        /**< SONY_HELENE_ATV_MN_EIAJ   (System-M (Japan)) */
 204        {HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
 205                HELENE_BW_6,  HELENE_OFFSET(0),  HELENE_OFFSET(1),  0x00},
 206        /**< SONY_HELENE_ATV_MN_SAP    (System-M (US)) */
 207        {HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
 208                HELENE_BW_6,  HELENE_OFFSET(0),  HELENE_OFFSET(1),  0x00},
 209        {HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
 210                HELENE_BW_6,  HELENE_OFFSET(3),  HELENE_OFFSET(1),  0x00},
 211        /**< SONY_HELENE_ATV_MN_A2     (System-M (Korea)) */
 212        {HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
 213                HELENE_BW_7,  HELENE_OFFSET(11), HELENE_OFFSET(5),  0x00},
 214        /**< SONY_HELENE_ATV_BG        (System-B/G) */
 215        {HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
 216                HELENE_BW_8,  HELENE_OFFSET(2),  HELENE_OFFSET(-3), 0x00},
 217        /**< SONY_HELENE_ATV_I         (System-I) */
 218        {HELENE_AUTO, 0x05, 0x03, 0x06, 0x03, 0x01, 0x01, 0x01, 0x00,
 219                HELENE_BW_8,  HELENE_OFFSET(2),  HELENE_OFFSET(-3), 0x00},
 220        /**< SONY_HELENE_ATV_DK        (System-D/K) */
 221        {HELENE_AUTO, 0x03, 0x04, 0x0A, 0x04, 0x04, 0x04, 0x04, 0x00,
 222                HELENE_BW_8,  HELENE_OFFSET(2),  HELENE_OFFSET(-3), 0x00},
 223        /**< SONY_HELENE_ATV_L         (System-L) */
 224        {HELENE_AUTO, 0x03, 0x04, 0x0A, 0x04, 0x04, 0x04, 0x04, 0x00,
 225                HELENE_BW_8,  HELENE_OFFSET(-1), HELENE_OFFSET(4),  0x00},
 226        /**< SONY_HELENE_ATV_L_DASH    (System-L DASH) */
 227        /* Digital */
 228        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x03, 0x03, 0x03, 0x00,
 229                HELENE_BW_6,  HELENE_OFFSET(-6), HELENE_OFFSET(-3), 0x00},
 230        /**< SONY_HELENE_DTV_8VSB      (ATSC 8VSB) */
 231        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 232                HELENE_BW_6,  HELENE_OFFSET(-6), HELENE_OFFSET(-3), 0x00},
 233        /**< SONY_HELENE_DTV_QAM       (US QAM) */
 234        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 235                HELENE_BW_6,  HELENE_OFFSET(-9), HELENE_OFFSET(-5), 0x00},
 236        /**< SONY_HELENE_DTV_ISDBT_6   (ISDB-T 6MHzBW) */
 237        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 238                HELENE_BW_7,  HELENE_OFFSET(-7), HELENE_OFFSET(-6), 0x00},
 239        /**< SONY_HELENE_DTV_ISDBT_7   (ISDB-T 7MHzBW) */
 240        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 241                HELENE_BW_8,  HELENE_OFFSET(-5), HELENE_OFFSET(-7), 0x00},
 242        /**< SONY_HELENE_DTV_ISDBT_8   (ISDB-T 8MHzBW) */
 243        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 244                HELENE_BW_6,  HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
 245        /**< SONY_HELENE_DTV_DVBT_5    (DVB-T 5MHzBW) */
 246        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 247                HELENE_BW_6,  HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
 248        /**< SONY_HELENE_DTV_DVBT_6    (DVB-T 6MHzBW) */
 249        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 250                HELENE_BW_7,  HELENE_OFFSET(-6), HELENE_OFFSET(-5), 0x00},
 251        /**< SONY_HELENE_DTV_DVBT_7    (DVB-T 7MHzBW) */
 252        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 253                HELENE_BW_8,  HELENE_OFFSET(-4), HELENE_OFFSET(-6), 0x00},
 254        /**< SONY_HELENE_DTV_DVBT_8    (DVB-T 8MHzBW) */
 255        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 256                HELENE_BW_1_7, HELENE_OFFSET(-10), HELENE_OFFSET(-10), 0x00},
 257        /**< SONY_HELENE_DTV_DVBT2_1_7 (DVB-T2 1.7MHzBW) */
 258        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 259                HELENE_BW_6,  HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
 260        /**< SONY_HELENE_DTV_DVBT2_5   (DVB-T2 5MHzBW) */
 261        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 262                HELENE_BW_6,  HELENE_OFFSET(-8), HELENE_OFFSET(-3), 0x00},
 263        /**< SONY_HELENE_DTV_DVBT2_6   (DVB-T2 6MHzBW) */
 264        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 265                HELENE_BW_7,  HELENE_OFFSET(-6), HELENE_OFFSET(-5), 0x00},
 266        /**< SONY_HELENE_DTV_DVBT2_7   (DVB-T2 7MHzBW) */
 267        {HELENE_AUTO, 0x09, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 268                HELENE_BW_8,  HELENE_OFFSET(-4), HELENE_OFFSET(-6), 0x00},
 269        /**< SONY_HELENE_DTV_DVBT2_8   (DVB-T2 8MHzBW) */
 270        {HELENE_AUTO, 0x05, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x00,
 271                HELENE_BW_6,  HELENE_OFFSET(-6), HELENE_OFFSET(-4), 0x00},
 272        /**< SONY_HELENE_DTV_DVBC_6    (DVB-C 6MHzBW) */
 273        {HELENE_AUTO, 0x05, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x00,
 274                HELENE_BW_8,  HELENE_OFFSET(-2), HELENE_OFFSET(-3), 0x00},
 275        /**< SONY_HELENE_DTV_DVBC_8    (DVB-C 8MHzBW) */
 276        {HELENE_AUTO, 0x03, 0x09, 0x09, 0x09, 0x02, 0x02, 0x02, 0x00,
 277                HELENE_BW_6,  HELENE_OFFSET(-6), HELENE_OFFSET(-2), 0x00},
 278        /**< SONY_HELENE_DTV_DVBC2_6   (DVB-C2 6MHzBW) */
 279        {HELENE_AUTO, 0x03, 0x09, 0x09, 0x09, 0x02, 0x02, 0x02, 0x00,
 280                HELENE_BW_8,  HELENE_OFFSET(-2), HELENE_OFFSET(0),  0x00},
 281        /**< SONY_HELENE_DTV_DVBC2_8   (DVB-C2 8MHzBW) */
 282        {HELENE_AUTO, 0x04, 0x0B, 0x0B, 0x0B, 0x02, 0x02, 0x02, 0x00,
 283                HELENE_BW_8,  HELENE_OFFSET(2),  HELENE_OFFSET(1),  0x00}
 284        /**< SONY_HELENE_DTV_DTMB      (DTMB) */
 285};
 286
 287static void helene_i2c_debug(struct helene_priv *priv,
 288                u8 reg, u8 write, const u8 *data, u32 len)
 289{
 290        dev_dbg(&priv->i2c->dev, "helene: I2C %s reg 0x%02x size %d\n",
 291                        (write == 0 ? "read" : "write"), reg, len);
 292        print_hex_dump_bytes("helene: I2C data: ",
 293                        DUMP_PREFIX_OFFSET, data, len);
 294}
 295
 296static int helene_write_regs(struct helene_priv *priv,
 297                u8 reg, const u8 *data, u32 len)
 298{
 299        int ret;
 300        u8 buf[MAX_WRITE_REGSIZE + 1];
 301        struct i2c_msg msg[1] = {
 302                {
 303                        .addr = priv->i2c_address,
 304                        .flags = 0,
 305                        .len = len + 1,
 306                        .buf = buf,
 307                }
 308        };
 309
 310        if (len + 1 > sizeof(buf)) {
 311                dev_warn(&priv->i2c->dev,
 312                                "wr reg=%04x: len=%d vs %Zu is too big!\n",
 313                                reg, len + 1, sizeof(buf));
 314                return -E2BIG;
 315        }
 316
 317        helene_i2c_debug(priv, reg, 1, data, len);
 318        buf[0] = reg;
 319        memcpy(&buf[1], data, len);
 320        ret = i2c_transfer(priv->i2c, msg, 1);
 321        if (ret >= 0 && ret != 1)
 322                ret = -EREMOTEIO;
 323        if (ret < 0) {
 324                dev_warn(&priv->i2c->dev,
 325                                "%s: i2c wr failed=%d reg=%02x len=%d\n",
 326                                KBUILD_MODNAME, ret, reg, len);
 327                return ret;
 328        }
 329        return 0;
 330}
 331
 332static int helene_write_reg(struct helene_priv *priv, u8 reg, u8 val)
 333{
 334        return helene_write_regs(priv, reg, &val, 1);
 335}
 336
 337static int helene_read_regs(struct helene_priv *priv,
 338                u8 reg, u8 *val, u32 len)
 339{
 340        int ret;
 341        struct i2c_msg msg[2] = {
 342                {
 343                        .addr = priv->i2c_address,
 344                        .flags = 0,
 345                        .len = 1,
 346                        .buf = &reg,
 347                }, {
 348                        .addr = priv->i2c_address,
 349                        .flags = I2C_M_RD,
 350                        .len = len,
 351                        .buf = val,
 352                }
 353        };
 354
 355        ret = i2c_transfer(priv->i2c, &msg[0], 1);
 356        if (ret >= 0 && ret != 1)
 357                ret = -EREMOTEIO;
 358        if (ret < 0) {
 359                dev_warn(&priv->i2c->dev,
 360                                "%s: I2C rw failed=%d addr=%02x reg=%02x\n",
 361                                KBUILD_MODNAME, ret, priv->i2c_address, reg);
 362                return ret;
 363        }
 364        ret = i2c_transfer(priv->i2c, &msg[1], 1);
 365        if (ret >= 0 && ret != 1)
 366                ret = -EREMOTEIO;
 367        if (ret < 0) {
 368                dev_warn(&priv->i2c->dev,
 369                                "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 370                                KBUILD_MODNAME, ret, priv->i2c_address, reg);
 371                return ret;
 372        }
 373        helene_i2c_debug(priv, reg, 0, val, len);
 374        return 0;
 375}
 376
 377static int helene_read_reg(struct helene_priv *priv, u8 reg, u8 *val)
 378{
 379        return helene_read_regs(priv, reg, val, 1);
 380}
 381
 382static int helene_set_reg_bits(struct helene_priv *priv,
 383                u8 reg, u8 data, u8 mask)
 384{
 385        int res;
 386        u8 rdata;
 387
 388        if (mask != 0xff) {
 389                res = helene_read_reg(priv, reg, &rdata);
 390                if (res != 0)
 391                        return res;
 392                data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 393        }
 394        return helene_write_reg(priv, reg, data);
 395}
 396
 397static int helene_enter_power_save(struct helene_priv *priv)
 398{
 399        dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 400        if (priv->state == STATE_SLEEP)
 401                return 0;
 402
 403        /* Standby setting for CPU */
 404        helene_write_reg(priv, 0x88, 0x0);
 405
 406        /* Standby setting for internal logic block */
 407        helene_write_reg(priv, 0x87, 0xC0);
 408
 409        priv->state = STATE_SLEEP;
 410        return 0;
 411}
 412
 413static int helene_leave_power_save(struct helene_priv *priv)
 414{
 415        dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 416        if (priv->state == STATE_ACTIVE)
 417                return 0;
 418
 419        /* Standby setting for internal logic block */
 420        helene_write_reg(priv, 0x87, 0xC4);
 421
 422        /* Standby setting for CPU */
 423        helene_write_reg(priv, 0x88, 0x40);
 424
 425        priv->state = STATE_ACTIVE;
 426        return 0;
 427}
 428
 429static int helene_init(struct dvb_frontend *fe)
 430{
 431        struct helene_priv *priv = fe->tuner_priv;
 432
 433        dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 434        return helene_leave_power_save(priv);
 435}
 436
 437static void helene_release(struct dvb_frontend *fe)
 438{
 439        struct helene_priv *priv = fe->tuner_priv;
 440
 441        dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 442        kfree(fe->tuner_priv);
 443        fe->tuner_priv = NULL;
 444}
 445
 446static int helene_sleep(struct dvb_frontend *fe)
 447{
 448        struct helene_priv *priv = fe->tuner_priv;
 449
 450        dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 451        helene_enter_power_save(priv);
 452        return 0;
 453}
 454
 455static enum helene_tv_system_t helene_get_tv_system(struct dvb_frontend *fe)
 456{
 457        enum helene_tv_system_t system = SONY_HELENE_TV_SYSTEM_UNKNOWN;
 458        struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 459        struct helene_priv *priv = fe->tuner_priv;
 460
 461        if (p->delivery_system == SYS_DVBT) {
 462                if (p->bandwidth_hz <= 5000000)
 463                        system = SONY_HELENE_DTV_DVBT_5;
 464                else if (p->bandwidth_hz <= 6000000)
 465                        system = SONY_HELENE_DTV_DVBT_6;
 466                else if (p->bandwidth_hz <= 7000000)
 467                        system = SONY_HELENE_DTV_DVBT_7;
 468                else if (p->bandwidth_hz <= 8000000)
 469                        system = SONY_HELENE_DTV_DVBT_8;
 470                else {
 471                        system = SONY_HELENE_DTV_DVBT_8;
 472                        p->bandwidth_hz = 8000000;
 473                }
 474        } else if (p->delivery_system == SYS_DVBT2) {
 475                if (p->bandwidth_hz <= 5000000)
 476                        system = SONY_HELENE_DTV_DVBT2_5;
 477                else if (p->bandwidth_hz <= 6000000)
 478                        system = SONY_HELENE_DTV_DVBT2_6;
 479                else if (p->bandwidth_hz <= 7000000)
 480                        system = SONY_HELENE_DTV_DVBT2_7;
 481                else if (p->bandwidth_hz <= 8000000)
 482                        system = SONY_HELENE_DTV_DVBT2_8;
 483                else {
 484                        system = SONY_HELENE_DTV_DVBT2_8;
 485                        p->bandwidth_hz = 8000000;
 486                }
 487        } else if (p->delivery_system == SYS_DVBS) {
 488                system = SONY_HELENE_STV_DVBS;
 489        } else if (p->delivery_system == SYS_DVBS2) {
 490                system = SONY_HELENE_STV_DVBS2;
 491        } else if (p->delivery_system == SYS_ISDBS) {
 492                system = SONY_HELENE_STV_ISDBS;
 493        } else if (p->delivery_system == SYS_ISDBT) {
 494                if (p->bandwidth_hz <= 6000000)
 495                        system = SONY_HELENE_DTV_ISDBT_6;
 496                else if (p->bandwidth_hz <= 7000000)
 497                        system = SONY_HELENE_DTV_ISDBT_7;
 498                else if (p->bandwidth_hz <= 8000000)
 499                        system = SONY_HELENE_DTV_ISDBT_8;
 500                else {
 501                        system = SONY_HELENE_DTV_ISDBT_8;
 502                        p->bandwidth_hz = 8000000;
 503                }
 504        } else if (p->delivery_system == SYS_DVBC_ANNEX_A) {
 505                if (p->bandwidth_hz <= 6000000)
 506                        system = SONY_HELENE_DTV_DVBC_6;
 507                else if (p->bandwidth_hz <= 8000000)
 508                        system = SONY_HELENE_DTV_DVBC_8;
 509        }
 510        dev_dbg(&priv->i2c->dev,
 511                        "%s(): HELENE DTV system %d (delsys %d, bandwidth %d)\n",
 512                        __func__, (int)system, p->delivery_system,
 513                        p->bandwidth_hz);
 514        return system;
 515}
 516
 517static int helene_set_params_s(struct dvb_frontend *fe)
 518{
 519        u8 data[MAX_WRITE_REGSIZE];
 520        u32 frequency;
 521        enum helene_tv_system_t tv_system;
 522        struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 523        struct helene_priv *priv = fe->tuner_priv;
 524        int frequencykHz = p->frequency;
 525        uint32_t frequency4kHz = 0;
 526        u32 symbol_rate = p->symbol_rate/1000;
 527
 528        dev_dbg(&priv->i2c->dev, "%s(): tune frequency %dkHz sr=%uKsps\n",
 529                        __func__, frequencykHz, symbol_rate);
 530        tv_system = helene_get_tv_system(fe);
 531
 532        if (tv_system == SONY_HELENE_TV_SYSTEM_UNKNOWN) {
 533                dev_err(&priv->i2c->dev, "%s(): unknown DTV system\n",
 534                                __func__);
 535                return -EINVAL;
 536        }
 537        /* RF switch turn to satellite */
 538        if (priv->set_tuner)
 539                priv->set_tuner(priv->set_tuner_data, 0);
 540        frequency = roundup(p->frequency / 1000, 1);
 541
 542        /* Disable IF signal output */
 543        helene_write_reg(priv, 0x15, 0x02);
 544
 545        /* RFIN matching in power save (Sat) reset */
 546        helene_write_reg(priv, 0x43, 0x06);
 547
 548        /* Analog block setting (0x6A, 0x6B) */
 549        data[0] = 0x00;
 550        data[1] = 0x00;
 551        helene_write_regs(priv, 0x6A, data, 2);
 552        helene_write_reg(priv, 0x75, 0x99);
 553        helene_write_reg(priv, 0x9D, 0x00);
 554
 555        /* Tuning setting for CPU (0x61) */
 556        helene_write_reg(priv, 0x61, 0x07);
 557
 558        /* Satellite mode select (0x01) */
 559        helene_write_reg(priv, 0x01, 0x01);
 560
 561        /* Clock enable for internal logic block, CPU wake-up (0x04, 0x05) */
 562        data[0] = 0xC4;
 563        data[1] = 0x40;
 564
 565        switch (priv->xtal) {
 566        case SONY_HELENE_XTAL_16000:
 567                data[2] = 0x02;
 568                break;
 569        case SONY_HELENE_XTAL_20500:
 570                data[2] = 0x02;
 571                break;
 572        case SONY_HELENE_XTAL_24000:
 573                data[2] = 0x03;
 574                break;
 575        case SONY_HELENE_XTAL_41000:
 576                data[2] = 0x05;
 577                break;
 578        default:
 579                dev_err(&priv->i2c->dev, "%s(): unknown xtal %d\n",
 580                                __func__, priv->xtal);
 581                return -EINVAL;
 582        }
 583
 584        /* Setting for analog block (0x07). LOOPFILTER INTERNAL */
 585        data[3] = 0x80;
 586
 587        /* Tuning setting for analog block
 588         * (0x08, 0x09, 0x0A, 0x0B). LOOPFILTER INTERNAL
 589        */
 590        if (priv->xtal == SONY_HELENE_XTAL_20500)
 591                data[4] = 0x58;
 592        else
 593                data[4] = 0x70;
 594
 595        data[5] = 0x1E;
 596        data[6] = 0x02;
 597        data[7] = 0x24;
 598
 599        /* Enable for analog block (0x0C, 0x0D, 0x0E). SAT LNA ON */
 600        data[8] = 0x0F;
 601        data[8] |= 0xE0; /* POWERSAVE_TERR_RF_ACTIVE */
 602        data[9]  = 0x02;
 603        data[10] = 0x1E;
 604
 605        /* Setting for LPF cutoff frequency (0x0F) */
 606        switch (tv_system) {
 607        case SONY_HELENE_STV_ISDBS:
 608                data[11] = 0x22; /* 22MHz */
 609                break;
 610        case SONY_HELENE_STV_DVBS:
 611                if (symbol_rate <= 4000)
 612                        data[11] = 0x05;
 613                else if (symbol_rate <= 10000)
 614                        data[11] = (uint8_t)((symbol_rate * 47
 615                                                + (40000-1)) / 40000);
 616                else
 617                        data[11] = (uint8_t)((symbol_rate * 27
 618                                                + (40000-1)) / 40000 + 5);
 619
 620                if (data[11] > 36)
 621                        data[11] = 36; /* 5 <= lpf_cutoff <= 36 is valid */
 622                break;
 623        case SONY_HELENE_STV_DVBS2:
 624                if (symbol_rate <= 4000)
 625                        data[11] = 0x05;
 626                else if (symbol_rate <= 10000)
 627                        data[11] = (uint8_t)((symbol_rate * 11
 628                                                + (10000-1)) / 10000);
 629                else
 630                        data[11] = (uint8_t)((symbol_rate * 3
 631                                                + (5000-1)) / 5000 + 5);
 632
 633                if (data[11] > 36)
 634                        data[11] = 36; /* 5 <= lpf_cutoff <= 36 is valid */
 635                break;
 636        default:
 637                dev_err(&priv->i2c->dev, "%s(): unknown standard %d\n",
 638                                __func__, tv_system);
 639                return -EINVAL;
 640        }
 641
 642        /* RF tuning frequency setting (0x10, 0x11, 0x12) */
 643        frequency4kHz = (frequencykHz + 2) / 4;
 644        data[12] = (uint8_t)(frequency4kHz & 0xFF);         /* FRF_L */
 645        data[13] = (uint8_t)((frequency4kHz >> 8) & 0xFF);  /* FRF_M */
 646        /* FRF_H (bit[3:0]) */
 647        data[14] = (uint8_t)((frequency4kHz >> 16) & 0x0F);
 648
 649        /* Tuning command (0x13) */
 650        data[15] = 0xFF;
 651
 652        /* Setting for IQOUT_LIMIT (0x14) 0.75Vpp */
 653        data[16] = 0x00;
 654
 655        /* Enable IQ output (0x15) */
 656        data[17] = 0x01;
 657
 658        helene_write_regs(priv, 0x04, data, 18);
 659
 660        dev_dbg(&priv->i2c->dev, "%s(): tune done\n",
 661                        __func__);
 662
 663        priv->frequency = frequency;
 664        return 0;
 665}
 666
 667static int helene_set_params(struct dvb_frontend *fe)
 668{
 669        u8 data[MAX_WRITE_REGSIZE];
 670        u32 frequency;
 671        enum helene_tv_system_t tv_system;
 672        struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 673        struct helene_priv *priv = fe->tuner_priv;
 674        int frequencykHz = p->frequency / 1000;
 675
 676        dev_dbg(&priv->i2c->dev, "%s(): tune frequency %dkHz\n",
 677                        __func__, frequencykHz);
 678        tv_system = helene_get_tv_system(fe);
 679
 680        if (tv_system == SONY_HELENE_TV_SYSTEM_UNKNOWN) {
 681                dev_dbg(&priv->i2c->dev, "%s(): unknown DTV system\n",
 682                                __func__);
 683                return -EINVAL;
 684        }
 685        if (priv->set_tuner)
 686                priv->set_tuner(priv->set_tuner_data, 1);
 687        frequency = roundup(p->frequency / 1000, 25);
 688
 689        /* mode select */
 690        helene_write_reg(priv, 0x01, 0x00);
 691
 692        /* Disable IF signal output */
 693        helene_write_reg(priv, 0x74, 0x02);
 694
 695        if (priv->state == STATE_SLEEP)
 696                helene_leave_power_save(priv);
 697
 698        /* Initial setting for internal analog block (0x91, 0x92) */
 699        if ((tv_system == SONY_HELENE_DTV_DVBC_6) ||
 700                        (tv_system == SONY_HELENE_DTV_DVBC_8)) {
 701                data[0] = 0x16;
 702                data[1] = 0x26;
 703        } else {
 704                data[0] = 0x10;
 705                data[1] = 0x20;
 706        }
 707        helene_write_regs(priv, 0x91, data, 2);
 708
 709        /* Setting for analog block */
 710        if (TERR_INTERNAL_LOOPFILTER_AVAILABLE(tv_system))
 711                data[0] = 0x90;
 712        else
 713                data[0] = 0x00;
 714
 715        /* Setting for local polarity (0x9D) */
 716        data[1] = (uint8_t)(terr_params[tv_system].IS_LOWERLOCAL & 0x01);
 717        helene_write_regs(priv, 0x9C, data, 2);
 718
 719        /* Enable for analog block */
 720        data[0] = 0xEE;
 721        data[1] = 0x02;
 722        data[2] = 0x1E;
 723        data[3] = 0x67; /* Tuning setting for CPU */
 724
 725        /* Setting for PLL reference divider for xtal=24MHz */
 726        if ((tv_system == SONY_HELENE_DTV_DVBC_6) ||
 727                        (tv_system == SONY_HELENE_DTV_DVBC_8))
 728                data[4] = 0x18;
 729        else
 730                data[4] = 0x03;
 731
 732        /* Tuning setting for analog block */
 733        if (TERR_INTERNAL_LOOPFILTER_AVAILABLE(tv_system)) {
 734                data[5] = 0x38;
 735                data[6] = 0x1E;
 736                data[7] = 0x02;
 737                data[8] = 0x24;
 738        } else if ((tv_system == SONY_HELENE_DTV_DVBC_6) ||
 739                        (tv_system == SONY_HELENE_DTV_DVBC_8)) {
 740                data[5] = 0x1C;
 741                data[6] = 0x78;
 742                data[7] = 0x08;
 743                data[8] = 0x1C;
 744        } else {
 745                data[5] = 0xB4;
 746                data[6] = 0x78;
 747                data[7] = 0x08;
 748                data[8] = 0x30;
 749        }
 750        helene_write_regs(priv, 0x5E, data, 9);
 751
 752        /* LT_AMP_EN should be 0 */
 753        helene_set_reg_bits(priv, 0x67, 0x0, 0x02);
 754
 755        /* Setting for IFOUT_LIMIT */
 756        data[0] = 0x00; /* 1.5Vpp */
 757
 758        /* RF_GAIN setting */
 759        if (terr_params[tv_system].RF_GAIN == HELENE_AUTO)
 760                data[1] = 0x80; /* RF_GAIN_SEL = 1 */
 761        else
 762                data[1] = (uint8_t)((terr_params[tv_system].RF_GAIN
 763                                        << 4) & 0x70);
 764
 765        /* IF_BPF_GC setting */
 766        data[1] |= (uint8_t)(terr_params[tv_system].IF_BPF_GC & 0x0F);
 767
 768        /* Setting for internal RFAGC (0x6A, 0x6B, 0x6C) */
 769        data[2] = 0x00;
 770        if (frequencykHz <= 172000) {
 771                data[3] = (uint8_t)(terr_params[tv_system].RFOVLD_DET_LV1_VL
 772                                & 0x0F);
 773                data[4] = (uint8_t)(terr_params[tv_system].IFOVLD_DET_LV_VL
 774                                & 0x07);
 775        } else if (frequencykHz <= 464000) {
 776                data[3] = (uint8_t)(terr_params[tv_system].RFOVLD_DET_LV1_VH
 777                                & 0x0F);
 778                data[4] = (uint8_t)(terr_params[tv_system].IFOVLD_DET_LV_VH
 779                                & 0x07);
 780        } else {
 781                data[3] = (uint8_t)(terr_params[tv_system].RFOVLD_DET_LV1_U
 782                                & 0x0F);
 783                data[4] = (uint8_t)(terr_params[tv_system].IFOVLD_DET_LV_U
 784                                & 0x07);
 785        }
 786        data[4] |= 0x20;
 787
 788        /* Setting for IF frequency and bandwidth */
 789
 790        /* IF filter center frequency offset (IF_BPF_F0) (0x6D) */
 791        data[5] = (uint8_t)((terr_params[tv_system].IF_BPF_F0 << 4) & 0x30);
 792
 793        /* IF filter band width (BW) (0x6D) */
 794        data[5] |= (uint8_t)(terr_params[tv_system].BW & 0x03);
 795
 796        /* IF frequency offset value (FIF_OFFSET) (0x6E) */
 797        data[6] = (uint8_t)(terr_params[tv_system].FIF_OFFSET & 0x1F);
 798
 799        /* IF band width offset value (BW_OFFSET) (0x6F) */
 800        data[7] = (uint8_t)(terr_params[tv_system].BW_OFFSET & 0x1F);
 801
 802        /* RF tuning frequency setting (0x70, 0x71, 0x72) */
 803        data[8]  = (uint8_t)(frequencykHz & 0xFF);         /* FRF_L */
 804        data[9]  = (uint8_t)((frequencykHz >> 8) & 0xFF);  /* FRF_M */
 805        data[10] = (uint8_t)((frequencykHz >> 16)
 806                        & 0x0F); /* FRF_H (bit[3:0]) */
 807
 808        /* Tuning command */
 809        data[11] = 0xFF;
 810
 811        /* Enable IF output, AGC and IFOUT pin selection (0x74) */
 812        data[12] = 0x01;
 813
 814        if ((tv_system == SONY_HELENE_DTV_DVBC_6) ||
 815                        (tv_system == SONY_HELENE_DTV_DVBC_8)) {
 816                data[13] = 0xD9;
 817                data[14] = 0x0F;
 818                data[15] = 0x24;
 819                data[16] = 0x87;
 820        } else {
 821                data[13] = 0x99;
 822                data[14] = 0x00;
 823                data[15] = 0x24;
 824                data[16] = 0x87;
 825        }
 826
 827        helene_write_regs(priv, 0x68, data, 17);
 828
 829        dev_dbg(&priv->i2c->dev, "%s(): tune done\n",
 830                        __func__);
 831
 832        priv->frequency = frequency;
 833        return 0;
 834}
 835
 836static int helene_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 837{
 838        struct helene_priv *priv = fe->tuner_priv;
 839
 840        *frequency = priv->frequency * 1000;
 841        return 0;
 842}
 843
 844static const struct dvb_tuner_ops helene_tuner_ops = {
 845        .info = {
 846                .name = "Sony HELENE Ter tuner",
 847                .frequency_min = 1000000,
 848                .frequency_max = 1200000000,
 849                .frequency_step = 25000,
 850        },
 851        .init = helene_init,
 852        .release = helene_release,
 853        .sleep = helene_sleep,
 854        .set_params = helene_set_params,
 855        .get_frequency = helene_get_frequency,
 856};
 857
 858static const struct dvb_tuner_ops helene_tuner_ops_s = {
 859        .info = {
 860                .name = "Sony HELENE Sat tuner",
 861                .frequency_min = 500000,
 862                .frequency_max = 2500000,
 863                .frequency_step = 1000,
 864        },
 865        .init = helene_init,
 866        .release = helene_release,
 867        .sleep = helene_sleep,
 868        .set_params = helene_set_params_s,
 869        .get_frequency = helene_get_frequency,
 870};
 871
 872/* power-on tuner
 873 * call once after reset
 874 */
 875static int helene_x_pon(struct helene_priv *priv)
 876{
 877        /* RFIN matching in power save (terrestrial) = ACTIVE */
 878        /* RFIN matching in power save (satellite) = ACTIVE */
 879        u8 dataT[] = { 0x06, 0x00, 0x02, 0x00 };
 880        /* SAT_RF_ACTIVE = true, lnaOff = false, terrRfActive = true */
 881        u8 dataS[] = { 0x05, 0x06 };
 882        u8 cdata[] = {0x7A, 0x01};
 883        u8 data[20];
 884        u8 rdata[2];
 885
 886        /* mode select */
 887        helene_write_reg(priv, 0x01, 0x00);
 888
 889        helene_write_reg(priv, 0x67, dataT[3]);
 890        helene_write_reg(priv, 0x43, dataS[1]);
 891        helene_write_regs(priv, 0x5E, dataT, 3);
 892        helene_write_reg(priv, 0x0C, dataS[0]);
 893
 894        /* Initial setting for internal logic block */
 895        helene_write_regs(priv, 0x99, cdata, sizeof(cdata));
 896
 897        /* 0x81 - 0x94 */
 898        data[0] = 0x18; /* xtal 24 MHz */
 899        data[1] = (uint8_t)(0x80 | (0x04 & 0x1F)); /* 4 x 25 = 100uA */
 900        data[2] = (uint8_t)(0x80 | (0x26 & 0x7F)); /* 38 x 0.25 = 9.5pF */
 901        data[3] = 0x80; /* REFOUT signal output 500mVpp */
 902        data[4] = 0x00; /* GPIO settings */
 903        data[5] = 0x00; /* GPIO settings */
 904        data[6] = 0xC4; /* Clock enable for internal logic block */
 905        data[7] = 0x40; /* Start CPU boot-up */
 906        data[8] = 0x10; /* For burst-write */
 907
 908        /* Setting for internal RFAGC */
 909        data[9] = 0x00;
 910        data[10] = 0x45;
 911        data[11] = 0x75;
 912
 913        data[12] = 0x07; /* Setting for analog block */
 914
 915        /* Initial setting for internal analog block */
 916        data[13] = 0x1C;
 917        data[14] = 0x3F;
 918        data[15] = 0x02;
 919        data[16] = 0x10;
 920        data[17] = 0x20;
 921        data[18] = 0x0A;
 922        data[19] = 0x00;
 923
 924        helene_write_regs(priv, 0x81, data, sizeof(data));
 925
 926        /* Setting for internal RFAGC */
 927        helene_write_reg(priv, 0x9B, 0x00);
 928
 929        msleep(20);
 930
 931        /* Check CPU_STT/CPU_ERR */
 932        helene_read_regs(priv, 0x1A, rdata, sizeof(rdata));
 933
 934        if (rdata[0] != 0x00) {
 935                dev_err(&priv->i2c->dev,
 936                                "HELENE tuner CPU error 0x%x\n", rdata[0]);
 937                return -EIO;
 938        }
 939
 940        /* VCO current setting */
 941        cdata[0] = 0x90;
 942        cdata[1] = 0x06;
 943        helene_write_regs(priv, 0x17, cdata, sizeof(cdata));
 944        msleep(20);
 945        helene_read_reg(priv, 0x19, data);
 946        helene_write_reg(priv, 0x95, (uint8_t)((data[0] >> 4) & 0x0F));
 947
 948        /* Disable IF signal output */
 949        helene_write_reg(priv, 0x74, 0x02);
 950
 951        /* Standby setting for CPU */
 952        helene_write_reg(priv, 0x88, 0x00);
 953
 954        /* Standby setting for internal logic block */
 955        helene_write_reg(priv, 0x87, 0xC0);
 956
 957        /* Load capacitance control setting for crystal oscillator */
 958        helene_write_reg(priv, 0x80, 0x01);
 959
 960        /* Satellite initial setting */
 961        cdata[0] = 0x07;
 962        cdata[1] = 0x00;
 963        helene_write_regs(priv, 0x41, cdata, sizeof(cdata));
 964
 965        dev_info(&priv->i2c->dev,
 966                        "HELENE tuner x_pon done\n");
 967
 968        return 0;
 969}
 970
 971struct dvb_frontend *helene_attach_s(struct dvb_frontend *fe,
 972                const struct helene_config *config,
 973                struct i2c_adapter *i2c)
 974{
 975        struct helene_priv *priv = NULL;
 976
 977        priv = kzalloc(sizeof(struct helene_priv), GFP_KERNEL);
 978        if (priv == NULL)
 979                return NULL;
 980        priv->i2c_address = (config->i2c_address >> 1);
 981        priv->i2c = i2c;
 982        priv->set_tuner_data = config->set_tuner_priv;
 983        priv->set_tuner = config->set_tuner_callback;
 984        priv->xtal = config->xtal;
 985
 986        if (fe->ops.i2c_gate_ctrl)
 987                fe->ops.i2c_gate_ctrl(fe, 1);
 988
 989        if (helene_x_pon(priv) != 0) {
 990                kfree(priv);
 991                return NULL;
 992        }
 993
 994        if (fe->ops.i2c_gate_ctrl)
 995                fe->ops.i2c_gate_ctrl(fe, 0);
 996
 997        memcpy(&fe->ops.tuner_ops, &helene_tuner_ops_s,
 998                        sizeof(struct dvb_tuner_ops));
 999        fe->tuner_priv = priv;
1000        dev_info(&priv->i2c->dev,

1001                        "Sony HELENE Sat attached on addr=%x at I2C adapter %p\n",
1002                        priv->i2c_address, priv->i2c);
1003        return fe;
1004}
1005EXPORT_SYMBOL(helene_attach_s);
1006
1007struct dvb_frontend *helene_attach(struct dvb_frontend *fe,
1008                const struct helene_config *config,
1009                struct i2c_adapter *i2c)
1010{
1011        struct helene_priv *priv = NULL;
1012
1013        priv = kzalloc(sizeof(struct helene_priv), GFP_KERNEL);
1014        if (priv == NULL)
1015                return NULL;
1016        priv->i2c_address = (config->i2c_address >> 1);
1017        priv->i2c = i2c;
1018        priv->set_tuner_data = config->set_tuner_priv;
1019        priv->set_tuner = config->set_tuner_callback;
1020        priv->xtal = config->xtal;
1021
1022        if (fe->ops.i2c_gate_ctrl)
1023                fe->ops.i2c_gate_ctrl(fe, 1);
1024
1025        if (helene_x_pon(priv) != 0) {
1026                kfree(priv);
1027                return NULL;
1028        }
1029
1030        if (fe->ops.i2c_gate_ctrl)
1031                fe->ops.i2c_gate_ctrl(fe, 0);
1032
1033        memcpy(&fe->ops.tuner_ops, &helene_tuner_ops,
1034                        sizeof(struct dvb_tuner_ops));
1035        fe->tuner_priv = priv;
1036        dev_info(&priv->i2c->dev,
1037                        "Sony HELENE Ter attached on addr=%x at I2C adapter %p\n",
1038                        priv->i2c_address, priv->i2c);
1039        return fe;
1040}
1041EXPORT_SYMBOL(helene_attach);
1042
1043MODULE_DESCRIPTION("Sony HELENE Sat/Ter tuner driver");
1044MODULE_AUTHOR("Abylay Ospan <aospan@netup.ru>");
1045MODULE_LICENSE("GPL");
1046