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22#ifndef __XGENE_ENET_MAIN_H__
23#define __XGENE_ENET_MAIN_H__
24
25#include <linux/acpi.h>
26#include <linux/clk.h>
27#include <linux/efi.h>
28#include <linux/irq.h>
29#include <linux/io.h>
30#include <linux/of_platform.h>
31#include <linux/of_net.h>
32#include <linux/of_mdio.h>
33#include <linux/module.h>
34#include <net/ip.h>
35#include <linux/prefetch.h>
36#include <linux/if_vlan.h>
37#include <linux/phy.h>
38#include "xgene_enet_hw.h"
39#include "xgene_enet_cle.h"
40#include "xgene_enet_ring2.h"
41#include "../../../phy/mdio-xgene.h"
42
43#define XGENE_DRV_VERSION "v1.0"
44#define XGENE_ENET_STD_MTU 1536
45#define XGENE_ENET_MAX_MTU 9600
46#define SKB_BUFFER_SIZE (XGENE_ENET_STD_MTU - NET_IP_ALIGN)
47
48#define BUFLEN_16K (16 * 1024)
49#define NUM_PKT_BUF 1024
50#define NUM_BUFPOOL 32
51#define NUM_NXTBUFPOOL 8
52#define MAX_EXP_BUFFS 256
53#define NUM_MSS_REG 4
54#define XGENE_MIN_ENET_FRAME_SIZE 60
55
56#define XGENE_MAX_ENET_IRQ 16
57#define XGENE_NUM_RX_RING 8
58#define XGENE_NUM_TX_RING 8
59#define XGENE_NUM_TXC_RING 8
60
61#define START_CPU_BUFNUM_0 0
62#define START_ETH_BUFNUM_0 2
63#define START_BP_BUFNUM_0 0x22
64#define START_RING_NUM_0 8
65#define START_CPU_BUFNUM_1 12
66#define START_ETH_BUFNUM_1 10
67#define START_BP_BUFNUM_1 0x2A
68#define START_RING_NUM_1 264
69
70#define XG_START_CPU_BUFNUM_1 12
71#define XG_START_ETH_BUFNUM_1 2
72#define XG_START_BP_BUFNUM_1 0x22
73#define XG_START_RING_NUM_1 264
74
75#define X2_START_CPU_BUFNUM_0 0
76#define X2_START_ETH_BUFNUM_0 0
77#define X2_START_BP_BUFNUM_0 0x20
78#define X2_START_RING_NUM_0 0
79#define X2_START_CPU_BUFNUM_1 0xc
80#define X2_START_ETH_BUFNUM_1 0
81#define X2_START_BP_BUFNUM_1 0x20
82#define X2_START_RING_NUM_1 256
83
84#define IRQ_ID_SIZE 16
85
86#define PHY_POLL_LINK_ON (10 * HZ)
87#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
88
89enum xgene_enet_id {
90 XGENE_ENET1 = 1,
91 XGENE_ENET2
92};
93
94enum xgene_enet_buf_len {
95 SIZE_2K = 2048,
96 SIZE_4K = 4096,
97 SIZE_16K = 16384
98};
99
100
101struct xgene_enet_desc_ring {
102 struct net_device *ndev;
103 u16 id;
104 u16 num;
105 u16 head;
106 u16 tail;
107 u16 exp_buf_tail;
108 u16 slots;
109 u16 irq;
110 char irq_name[IRQ_ID_SIZE];
111 u32 size;
112 u32 state[X2_NUM_RING_CONFIG];
113 void __iomem *cmd_base;
114 void __iomem *cmd;
115 dma_addr_t dma;
116 dma_addr_t irq_mbox_dma;
117 void *irq_mbox_addr;
118 u16 dst_ring_num;
119 u16 nbufpool;
120 int npagepool;
121 u8 index;
122 u32 flags;
123 struct sk_buff *(*rx_skb);
124 struct sk_buff *(*cp_skb);
125 dma_addr_t *frag_dma_addr;
126 struct page *(*frag_page);
127 enum xgene_enet_ring_cfgsize cfgsize;
128 struct xgene_enet_desc_ring *cp_ring;
129 struct xgene_enet_desc_ring *buf_pool;
130 struct xgene_enet_desc_ring *page_pool;
131 struct napi_struct napi;
132 union {
133 void *desc_addr;
134 struct xgene_enet_raw_desc *raw_desc;
135 struct xgene_enet_raw_desc16 *raw_desc16;
136 };
137 __le64 *exp_bufs;
138 u64 tx_packets;
139 u64 tx_bytes;
140 u64 rx_packets;
141 u64 rx_bytes;
142 u64 rx_dropped;
143 u64 rx_errors;
144 u64 rx_length_errors;
145 u64 rx_crc_errors;
146 u64 rx_frame_errors;
147 u64 rx_fifo_errors;
148};
149
150struct xgene_mac_ops {
151 void (*init)(struct xgene_enet_pdata *pdata);
152 void (*reset)(struct xgene_enet_pdata *pdata);
153 void (*tx_enable)(struct xgene_enet_pdata *pdata);
154 void (*rx_enable)(struct xgene_enet_pdata *pdata);
155 void (*tx_disable)(struct xgene_enet_pdata *pdata);
156 void (*rx_disable)(struct xgene_enet_pdata *pdata);
157 void (*set_speed)(struct xgene_enet_pdata *pdata);
158 void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
159 void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize);
160 void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index);
161 void (*link_state)(struct work_struct *work);
162 void (*enable_tx_pause)(struct xgene_enet_pdata *pdata, bool enable);
163 void (*flowctl_rx)(struct xgene_enet_pdata *pdata, bool enable);
164 void (*flowctl_tx)(struct xgene_enet_pdata *pdata, bool enable);
165};
166
167struct xgene_port_ops {
168 int (*reset)(struct xgene_enet_pdata *pdata);
169 void (*clear)(struct xgene_enet_pdata *pdata,
170 struct xgene_enet_desc_ring *ring);
171 void (*cle_bypass)(struct xgene_enet_pdata *pdata,
172 u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id);
173 void (*shutdown)(struct xgene_enet_pdata *pdata);
174};
175
176struct xgene_ring_ops {
177 u8 num_ring_config;
178 u8 num_ring_id_shift;
179 struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
180 void (*clear)(struct xgene_enet_desc_ring *);
181 void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
182 u32 (*len)(struct xgene_enet_desc_ring *);
183 void (*coalesce)(struct xgene_enet_desc_ring *);
184};
185
186struct xgene_cle_ops {
187 int (*cle_init)(struct xgene_enet_pdata *pdata);
188};
189
190
191struct xgene_enet_pdata {
192 struct net_device *ndev;
193 struct mii_bus *mdio_bus;
194 int phy_speed;
195 struct clk *clk;
196 struct platform_device *pdev;
197 enum xgene_enet_id enet_id;
198 struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
199 struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
200 u16 tx_level[XGENE_NUM_TX_RING];
201 u16 txc_level[XGENE_NUM_TX_RING];
202 char *dev_name;
203 u32 rx_buff_cnt;
204 u32 tx_qcnt_hi;
205 u32 irqs[XGENE_MAX_ENET_IRQ];
206 u8 rxq_cnt;
207 u8 txq_cnt;
208 u8 cq_cnt;
209 void __iomem *eth_csr_addr;
210 void __iomem *eth_ring_if_addr;
211 void __iomem *eth_diag_csr_addr;
212 void __iomem *mcx_mac_addr;
213 void __iomem *mcx_mac_csr_addr;
214 void __iomem *base_addr;
215 void __iomem *pcs_addr;
216 void __iomem *ring_csr_addr;
217 void __iomem *ring_cmd_addr;
218 int phy_mode;
219 enum xgene_enet_rm rm;
220 struct xgene_enet_cle cle;
221 struct rtnl_link_stats64 stats;
222 const struct xgene_mac_ops *mac_ops;
223 const struct xgene_port_ops *port_ops;
224 struct xgene_ring_ops *ring_ops;
225 const struct xgene_cle_ops *cle_ops;
226 struct delayed_work link_work;
227 u32 port_id;
228 u8 cpu_bufnum;
229 u8 eth_bufnum;
230 u8 bp_bufnum;
231 u16 ring_num;
232 u32 mss[NUM_MSS_REG];
233 u32 mss_refcnt[NUM_MSS_REG];
234 spinlock_t mss_lock;
235 u8 tx_delay;
236 u8 rx_delay;
237 bool mdio_driver;
238 struct gpio_desc *sfp_rdy;
239 bool sfp_gpio_en;
240 u32 pause_autoneg;
241 bool tx_pause;
242 bool rx_pause;
243};
244
245struct xgene_indirect_ctl {
246 void __iomem *addr;
247 void __iomem *ctl;
248 void __iomem *cmd;
249 void __iomem *cmd_done;
250};
251
252static inline struct device *ndev_to_dev(struct net_device *ndev)
253{
254 return ndev->dev.parent;
255}
256
257static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
258{
259 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
260
261 return ((u16)pdata->rm << 10) | ring->num;
262}
263
264void xgene_enet_set_ethtool_ops(struct net_device *netdev);
265
266#endif
267
