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27#ifndef _I40E_TYPE_H_
28#define _I40E_TYPE_H_
29
30#include "i40e_status.h"
31#include "i40e_osdep.h"
32#include "i40e_register.h"
33#include "i40e_adminq.h"
34#include "i40e_hmc.h"
35#include "i40e_lan_hmc.h"
36#include "i40e_devids.h"
37
38
39#define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
40
41#define I40E_MAX_VSI_QP 16
42#define I40E_MAX_VF_VSI 3
43#define I40E_MAX_CHAINED_RX_BUFFERS 5
44#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
45
46
47#define I40E_MAX_NVM_TIMEOUT 18000
48
49
50#define I40E_MS_TO_GTIME(time) ((time) * 1000)
51
52
53struct i40e_hw;
54typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
55
56
57
58#define I40E_DESC_UNUSED(R) \
59 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60 (R)->next_to_clean - (R)->next_to_use - 1)
61
62
63#define I40E_QTX_CTL_VF_QUEUE 0x0
64#define I40E_QTX_CTL_VM_QUEUE 0x1
65#define I40E_QTX_CTL_PF_QUEUE 0x2
66
67
68enum i40e_debug_mask {
69 I40E_DEBUG_INIT = 0x00000001,
70 I40E_DEBUG_RELEASE = 0x00000002,
71
72 I40E_DEBUG_LINK = 0x00000010,
73 I40E_DEBUG_PHY = 0x00000020,
74 I40E_DEBUG_HMC = 0x00000040,
75 I40E_DEBUG_NVM = 0x00000080,
76 I40E_DEBUG_LAN = 0x00000100,
77 I40E_DEBUG_FLOW = 0x00000200,
78 I40E_DEBUG_DCB = 0x00000400,
79 I40E_DEBUG_DIAG = 0x00000800,
80 I40E_DEBUG_FD = 0x00001000,
81
82 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
83 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
84 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
85 I40E_DEBUG_AQ_COMMAND = 0x06000000,
86 I40E_DEBUG_AQ = 0x0F000000,
87
88 I40E_DEBUG_USER = 0xF0000000,
89
90 I40E_DEBUG_ALL = 0xFFFFFFFF
91};
92
93
94
95
96
97
98
99
100
101enum i40e_mac_type {
102 I40E_MAC_UNKNOWN = 0,
103 I40E_MAC_X710,
104 I40E_MAC_XL710,
105 I40E_MAC_VF,
106 I40E_MAC_X722,
107 I40E_MAC_X722_VF,
108 I40E_MAC_GENERIC,
109};
110
111enum i40e_media_type {
112 I40E_MEDIA_TYPE_UNKNOWN = 0,
113 I40E_MEDIA_TYPE_FIBER,
114 I40E_MEDIA_TYPE_BASET,
115 I40E_MEDIA_TYPE_BACKPLANE,
116 I40E_MEDIA_TYPE_CX4,
117 I40E_MEDIA_TYPE_DA,
118 I40E_MEDIA_TYPE_VIRTUAL
119};
120
121enum i40e_fc_mode {
122 I40E_FC_NONE = 0,
123 I40E_FC_RX_PAUSE,
124 I40E_FC_TX_PAUSE,
125 I40E_FC_FULL,
126 I40E_FC_PFC,
127 I40E_FC_DEFAULT
128};
129
130enum i40e_set_fc_aq_failures {
131 I40E_SET_FC_AQ_FAIL_NONE = 0,
132 I40E_SET_FC_AQ_FAIL_GET = 1,
133 I40E_SET_FC_AQ_FAIL_SET = 2,
134 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
135 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
136};
137
138enum i40e_vsi_type {
139 I40E_VSI_MAIN = 0,
140 I40E_VSI_VMDQ1 = 1,
141 I40E_VSI_VMDQ2 = 2,
142 I40E_VSI_CTRL = 3,
143 I40E_VSI_FCOE = 4,
144 I40E_VSI_MIRROR = 5,
145 I40E_VSI_SRIOV = 6,
146 I40E_VSI_FDIR = 7,
147 I40E_VSI_TYPE_UNKNOWN
148};
149
150enum i40e_queue_type {
151 I40E_QUEUE_TYPE_RX = 0,
152 I40E_QUEUE_TYPE_TX,
153 I40E_QUEUE_TYPE_PE_CEQ,
154 I40E_QUEUE_TYPE_UNKNOWN
155};
156
157struct i40e_link_status {
158 enum i40e_aq_phy_type phy_type;
159 enum i40e_aq_link_speed link_speed;
160 u8 link_info;
161 u8 an_info;
162 u8 ext_info;
163 u8 loopback;
164
165 bool lse_enable;
166 u16 max_frame_size;
167 bool crc_enable;
168 u8 pacing;
169 u8 requested_speeds;
170 u8 module_type[3];
171
172#define I40E_MODULE_TYPE_SFP 0x03
173#define I40E_MODULE_TYPE_QSFP 0x0D
174
175#define I40E_MODULE_TYPE_40G_ACTIVE 0x01
176#define I40E_MODULE_TYPE_40G_LR4 0x02
177#define I40E_MODULE_TYPE_40G_SR4 0x04
178#define I40E_MODULE_TYPE_40G_CR4 0x08
179#define I40E_MODULE_TYPE_10G_BASE_SR 0x10
180#define I40E_MODULE_TYPE_10G_BASE_LR 0x20
181#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
182#define I40E_MODULE_TYPE_10G_BASE_ER 0x80
183
184#define I40E_MODULE_TYPE_1000BASE_SX 0x01
185#define I40E_MODULE_TYPE_1000BASE_LX 0x02
186#define I40E_MODULE_TYPE_1000BASE_CX 0x04
187#define I40E_MODULE_TYPE_1000BASE_T 0x08
188};
189
190struct i40e_phy_info {
191 struct i40e_link_status link_info;
192 struct i40e_link_status link_info_old;
193 bool get_link_info;
194 enum i40e_media_type media_type;
195
196 u64 phy_types;
197};
198
199#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
200#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
201#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
202#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
203#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
204#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
205#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
206#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
207#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
208#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
209#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
210#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
211#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
212#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
213#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
214#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
215#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
216#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
217#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
218#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
219#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
220#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
221#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
222#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
223#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
224#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
225#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
226 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
227#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
228
229
230
231
232
233
234#define I40E_PHY_TYPE_OFFSET 1
235#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
236 I40E_PHY_TYPE_OFFSET)
237#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
238 I40E_PHY_TYPE_OFFSET)
239#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
240 I40E_PHY_TYPE_OFFSET)
241#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
242 I40E_PHY_TYPE_OFFSET)
243#define I40E_HW_CAP_MAX_GPIO 30
244
245struct i40e_hw_capabilities {
246 u32 switch_mode;
247#define I40E_NVM_IMAGE_TYPE_EVB 0x0
248#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
249#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
250
251 u32 management_mode;
252 u32 mng_protocols_over_mctp;
253#define I40E_MNG_PROTOCOL_PLDM 0x2
254#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
255#define I40E_MNG_PROTOCOL_NCSI 0x8
256 u32 npar_enable;
257 u32 os2bmc;
258 u32 valid_functions;
259 bool sr_iov_1_1;
260 bool vmdq;
261 bool evb_802_1_qbg;
262 bool evb_802_1_qbh;
263 bool dcb;
264 bool fcoe;
265 bool iscsi;
266 bool flex10_enable;
267 bool flex10_capable;
268 u32 flex10_mode;
269#define I40E_FLEX10_MODE_UNKNOWN 0x0
270#define I40E_FLEX10_MODE_DCC 0x1
271#define I40E_FLEX10_MODE_DCI 0x2
272
273 u32 flex10_status;
274#define I40E_FLEX10_STATUS_DCC_ERROR 0x1
275#define I40E_FLEX10_STATUS_VC_MODE 0x2
276
277 bool sec_rev_disabled;
278 bool update_disabled;
279#define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
280#define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
281
282 bool mgmt_cem;
283 bool ieee_1588;
284 bool iwarp;
285 bool fd;
286 u32 fd_filters_guaranteed;
287 u32 fd_filters_best_effort;
288 bool rss;
289 u32 rss_table_size;
290 u32 rss_table_entry_width;
291 bool led[I40E_HW_CAP_MAX_GPIO];
292 bool sdp[I40E_HW_CAP_MAX_GPIO];
293 u32 nvm_image_type;
294 u32 num_flow_director_filters;
295 u32 num_vfs;
296 u32 vf_base_id;
297 u32 num_vsis;
298 u32 num_rx_qp;
299 u32 num_tx_qp;
300 u32 base_queue;
301 u32 num_msix_vectors;
302 u32 num_msix_vectors_vf;
303 u32 led_pin_num;
304 u32 sdp_pin_num;
305 u32 mdio_port_num;
306 u32 mdio_port_mode;
307 u8 rx_buf_chain_len;
308 u32 enabled_tcmap;
309 u32 maxtc;
310 u64 wr_csr_prot;
311};
312
313struct i40e_mac_info {
314 enum i40e_mac_type type;
315 u8 addr[ETH_ALEN];
316 u8 perm_addr[ETH_ALEN];
317 u8 san_addr[ETH_ALEN];
318 u16 max_fcoeq;
319};
320
321enum i40e_aq_resources_ids {
322 I40E_NVM_RESOURCE_ID = 1
323};
324
325enum i40e_aq_resource_access_type {
326 I40E_RESOURCE_READ = 1,
327 I40E_RESOURCE_WRITE
328};
329
330struct i40e_nvm_info {
331 u64 hw_semaphore_timeout;
332 u32 timeout;
333 u16 sr_size;
334 bool blank_nvm_mode;
335 u16 version;
336 u32 eetrack;
337 u32 oem_ver;
338};
339
340
341
342enum i40e_nvmupd_cmd {
343 I40E_NVMUPD_INVALID,
344 I40E_NVMUPD_READ_CON,
345 I40E_NVMUPD_READ_SNT,
346 I40E_NVMUPD_READ_LCB,
347 I40E_NVMUPD_READ_SA,
348 I40E_NVMUPD_WRITE_ERA,
349 I40E_NVMUPD_WRITE_CON,
350 I40E_NVMUPD_WRITE_SNT,
351 I40E_NVMUPD_WRITE_LCB,
352 I40E_NVMUPD_WRITE_SA,
353 I40E_NVMUPD_CSUM_CON,
354 I40E_NVMUPD_CSUM_SA,
355 I40E_NVMUPD_CSUM_LCB,
356 I40E_NVMUPD_STATUS,
357 I40E_NVMUPD_EXEC_AQ,
358 I40E_NVMUPD_GET_AQ_RESULT,
359};
360
361enum i40e_nvmupd_state {
362 I40E_NVMUPD_STATE_INIT,
363 I40E_NVMUPD_STATE_READING,
364 I40E_NVMUPD_STATE_WRITING,
365 I40E_NVMUPD_STATE_INIT_WAIT,
366 I40E_NVMUPD_STATE_WRITE_WAIT,
367 I40E_NVMUPD_STATE_ERROR
368};
369
370
371
372
373#define I40E_NVM_READ 0xB
374#define I40E_NVM_WRITE 0xC
375
376#define I40E_NVM_MOD_PNT_MASK 0xFF
377
378#define I40E_NVM_TRANS_SHIFT 8
379#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
380#define I40E_NVM_CON 0x0
381#define I40E_NVM_SNT 0x1
382#define I40E_NVM_LCB 0x2
383#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
384#define I40E_NVM_ERA 0x4
385#define I40E_NVM_CSUM 0x8
386#define I40E_NVM_EXEC 0xf
387
388#define I40E_NVM_ADAPT_SHIFT 16
389#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
390
391#define I40E_NVMUPD_MAX_DATA 4096
392#define I40E_NVMUPD_IFACE_TIMEOUT 2
393
394struct i40e_nvm_access {
395 u32 command;
396 u32 config;
397 u32 offset;
398 u32 data_size;
399 u8 data[1];
400};
401
402
403enum i40e_bus_type {
404 i40e_bus_type_unknown = 0,
405 i40e_bus_type_pci,
406 i40e_bus_type_pcix,
407 i40e_bus_type_pci_express,
408 i40e_bus_type_reserved
409};
410
411
412enum i40e_bus_speed {
413 i40e_bus_speed_unknown = 0,
414 i40e_bus_speed_33 = 33,
415 i40e_bus_speed_66 = 66,
416 i40e_bus_speed_100 = 100,
417 i40e_bus_speed_120 = 120,
418 i40e_bus_speed_133 = 133,
419 i40e_bus_speed_2500 = 2500,
420 i40e_bus_speed_5000 = 5000,
421 i40e_bus_speed_8000 = 8000,
422 i40e_bus_speed_reserved
423};
424
425
426enum i40e_bus_width {
427 i40e_bus_width_unknown = 0,
428 i40e_bus_width_pcie_x1 = 1,
429 i40e_bus_width_pcie_x2 = 2,
430 i40e_bus_width_pcie_x4 = 4,
431 i40e_bus_width_pcie_x8 = 8,
432 i40e_bus_width_32 = 32,
433 i40e_bus_width_64 = 64,
434 i40e_bus_width_reserved
435};
436
437
438struct i40e_bus_info {
439 enum i40e_bus_speed speed;
440 enum i40e_bus_width width;
441 enum i40e_bus_type type;
442
443 u16 func;
444 u16 device;
445 u16 lan_id;
446};
447
448
449struct i40e_fc_info {
450 enum i40e_fc_mode current_mode;
451 enum i40e_fc_mode requested_mode;
452};
453
454#define I40E_MAX_TRAFFIC_CLASS 8
455#define I40E_MAX_USER_PRIORITY 8
456#define I40E_DCBX_MAX_APPS 32
457#define I40E_LLDPDU_SIZE 1500
458
459
460struct i40e_ieee_ets_config {
461 u8 willing;
462 u8 cbs;
463 u8 maxtcs;
464 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
465 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
466 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
467};
468
469
470struct i40e_ieee_ets_recommend {
471 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
472 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
473 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
474};
475
476
477struct i40e_ieee_pfc_config {
478 u8 willing;
479 u8 mbc;
480 u8 pfccap;
481 u8 pfcenable;
482};
483
484
485struct i40e_ieee_app_priority_table {
486 u8 priority;
487 u8 selector;
488 u16 protocolid;
489};
490
491struct i40e_dcbx_config {
492 u32 numapps;
493 u32 tlv_status;
494 struct i40e_ieee_ets_config etscfg;
495 struct i40e_ieee_ets_recommend etsrec;
496 struct i40e_ieee_pfc_config pfc;
497 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
498};
499
500
501struct i40e_hw {
502 u8 __iomem *hw_addr;
503 void *back;
504
505
506 struct i40e_phy_info phy;
507 struct i40e_mac_info mac;
508 struct i40e_bus_info bus;
509 struct i40e_nvm_info nvm;
510 struct i40e_fc_info fc;
511
512
513 u16 device_id;
514 u16 vendor_id;
515 u16 subsystem_device_id;
516 u16 subsystem_vendor_id;
517 u8 revision_id;
518 u8 port;
519 bool adapter_stopped;
520
521
522 struct i40e_hw_capabilities dev_caps;
523 struct i40e_hw_capabilities func_caps;
524
525
526 u16 fdir_shared_filter_count;
527
528
529 u8 pf_id;
530 u16 main_vsi_seid;
531
532
533 u16 partition_id;
534 u16 num_partitions;
535 u16 num_ports;
536
537
538 u16 numa_node;
539
540
541 struct i40e_adminq_info aq;
542
543
544 enum i40e_nvmupd_state nvmupd_state;
545 struct i40e_aq_desc nvm_wb_desc;
546 struct i40e_virt_mem nvm_buff;
547 bool nvm_release_on_done;
548 u16 nvm_wait_opcode;
549
550
551 struct i40e_hmc_info hmc;
552
553
554 u16 dcbx_status;
555
556
557 struct i40e_dcbx_config local_dcbx_config;
558 struct i40e_dcbx_config remote_dcbx_config;
559 struct i40e_dcbx_config desired_dcbx_config;
560
561
562 u32 debug_mask;
563 char err_str[16];
564};
565
566static inline bool i40e_is_vf(struct i40e_hw *hw)
567{
568 return (hw->mac.type == I40E_MAC_VF ||
569 hw->mac.type == I40E_MAC_X722_VF);
570}
571
572struct i40e_driver_version {
573 u8 major_version;
574 u8 minor_version;
575 u8 build_version;
576 u8 subbuild_version;
577 u8 driver_string[32];
578};
579
580
581union i40e_16byte_rx_desc {
582 struct {
583 __le64 pkt_addr;
584 __le64 hdr_addr;
585 } read;
586 struct {
587 struct {
588 struct {
589 union {
590 __le16 mirroring_status;
591 __le16 fcoe_ctx_id;
592 } mirr_fcoe;
593 __le16 l2tag1;
594 } lo_dword;
595 union {
596 __le32 rss;
597 __le32 fd_id;
598 __le32 fcoe_param;
599 } hi_dword;
600 } qword0;
601 struct {
602
603 __le64 status_error_len;
604 } qword1;
605 } wb;
606};
607
608union i40e_32byte_rx_desc {
609 struct {
610 __le64 pkt_addr;
611 __le64 hdr_addr;
612
613 __le64 rsvd1;
614 __le64 rsvd2;
615 } read;
616 struct {
617 struct {
618 struct {
619 union {
620 __le16 mirroring_status;
621 __le16 fcoe_ctx_id;
622 } mirr_fcoe;
623 __le16 l2tag1;
624 } lo_dword;
625 union {
626 __le32 rss;
627 __le32 fcoe_param;
628
629
630
631 __le32 fd_id;
632 } hi_dword;
633 } qword0;
634 struct {
635
636 __le64 status_error_len;
637 } qword1;
638 struct {
639 __le16 ext_status;
640 __le16 rsvd;
641 __le16 l2tag2_1;
642 __le16 l2tag2_2;
643 } qword2;
644 struct {
645 union {
646 __le32 flex_bytes_lo;
647 __le32 pe_status;
648 } lo_dword;
649 union {
650 __le32 flex_bytes_hi;
651 __le32 fd_id;
652 } hi_dword;
653 } qword3;
654 } wb;
655};
656
657enum i40e_rx_desc_status_bits {
658
659 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
660 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
661 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
662 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
663 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
664 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5,
665 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
666
667 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
668 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9,
669 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
670 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12,
671 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
672 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
673 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16,
674
675
676
677 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
678 I40E_RX_DESC_STATUS_LAST
679};
680
681#define I40E_RXD_QW1_STATUS_SHIFT 0
682#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
683 << I40E_RXD_QW1_STATUS_SHIFT)
684
685#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
686#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
687 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
688
689#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
690#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
691 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
692
693enum i40e_rx_desc_fltstat_values {
694 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
695 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1,
696 I40E_RX_DESC_FLTSTAT_RSV = 2,
697 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
698};
699
700#define I40E_RXD_QW1_ERROR_SHIFT 19
701#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
702
703enum i40e_rx_desc_error_bits {
704
705 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
706 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
707 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
708 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3,
709 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
710 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
711 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
712 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
713 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
714};
715
716enum i40e_rx_desc_error_l3l4e_fcoe_masks {
717 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
718 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
719 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
720 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
721 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
722};
723
724#define I40E_RXD_QW1_PTYPE_SHIFT 30
725#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
726
727
728enum i40e_rx_l2_ptype {
729 I40E_RX_PTYPE_L2_RESERVED = 0,
730 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
731 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
732 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
733 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
734 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
735 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
736 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
737 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
738 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
739 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
740 I40E_RX_PTYPE_L2_ARP = 11,
741 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
742 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
743 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
744 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
745 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
746 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
747 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
748 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
749 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
750 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
751 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
752 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
753 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
754 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
755};
756
757struct i40e_rx_ptype_decoded {
758 u32 ptype:8;
759 u32 known:1;
760 u32 outer_ip:1;
761 u32 outer_ip_ver:1;
762 u32 outer_frag:1;
763 u32 tunnel_type:3;
764 u32 tunnel_end_prot:2;
765 u32 tunnel_end_frag:1;
766 u32 inner_prot:4;
767 u32 payload_layer:3;
768};
769
770enum i40e_rx_ptype_outer_ip {
771 I40E_RX_PTYPE_OUTER_L2 = 0,
772 I40E_RX_PTYPE_OUTER_IP = 1
773};
774
775enum i40e_rx_ptype_outer_ip_ver {
776 I40E_RX_PTYPE_OUTER_NONE = 0,
777 I40E_RX_PTYPE_OUTER_IPV4 = 0,
778 I40E_RX_PTYPE_OUTER_IPV6 = 1
779};
780
781enum i40e_rx_ptype_outer_fragmented {
782 I40E_RX_PTYPE_NOT_FRAG = 0,
783 I40E_RX_PTYPE_FRAG = 1
784};
785
786enum i40e_rx_ptype_tunnel_type {
787 I40E_RX_PTYPE_TUNNEL_NONE = 0,
788 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
789 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
790 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
791 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
792};
793
794enum i40e_rx_ptype_tunnel_end_prot {
795 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
796 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
797 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
798};
799
800enum i40e_rx_ptype_inner_prot {
801 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
802 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
803 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
804 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
805 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
806 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
807};
808
809enum i40e_rx_ptype_payload_layer {
810 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
811 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
812 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
813 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
814};
815
816#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
817#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
818 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
819
820#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
821#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
822 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
823
824#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
825#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
826
827enum i40e_rx_desc_ext_status_bits {
828
829 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
830 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
831 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2,
832 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4,
833 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
834 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
835 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
836};
837
838enum i40e_rx_desc_pe_status_bits {
839
840 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0,
841 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0,
842 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16,
843 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
844 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
845 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
846 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
847 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
848 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
849};
850
851#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
852#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
853
854#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
855#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
856 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
857
858#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
859#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
860 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
861
862enum i40e_rx_prog_status_desc_status_bits {
863
864 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
865 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2
866};
867
868enum i40e_rx_prog_status_desc_prog_id_masks {
869 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
870 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
871 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
872};
873
874enum i40e_rx_prog_status_desc_error_bits {
875
876 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
877 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
878 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
879 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
880};
881
882
883struct i40e_tx_desc {
884 __le64 buffer_addr;
885 __le64 cmd_type_offset_bsz;
886};
887
888#define I40E_TXD_QW1_DTYPE_SHIFT 0
889#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
890
891enum i40e_tx_desc_dtype_value {
892 I40E_TX_DESC_DTYPE_DATA = 0x0,
893 I40E_TX_DESC_DTYPE_NOP = 0x1,
894 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
895 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
896 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
897 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
898 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
899 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
900 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
901 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
902};
903
904#define I40E_TXD_QW1_CMD_SHIFT 4
905#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
906
907enum i40e_tx_desc_cmd_bits {
908 I40E_TX_DESC_CMD_EOP = 0x0001,
909 I40E_TX_DESC_CMD_RS = 0x0002,
910 I40E_TX_DESC_CMD_ICRC = 0x0004,
911 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
912 I40E_TX_DESC_CMD_DUMMY = 0x0010,
913 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000,
914 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020,
915 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040,
916 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060,
917 I40E_TX_DESC_CMD_FCOET = 0x0080,
918 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000,
919 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100,
920 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200,
921 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300,
922 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000,
923 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100,
924 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200,
925 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300,
926};
927
928#define I40E_TXD_QW1_OFFSET_SHIFT 16
929#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
930 I40E_TXD_QW1_OFFSET_SHIFT)
931
932enum i40e_tx_desc_length_fields {
933
934 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0,
935 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7,
936 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14
937};
938
939#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
940#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
941 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
942
943#define I40E_TXD_QW1_L2TAG1_SHIFT 48
944#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
945
946
947struct i40e_tx_context_desc {
948 __le32 tunneling_params;
949 __le16 l2tag2;
950 __le16 rsvd;
951 __le64 type_cmd_tso_mss;
952};
953
954#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
955#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
956
957#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
958#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
959
960enum i40e_tx_ctx_desc_cmd_bits {
961 I40E_TX_CTX_DESC_TSO = 0x01,
962 I40E_TX_CTX_DESC_TSYN = 0x02,
963 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
964 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
965 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
966 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
967 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
968 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
969 I40E_TX_CTX_DESC_SWPE = 0x40
970};
971
972#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
973#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
974 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
975
976#define I40E_TXD_CTX_QW1_MSS_SHIFT 50
977#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
978 I40E_TXD_CTX_QW1_MSS_SHIFT)
979
980#define I40E_TXD_CTX_QW1_VSI_SHIFT 50
981#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
982
983#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
984#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
985 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
986
987enum i40e_tx_ctx_desc_eipt_offload {
988 I40E_TX_CTX_EXT_IP_NONE = 0x0,
989 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
990 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
991 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
992};
993
994#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
995#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
996 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
997
998#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
999#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1000
1001#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1002#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1003
1004#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1005#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1006 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1007
1008#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1009
1010#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1011#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1012 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1013
1014#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1015#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1016 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1017
1018#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1019#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1020struct i40e_filter_program_desc {
1021 __le32 qindex_flex_ptype_vsi;
1022 __le32 rsvd;
1023 __le32 dtype_cmd_cntindex;
1024 __le32 fd_id;
1025};
1026#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1027#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1028 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1029#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1030#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1031 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1032#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1033#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1034 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1035
1036
1037enum i40e_filter_pctype {
1038
1039
1040
1041 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1042 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1043 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1044 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1045 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1046 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1047 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1048 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1049
1050
1051
1052 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1053 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1054 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1055 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1056 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1057 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1058 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1059 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1060
1061 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1062 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1063 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1064
1065 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1066};
1067
1068enum i40e_filter_program_desc_dest {
1069 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1070 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1071 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1072};
1073
1074enum i40e_filter_program_desc_fd_status {
1075 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1076 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1077 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1078 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1079};
1080
1081#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1082#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1083 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1084
1085#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1086#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1087 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1088
1089#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1090#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1091
1092enum i40e_filter_program_desc_pcmd {
1093 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1094 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1095};
1096
1097#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1098#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1099
1100#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1101#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1102
1103#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1104 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1105#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1106 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1107
1108#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1109#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1110 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1111
1112enum i40e_filter_type {
1113 I40E_FLOW_DIRECTOR_FLTR = 0,
1114 I40E_PE_QUAD_HASH_FLTR = 1,
1115 I40E_ETHERTYPE_FLTR,
1116 I40E_FCOE_CTX_FLTR,
1117 I40E_MAC_VLAN_FLTR,
1118 I40E_HASH_FLTR
1119};
1120
1121struct i40e_vsi_context {
1122 u16 seid;
1123 u16 uplink_seid;
1124 u16 vsi_number;
1125 u16 vsis_allocated;
1126 u16 vsis_unallocated;
1127 u16 flags;
1128 u8 pf_num;
1129 u8 vf_num;
1130 u8 connection_type;
1131 struct i40e_aqc_vsi_properties_data info;
1132};
1133
1134struct i40e_veb_context {
1135 u16 seid;
1136 u16 uplink_seid;
1137 u16 veb_number;
1138 u16 vebs_allocated;
1139 u16 vebs_unallocated;
1140 u16 flags;
1141 struct i40e_aqc_get_veb_parameters_completion info;
1142};
1143
1144
1145struct i40e_eth_stats {
1146 u64 rx_bytes;
1147 u64 rx_unicast;
1148 u64 rx_multicast;
1149 u64 rx_broadcast;
1150 u64 rx_discards;
1151 u64 rx_unknown_protocol;
1152 u64 tx_bytes;
1153 u64 tx_unicast;
1154 u64 tx_multicast;
1155 u64 tx_broadcast;
1156 u64 tx_discards;
1157 u64 tx_errors;
1158};
1159
1160
1161struct i40e_veb_tc_stats {
1162 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1163 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1164 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1165 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1166};
1167
1168
1169struct i40e_hw_port_stats {
1170
1171 struct i40e_eth_stats eth;
1172
1173
1174 u64 tx_dropped_link_down;
1175 u64 crc_errors;
1176 u64 illegal_bytes;
1177 u64 error_bytes;
1178 u64 mac_local_faults;
1179 u64 mac_remote_faults;
1180 u64 rx_length_errors;
1181 u64 link_xon_rx;
1182 u64 link_xoff_rx;
1183 u64 priority_xon_rx[8];
1184 u64 priority_xoff_rx[8];
1185 u64 link_xon_tx;
1186 u64 link_xoff_tx;
1187 u64 priority_xon_tx[8];
1188 u64 priority_xoff_tx[8];
1189 u64 priority_xon_2_xoff[8];
1190 u64 rx_size_64;
1191 u64 rx_size_127;
1192 u64 rx_size_255;
1193 u64 rx_size_511;
1194 u64 rx_size_1023;
1195 u64 rx_size_1522;
1196 u64 rx_size_big;
1197 u64 rx_undersize;
1198 u64 rx_fragments;
1199 u64 rx_oversize;
1200 u64 rx_jabber;
1201 u64 tx_size_64;
1202 u64 tx_size_127;
1203 u64 tx_size_255;
1204 u64 tx_size_511;
1205 u64 tx_size_1023;
1206 u64 tx_size_1522;
1207 u64 tx_size_big;
1208 u64 mac_short_packet_dropped;
1209 u64 checksum_error;
1210
1211 u64 fd_atr_match;
1212 u64 fd_sb_match;
1213 u64 fd_atr_tunnel_match;
1214 u32 fd_atr_status;
1215 u32 fd_sb_status;
1216
1217 u32 tx_lpi_status;
1218 u32 rx_lpi_status;
1219 u64 tx_lpi_count;
1220 u64 rx_lpi_count;
1221};
1222
1223
1224#define I40E_SR_NVM_CONTROL_WORD 0x00
1225#define I40E_SR_EMP_MODULE_PTR 0x0F
1226#define I40E_NVM_OEM_VER_OFF 0x83
1227#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1228#define I40E_SR_NVM_WAKE_ON_LAN 0x19
1229#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1230#define I40E_SR_NVM_EETRACK_LO 0x2D
1231#define I40E_SR_NVM_EETRACK_HI 0x2E
1232#define I40E_SR_VPD_PTR 0x2F
1233#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1234#define I40E_SR_SW_CHECKSUM_WORD 0x3F
1235
1236
1237#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1238#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1239#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1240#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1241
1242
1243#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1244#define I40E_SR_WORDS_IN_1KB 512
1245
1246
1247
1248#define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1249
1250#define I40E_SRRD_SRCTL_ATTEMPTS 100000
1251
1252enum i40e_switch_element_types {
1253 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1254 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1255 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1256 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1257 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1258 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1259 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1260 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1261 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1262};
1263
1264
1265enum i40e_ether_type_index {
1266 I40E_ETHER_TYPE_1588 = 0,
1267 I40E_ETHER_TYPE_FIP = 1,
1268 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1269 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1270 I40E_ETHER_TYPE_LLDP = 4,
1271 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1272 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1273 I40E_ETHER_TYPE_QCN_CNM = 7,
1274 I40E_ETHER_TYPE_8021X = 8,
1275 I40E_ETHER_TYPE_ARP = 9,
1276 I40E_ETHER_TYPE_RSV1 = 10,
1277 I40E_ETHER_TYPE_RSV2 = 11,
1278};
1279
1280
1281#define I40E_HASH_FILTER_BASE_SIZE 1024
1282
1283enum i40e_hash_filter_size {
1284 I40E_HASH_FILTER_SIZE_1K = 0,
1285 I40E_HASH_FILTER_SIZE_2K = 1,
1286 I40E_HASH_FILTER_SIZE_4K = 2,
1287 I40E_HASH_FILTER_SIZE_8K = 3,
1288 I40E_HASH_FILTER_SIZE_16K = 4,
1289 I40E_HASH_FILTER_SIZE_32K = 5,
1290 I40E_HASH_FILTER_SIZE_64K = 6,
1291 I40E_HASH_FILTER_SIZE_128K = 7,
1292 I40E_HASH_FILTER_SIZE_256K = 8,
1293 I40E_HASH_FILTER_SIZE_512K = 9,
1294 I40E_HASH_FILTER_SIZE_1M = 10,
1295};
1296
1297
1298#define I40E_DMA_CNTX_BASE_SIZE 512
1299
1300enum i40e_dma_cntx_size {
1301 I40E_DMA_CNTX_SIZE_512 = 0,
1302 I40E_DMA_CNTX_SIZE_1K = 1,
1303 I40E_DMA_CNTX_SIZE_2K = 2,
1304 I40E_DMA_CNTX_SIZE_4K = 3,
1305 I40E_DMA_CNTX_SIZE_8K = 4,
1306 I40E_DMA_CNTX_SIZE_16K = 5,
1307 I40E_DMA_CNTX_SIZE_32K = 6,
1308 I40E_DMA_CNTX_SIZE_64K = 7,
1309 I40E_DMA_CNTX_SIZE_128K = 8,
1310 I40E_DMA_CNTX_SIZE_256K = 9,
1311};
1312
1313
1314enum i40e_hash_lut_size {
1315 I40E_HASH_LUT_SIZE_128 = 0,
1316 I40E_HASH_LUT_SIZE_512 = 1,
1317};
1318
1319
1320struct i40e_filter_control_settings {
1321
1322 enum i40e_hash_filter_size pe_filt_num;
1323
1324 enum i40e_dma_cntx_size pe_cntx_num;
1325
1326 enum i40e_hash_filter_size fcoe_filt_num;
1327
1328 enum i40e_dma_cntx_size fcoe_cntx_num;
1329
1330 enum i40e_hash_lut_size hash_lut_size;
1331
1332 bool enable_fdir;
1333
1334 bool enable_ethtype;
1335
1336 bool enable_macvlan;
1337};
1338
1339
1340struct i40e_control_filter_stats {
1341 u16 mac_etype_used;
1342 u16 etype_used;
1343 u16 mac_etype_free;
1344 u16 etype_free;
1345};
1346
1347enum i40e_reset_type {
1348 I40E_RESET_POR = 0,
1349 I40E_RESET_CORER = 1,
1350 I40E_RESET_GLOBR = 2,
1351 I40E_RESET_EMPR = 3,
1352};
1353
1354
1355#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1356
1357
1358#define I40E_FD_INSET_L3_SRC_SHIFT 47
1359#define I40E_FD_INSET_L3_SRC_WORD_MASK (0x3ULL << \
1360 I40E_FD_INSET_L3_SRC_SHIFT)
1361#define I40E_FD_INSET_L3_DST_SHIFT 35
1362#define I40E_FD_INSET_L3_DST_WORD_MASK (0x3ULL << \
1363 I40E_FD_INSET_L3_DST_SHIFT)
1364#define I40E_FD_INSET_L4_SRC_SHIFT 34
1365#define I40E_FD_INSET_L4_SRC_WORD_MASK (0x1ULL << \
1366 I40E_FD_INSET_L4_SRC_SHIFT)
1367#define I40E_FD_INSET_L4_DST_SHIFT 33
1368#define I40E_FD_INSET_L4_DST_WORD_MASK (0x1ULL << \
1369 I40E_FD_INSET_L4_DST_SHIFT)
1370#define I40E_FD_INSET_VERIFY_TAG_SHIFT 31
1371#define I40E_FD_INSET_VERIFY_TAG_WORD_MASK (0x3ULL << \
1372 I40E_FD_INSET_VERIFY_TAG_SHIFT)
1373
1374#define I40E_FD_INSET_FLEX_WORD50_SHIFT 17
1375#define I40E_FD_INSET_FLEX_WORD50_MASK (0x1ULL << \
1376 I40E_FD_INSET_FLEX_WORD50_SHIFT)
1377#define I40E_FD_INSET_FLEX_WORD51_SHIFT 16
1378#define I40E_FD_INSET_FLEX_WORD51_MASK (0x1ULL << \
1379 I40E_FD_INSET_FLEX_WORD51_SHIFT)
1380#define I40E_FD_INSET_FLEX_WORD52_SHIFT 15
1381#define I40E_FD_INSET_FLEX_WORD52_MASK (0x1ULL << \
1382 I40E_FD_INSET_FLEX_WORD52_SHIFT)
1383#define I40E_FD_INSET_FLEX_WORD53_SHIFT 14
1384#define I40E_FD_INSET_FLEX_WORD53_MASK (0x1ULL << \
1385 I40E_FD_INSET_FLEX_WORD53_SHIFT)
1386#define I40E_FD_INSET_FLEX_WORD54_SHIFT 13
1387#define I40E_FD_INSET_FLEX_WORD54_MASK (0x1ULL << \
1388 I40E_FD_INSET_FLEX_WORD54_SHIFT)
1389#define I40E_FD_INSET_FLEX_WORD55_SHIFT 12
1390#define I40E_FD_INSET_FLEX_WORD55_MASK (0x1ULL << \
1391 I40E_FD_INSET_FLEX_WORD55_SHIFT)
1392#define I40E_FD_INSET_FLEX_WORD56_SHIFT 11
1393#define I40E_FD_INSET_FLEX_WORD56_MASK (0x1ULL << \
1394 I40E_FD_INSET_FLEX_WORD56_SHIFT)
1395#define I40E_FD_INSET_FLEX_WORD57_SHIFT 10
1396#define I40E_FD_INSET_FLEX_WORD57_MASK (0x1ULL << \
1397 I40E_FD_INSET_FLEX_WORD57_SHIFT)
1398#endif
1399
