1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29#ifndef _IXGBE_H_
30#define _IXGBE_H_
31
32#include <linux/bitops.h>
33#include <linux/types.h>
34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/cpumask.h>
37#include <linux/aer.h>
38#include <linux/if_vlan.h>
39#include <linux/jiffies.h>
40
41#include <linux/timecounter.h>
42#include <linux/net_tstamp.h>
43#include <linux/ptp_clock_kernel.h>
44
45#include "ixgbe_type.h"
46#include "ixgbe_common.h"
47#include "ixgbe_dcb.h"
48#if IS_ENABLED(CONFIG_FCOE)
49#define IXGBE_FCOE
50#include "ixgbe_fcoe.h"
51#endif
52#ifdef CONFIG_IXGBE_DCA
53#include <linux/dca.h>
54#endif
55
56#include <net/busy_poll.h>
57
58#ifdef CONFIG_NET_RX_BUSY_POLL
59#define BP_EXTENDED_STATS
60#endif
61
62#undef pr_fmt
63#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
64
65
66#define IXGBE_DEFAULT_TXD 512
67#define IXGBE_DEFAULT_TX_WORK 256
68#define IXGBE_MAX_TXD 4096
69#define IXGBE_MIN_TXD 64
70
71#if (PAGE_SIZE < 8192)
72#define IXGBE_DEFAULT_RXD 512
73#else
74#define IXGBE_DEFAULT_RXD 128
75#endif
76#define IXGBE_MAX_RXD 4096
77#define IXGBE_MIN_RXD 64
78
79#define IXGBE_ETH_P_LLDP 0x88CC
80
81
82#define IXGBE_MIN_FCRTL 0x40
83#define IXGBE_MAX_FCRTL 0x7FF80
84#define IXGBE_MIN_FCRTH 0x600
85#define IXGBE_MAX_FCRTH 0x7FFF0
86#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
87#define IXGBE_MIN_FCPAUSE 0
88#define IXGBE_MAX_FCPAUSE 0xFFFF
89
90
91#define IXGBE_RXBUFFER_256 256
92#define IXGBE_RXBUFFER_2K 2048
93#define IXGBE_RXBUFFER_3K 3072
94#define IXGBE_RXBUFFER_4K 4096
95#define IXGBE_MAX_RXBUFFER 16384
96
97
98
99
100
101
102
103
104
105#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
106
107
108#define IXGBE_RX_BUFFER_WRITE 16
109
110enum ixgbe_tx_flags {
111
112 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
113 IXGBE_TX_FLAGS_TSO = 0x02,
114 IXGBE_TX_FLAGS_TSTAMP = 0x04,
115
116
117 IXGBE_TX_FLAGS_CC = 0x08,
118 IXGBE_TX_FLAGS_IPV4 = 0x10,
119 IXGBE_TX_FLAGS_CSUM = 0x20,
120
121
122 IXGBE_TX_FLAGS_SW_VLAN = 0x40,
123 IXGBE_TX_FLAGS_FCOE = 0x80,
124};
125
126
127#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
128#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
129#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
130#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
131
132#define IXGBE_MAX_VF_MC_ENTRIES 30
133#define IXGBE_MAX_VF_FUNCTIONS 64
134#define IXGBE_MAX_VFTA_ENTRIES 128
135#define MAX_EMULATION_MAC_ADDRS 16
136#define IXGBE_MAX_PF_MACVLANS 15
137#define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
138#define IXGBE_82599_VF_DEVICE_ID 0x10ED
139#define IXGBE_X540_VF_DEVICE_ID 0x1515
140
141struct vf_data_storage {
142 struct pci_dev *vfdev;
143 unsigned char vf_mac_addresses[ETH_ALEN];
144 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
145 u16 num_vf_mc_hashes;
146 bool clear_to_send;
147 bool pf_set_mac;
148 u16 pf_vlan;
149 u16 pf_qos;
150 u16 tx_rate;
151 u8 spoofchk_enabled;
152 bool rss_query_enabled;
153 u8 trusted;
154 int xcast_mode;
155 unsigned int vf_api;
156};
157
158enum ixgbevf_xcast_modes {
159 IXGBEVF_XCAST_MODE_NONE = 0,
160 IXGBEVF_XCAST_MODE_MULTI,
161 IXGBEVF_XCAST_MODE_ALLMULTI,
162};
163
164struct vf_macvlans {
165 struct list_head l;
166 int vf;
167 bool free;
168 bool is_macvlan;
169 u8 vf_macvlan[ETH_ALEN];
170};
171
172#define IXGBE_MAX_TXD_PWR 14
173#define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR)
174
175
176#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
177#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
178
179
180
181struct ixgbe_tx_buffer {
182 union ixgbe_adv_tx_desc *next_to_watch;
183 unsigned long time_stamp;
184 struct sk_buff *skb;
185 unsigned int bytecount;
186 unsigned short gso_segs;
187 __be16 protocol;
188 DEFINE_DMA_UNMAP_ADDR(dma);
189 DEFINE_DMA_UNMAP_LEN(len);
190 u32 tx_flags;
191};
192
193struct ixgbe_rx_buffer {
194 struct sk_buff *skb;
195 dma_addr_t dma;
196 struct page *page;
197 unsigned int page_offset;
198};
199
200struct ixgbe_queue_stats {
201 u64 packets;
202 u64 bytes;
203#ifdef BP_EXTENDED_STATS
204 u64 yields;
205 u64 misses;
206 u64 cleaned;
207#endif
208};
209
210struct ixgbe_tx_queue_stats {
211 u64 restart_queue;
212 u64 tx_busy;
213 u64 tx_done_old;
214};
215
216struct ixgbe_rx_queue_stats {
217 u64 rsc_count;
218 u64 rsc_flush;
219 u64 non_eop_descs;
220 u64 alloc_rx_page_failed;
221 u64 alloc_rx_buff_failed;
222 u64 csum_err;
223};
224
225#define IXGBE_TS_HDR_LEN 8
226
227enum ixgbe_ring_state_t {
228 __IXGBE_TX_FDIR_INIT_DONE,
229 __IXGBE_TX_XPS_INIT_DONE,
230 __IXGBE_TX_DETECT_HANG,
231 __IXGBE_HANG_CHECK_ARMED,
232 __IXGBE_RX_RSC_ENABLED,
233 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
234 __IXGBE_RX_FCOE,
235};
236
237struct ixgbe_fwd_adapter {
238 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
239 struct net_device *netdev;
240 struct ixgbe_adapter *real_adapter;
241 unsigned int tx_base_queue;
242 unsigned int rx_base_queue;
243 int pool;
244};
245
246#define check_for_tx_hang(ring) \
247 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
248#define set_check_for_tx_hang(ring) \
249 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
250#define clear_check_for_tx_hang(ring) \
251 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
252#define ring_is_rsc_enabled(ring) \
253 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
254#define set_ring_rsc_enabled(ring) \
255 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
256#define clear_ring_rsc_enabled(ring) \
257 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
258struct ixgbe_ring {
259 struct ixgbe_ring *next;
260 struct ixgbe_q_vector *q_vector;
261 struct net_device *netdev;
262 struct device *dev;
263 struct ixgbe_fwd_adapter *l2_accel_priv;
264 void *desc;
265 union {
266 struct ixgbe_tx_buffer *tx_buffer_info;
267 struct ixgbe_rx_buffer *rx_buffer_info;
268 };
269 unsigned long state;
270 u8 __iomem *tail;
271 dma_addr_t dma;
272 unsigned int size;
273
274 u16 count;
275
276 u8 queue_index;
277 u8 reg_idx;
278
279
280
281
282 u16 next_to_use;
283 u16 next_to_clean;
284
285 unsigned long last_rx_timestamp;
286
287 union {
288 u16 next_to_alloc;
289 struct {
290 u8 atr_sample_rate;
291 u8 atr_count;
292 };
293 };
294
295 u8 dcb_tc;
296 struct ixgbe_queue_stats stats;
297 struct u64_stats_sync syncp;
298 union {
299 struct ixgbe_tx_queue_stats tx_stats;
300 struct ixgbe_rx_queue_stats rx_stats;
301 };
302} ____cacheline_internodealigned_in_smp;
303
304enum ixgbe_ring_f_enum {
305 RING_F_NONE = 0,
306 RING_F_VMDQ,
307 RING_F_RSS,
308 RING_F_FDIR,
309#ifdef IXGBE_FCOE
310 RING_F_FCOE,
311#endif
312
313 RING_F_ARRAY_SIZE
314};
315
316#define IXGBE_MAX_RSS_INDICES 16
317#define IXGBE_MAX_RSS_INDICES_X550 63
318#define IXGBE_MAX_VMDQ_INDICES 64
319#define IXGBE_MAX_FDIR_INDICES 63
320#define IXGBE_MAX_FCOE_INDICES 8
321#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
322#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
323#define IXGBE_MAX_L2A_QUEUES 4
324#define IXGBE_BAD_L2A_QUEUE 3
325#define IXGBE_MAX_MACVLANS 31
326#define IXGBE_MAX_DCBMACVLANS 8
327
328struct ixgbe_ring_feature {
329 u16 limit;
330 u16 indices;
331 u16 mask;
332 u16 offset;
333} ____cacheline_internodealigned_in_smp;
334
335#define IXGBE_82599_VMDQ_8Q_MASK 0x78
336#define IXGBE_82599_VMDQ_4Q_MASK 0x7C
337#define IXGBE_82599_VMDQ_2Q_MASK 0x7E
338
339
340
341
342
343
344static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
345{
346#ifdef IXGBE_FCOE
347 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
348 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K :
349 IXGBE_RXBUFFER_3K;
350#endif
351 return IXGBE_RXBUFFER_2K;
352}
353
354static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
355{
356#ifdef IXGBE_FCOE
357 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
358 return (PAGE_SIZE < 8192) ? 1 : 0;
359#endif
360 return 0;
361}
362#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
363
364struct ixgbe_ring_container {
365 struct ixgbe_ring *ring;
366 unsigned int total_bytes;
367 unsigned int total_packets;
368 u16 work_limit;
369 u8 count;
370 u8 itr;
371};
372
373
374#define ixgbe_for_each_ring(pos, head) \
375 for (pos = (head).ring; pos != NULL; pos = pos->next)
376
377#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
378 ? 8 : 1)
379#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
380
381
382
383
384struct ixgbe_q_vector {
385 struct ixgbe_adapter *adapter;
386#ifdef CONFIG_IXGBE_DCA
387 int cpu;
388#endif
389 u16 v_idx;
390
391
392 u16 itr;
393 struct ixgbe_ring_container rx, tx;
394
395 struct napi_struct napi;
396 cpumask_t affinity_mask;
397 int numa_node;
398 struct rcu_head rcu;
399 char name[IFNAMSIZ + 9];
400
401#ifdef CONFIG_NET_RX_BUSY_POLL
402 atomic_t state;
403#endif
404
405
406 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
407};
408
409#ifdef CONFIG_NET_RX_BUSY_POLL
410enum ixgbe_qv_state_t {
411 IXGBE_QV_STATE_IDLE = 0,
412 IXGBE_QV_STATE_NAPI,
413 IXGBE_QV_STATE_POLL,
414 IXGBE_QV_STATE_DISABLE
415};
416
417static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
418{
419
420 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
421}
422
423
424static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
425{
426 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
427 IXGBE_QV_STATE_NAPI);
428#ifdef BP_EXTENDED_STATS
429 if (rc != IXGBE_QV_STATE_IDLE)
430 q_vector->tx.ring->stats.yields++;
431#endif
432
433 return rc == IXGBE_QV_STATE_IDLE;
434}
435
436
437static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
438{
439 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI);
440
441
442 if (q_vector->napi.gro_list)
443 napi_gro_flush(&q_vector->napi, false);
444
445
446 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
447}
448
449
450static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
451{
452 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
453 IXGBE_QV_STATE_POLL);
454#ifdef BP_EXTENDED_STATS
455 if (rc != IXGBE_QV_STATE_IDLE)
456 q_vector->rx.ring->stats.yields++;
457#endif
458 return rc == IXGBE_QV_STATE_IDLE;
459}
460
461
462static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
463{
464 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL);
465
466
467 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
468}
469
470
471static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
472{
473 return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL;
474}
475
476
477static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
478{
479 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
480 IXGBE_QV_STATE_DISABLE);
481
482 return rc == IXGBE_QV_STATE_IDLE;
483}
484
485#else
486static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
487{
488}
489
490static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
491{
492 return true;
493}
494
495static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
496{
497 return false;
498}
499
500static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
501{
502 return false;
503}
504
505static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
506{
507 return false;
508}
509
510static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
511{
512 return false;
513}
514
515static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
516{
517 return true;
518}
519
520#endif
521
522#ifdef CONFIG_IXGBE_HWMON
523
524#define IXGBE_HWMON_TYPE_LOC 0
525#define IXGBE_HWMON_TYPE_TEMP 1
526#define IXGBE_HWMON_TYPE_CAUTION 2
527#define IXGBE_HWMON_TYPE_MAX 3
528
529struct hwmon_attr {
530 struct device_attribute dev_attr;
531 struct ixgbe_hw *hw;
532 struct ixgbe_thermal_diode_data *sensor;
533 char name[12];
534};
535
536struct hwmon_buff {
537 struct attribute_group group;
538 const struct attribute_group *groups[2];
539 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
540 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
541 unsigned int n_hwmon;
542};
543#endif
544
545
546
547
548
549#define IXGBE_MIN_RSC_ITR 24
550#define IXGBE_100K_ITR 40
551#define IXGBE_20K_ITR 200
552#define IXGBE_12K_ITR 336
553
554
555static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
556 const u32 stat_err_bits)
557{
558 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
559}
560
561static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
562{
563 u16 ntc = ring->next_to_clean;
564 u16 ntu = ring->next_to_use;
565
566 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
567}
568
569#define IXGBE_RX_DESC(R, i) \
570 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
571#define IXGBE_TX_DESC(R, i) \
572 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
573#define IXGBE_TX_CTXTDESC(R, i) \
574 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
575
576#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728
577#ifdef IXGBE_FCOE
578
579#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
580#endif
581
582#define OTHER_VECTOR 1
583#define NON_Q_VECTORS (OTHER_VECTOR)
584
585#define MAX_MSIX_VECTORS_82599 64
586#define MAX_Q_VECTORS_82599 64
587#define MAX_MSIX_VECTORS_82598 18
588#define MAX_Q_VECTORS_82598 16
589
590struct ixgbe_mac_addr {
591 u8 addr[ETH_ALEN];
592 u16 pool;
593 u16 state;
594};
595
596#define IXGBE_MAC_STATE_DEFAULT 0x1
597#define IXGBE_MAC_STATE_MODIFIED 0x2
598#define IXGBE_MAC_STATE_IN_USE 0x4
599
600#define MAX_Q_VECTORS MAX_Q_VECTORS_82599
601#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
602
603#define MIN_MSIX_Q_VECTORS 1
604#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
605
606
607#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
608#define IXGBE_SFP_POLL_JIFFIES (2 * HZ)
609
610
611struct ixgbe_adapter {
612 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
613
614 struct net_device *netdev;
615 struct pci_dev *pdev;
616
617 unsigned long state;
618
619
620
621
622 u32 flags;
623#define IXGBE_FLAG_MSI_ENABLED BIT(1)
624#define IXGBE_FLAG_MSIX_ENABLED BIT(3)
625#define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4)
626#define IXGBE_FLAG_RX_PS_CAPABLE BIT(5)
627#define IXGBE_FLAG_RX_PS_ENABLED BIT(6)
628#define IXGBE_FLAG_DCA_ENABLED BIT(8)
629#define IXGBE_FLAG_DCA_CAPABLE BIT(9)
630#define IXGBE_FLAG_IMIR_ENABLED BIT(10)
631#define IXGBE_FLAG_MQ_CAPABLE BIT(11)
632#define IXGBE_FLAG_DCB_ENABLED BIT(12)
633#define IXGBE_FLAG_VMDQ_CAPABLE BIT(13)
634#define IXGBE_FLAG_VMDQ_ENABLED BIT(14)
635#define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15)
636#define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16)
637#define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17)
638#define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18)
639#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19)
640#define IXGBE_FLAG_FCOE_CAPABLE BIT(20)
641#define IXGBE_FLAG_FCOE_ENABLED BIT(21)
642#define IXGBE_FLAG_SRIOV_CAPABLE BIT(22)
643#define IXGBE_FLAG_SRIOV_ENABLED BIT(23)
644#define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24)
645#define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25)
646#define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26)
647#define IXGBE_FLAG_DCB_CAPABLE BIT(27)
648#define IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE BIT(28)
649
650 u32 flags2;
651#define IXGBE_FLAG2_RSC_CAPABLE BIT(0)
652#define IXGBE_FLAG2_RSC_ENABLED BIT(1)
653#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2)
654#define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3)
655#define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4)
656#define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5)
657#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7)
658#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8)
659#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9)
660#define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10)
661#define IXGBE_FLAG2_PHY_INTERRUPT BIT(11)
662#define IXGBE_FLAG2_UDP_TUN_REREG_NEEDED BIT(12)
663#define IXGBE_FLAG2_VLAN_PROMISC BIT(13)
664
665
666 int num_tx_queues;
667 u16 tx_itr_setting;
668 u16 tx_work_limit;
669
670
671 int num_rx_queues;
672 u16 rx_itr_setting;
673
674
675 __be16 vxlan_port;
676 __be16 geneve_port;
677
678
679 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
680
681 u64 restart_queue;
682 u64 lsc_int;
683 u32 tx_timeout_count;
684
685
686 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
687 int num_rx_pools;
688 int num_rx_queues_per_pool;
689 u64 hw_csum_rx_error;
690 u64 hw_rx_no_dma_resources;
691 u64 rsc_total_count;
692 u64 rsc_total_flush;
693 u64 non_eop_descs;
694 u32 alloc_rx_page_failed;
695 u32 alloc_rx_buff_failed;
696
697 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
698
699
700 struct ieee_pfc *ixgbe_ieee_pfc;
701 struct ieee_ets *ixgbe_ieee_ets;
702 struct ixgbe_dcb_config dcb_cfg;
703 struct ixgbe_dcb_config temp_dcb_cfg;
704 u8 dcb_set_bitmap;
705 u8 dcbx_cap;
706 enum ixgbe_fc_mode last_lfc_mode;
707
708 int num_q_vectors;
709 int max_q_vectors;
710 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
711 struct msix_entry *msix_entries;
712
713 u32 test_icr;
714 struct ixgbe_ring test_tx_ring;
715 struct ixgbe_ring test_rx_ring;
716
717
718 struct ixgbe_hw hw;
719 u16 msg_enable;
720 struct ixgbe_hw_stats stats;
721
722 u64 tx_busy;
723 unsigned int tx_ring_count;
724 unsigned int rx_ring_count;
725
726 u32 link_speed;
727 bool link_up;
728 unsigned long sfp_poll_time;
729 unsigned long link_check_timeout;
730
731 struct timer_list service_timer;
732 struct work_struct service_task;
733
734 struct hlist_head fdir_filter_list;
735 unsigned long fdir_overflow;
736 union ixgbe_atr_input fdir_mask;
737 int fdir_filter_count;
738 u32 fdir_pballoc;
739 u32 atr_sample_rate;
740 spinlock_t fdir_perfect_lock;
741
742#ifdef IXGBE_FCOE
743 struct ixgbe_fcoe fcoe;
744#endif
745 u8 __iomem *io_addr;
746 u32 wol;
747
748 u16 bridge_mode;
749
750 u16 eeprom_verh;
751 u16 eeprom_verl;
752 u16 eeprom_cap;
753
754 u32 interrupt_event;
755 u32 led_reg;
756
757 struct ptp_clock *ptp_clock;
758 struct ptp_clock_info ptp_caps;
759 struct work_struct ptp_tx_work;
760 struct sk_buff *ptp_tx_skb;
761 struct hwtstamp_config tstamp_config;
762 unsigned long ptp_tx_start;
763 unsigned long last_overflow_check;
764 unsigned long last_rx_ptp_check;
765 unsigned long last_rx_timestamp;
766 spinlock_t tmreg_lock;
767 struct cyclecounter hw_cc;
768 struct timecounter hw_tc;
769 u32 base_incval;
770 u32 tx_hwtstamp_timeouts;
771 u32 rx_hwtstamp_cleared;
772 void (*ptp_setup_sdp)(struct ixgbe_adapter *);
773
774
775 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
776 unsigned int num_vfs;
777 struct vf_data_storage *vfinfo;
778 int vf_rate_link_speed;
779 struct vf_macvlans vf_mvs;
780 struct vf_macvlans *mv_list;
781
782 u32 timer_event_accumulator;
783 u32 vferr_refcount;
784 struct ixgbe_mac_addr *mac_table;
785 struct kobject *info_kobj;
786#ifdef CONFIG_IXGBE_HWMON
787 struct hwmon_buff *ixgbe_hwmon_buff;
788#endif
789#ifdef CONFIG_DEBUG_FS
790 struct dentry *ixgbe_dbg_adapter;
791#endif
792
793 u8 default_up;
794 unsigned long fwd_bitmask;
795
796#define IXGBE_MAX_LINK_HANDLE 10
797 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE];
798 unsigned long tables;
799
800
801
802
803#define IXGBE_MAX_RETA_ENTRIES 512
804 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES];
805
806#define IXGBE_RSS_KEY_SIZE 40
807 u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)];
808};
809
810static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
811{
812 switch (adapter->hw.mac.type) {
813 case ixgbe_mac_82598EB:
814 case ixgbe_mac_82599EB:
815 case ixgbe_mac_X540:
816 return IXGBE_MAX_RSS_INDICES;
817 case ixgbe_mac_X550:
818 case ixgbe_mac_X550EM_x:
819 case ixgbe_mac_x550em_a:
820 return IXGBE_MAX_RSS_INDICES_X550;
821 default:
822 return 0;
823 }
824}
825
826struct ixgbe_fdir_filter {
827 struct hlist_node fdir_node;
828 union ixgbe_atr_input filter;
829 u16 sw_idx;
830 u64 action;
831};
832
833enum ixgbe_state_t {
834 __IXGBE_TESTING,
835 __IXGBE_RESETTING,
836 __IXGBE_DOWN,
837 __IXGBE_DISABLED,
838 __IXGBE_REMOVING,
839 __IXGBE_SERVICE_SCHED,
840 __IXGBE_SERVICE_INITED,
841 __IXGBE_IN_SFP_INIT,
842 __IXGBE_PTP_RUNNING,
843 __IXGBE_PTP_TX_IN_PROGRESS,
844 __IXGBE_RESET_REQUESTED,
845};
846
847struct ixgbe_cb {
848 union {
849 struct sk_buff *head;
850 struct sk_buff *tail;
851 };
852 dma_addr_t dma;
853 u16 append_cnt;
854 bool page_released;
855};
856#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
857
858enum ixgbe_boards {
859 board_82598,
860 board_82599,
861 board_X540,
862 board_X550,
863 board_X550EM_x,
864 board_x550em_a,
865};
866
867extern const struct ixgbe_info ixgbe_82598_info;
868extern const struct ixgbe_info ixgbe_82599_info;
869extern const struct ixgbe_info ixgbe_X540_info;
870extern const struct ixgbe_info ixgbe_X550_info;
871extern const struct ixgbe_info ixgbe_X550EM_x_info;
872extern const struct ixgbe_info ixgbe_x550em_a_info;
873#ifdef CONFIG_IXGBE_DCB
874extern const struct dcbnl_rtnl_ops dcbnl_ops;
875#endif
876
877extern char ixgbe_driver_name[];
878extern const char ixgbe_driver_version[];
879#ifdef IXGBE_FCOE
880extern char ixgbe_default_device_descr[];
881#endif
882
883int ixgbe_open(struct net_device *netdev);
884int ixgbe_close(struct net_device *netdev);
885void ixgbe_up(struct ixgbe_adapter *adapter);
886void ixgbe_down(struct ixgbe_adapter *adapter);
887void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
888void ixgbe_reset(struct ixgbe_adapter *adapter);
889void ixgbe_set_ethtool_ops(struct net_device *netdev);
890int ixgbe_setup_rx_resources(struct ixgbe_ring *);
891int ixgbe_setup_tx_resources(struct ixgbe_ring *);
892void ixgbe_free_rx_resources(struct ixgbe_ring *);
893void ixgbe_free_tx_resources(struct ixgbe_ring *);
894void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
895void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
896void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *);
897void ixgbe_update_stats(struct ixgbe_adapter *adapter);
898int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
899bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
900 u16 subdevice_id);
901#ifdef CONFIG_PCI_IOV
902void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
903#endif
904int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
905 const u8 *addr, u16 queue);
906int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
907 const u8 *addr, u16 queue);
908void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid);
909void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
910netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
911 struct ixgbe_ring *);
912void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
913 struct ixgbe_tx_buffer *);
914void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
915void ixgbe_write_eitr(struct ixgbe_q_vector *);
916int ixgbe_poll(struct napi_struct *napi, int budget);
917int ethtool_ioctl(struct ifreq *ifr);
918s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
919s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
920s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
921s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
922 union ixgbe_atr_hash_dword input,
923 union ixgbe_atr_hash_dword common,
924 u8 queue);
925s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
926 union ixgbe_atr_input *input_mask);
927s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
928 union ixgbe_atr_input *input,
929 u16 soft_id, u8 queue);
930s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
931 union ixgbe_atr_input *input,
932 u16 soft_id);
933void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
934 union ixgbe_atr_input *mask);
935int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
936 struct ixgbe_fdir_filter *input,
937 u16 sw_idx);
938void ixgbe_set_rx_mode(struct net_device *netdev);
939#ifdef CONFIG_IXGBE_DCB
940void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
941#endif
942int ixgbe_setup_tc(struct net_device *dev, u8 tc);
943void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
944void ixgbe_do_reset(struct net_device *netdev);
945#ifdef CONFIG_IXGBE_HWMON
946void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
947int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
948#endif
949#ifdef IXGBE_FCOE
950void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
951int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
952 u8 *hdr_len);
953int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
954 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
955int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
956 struct scatterlist *sgl, unsigned int sgc);
957int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
958 struct scatterlist *sgl, unsigned int sgc);
959int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
960int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
961void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
962int ixgbe_fcoe_enable(struct net_device *netdev);
963int ixgbe_fcoe_disable(struct net_device *netdev);
964#ifdef CONFIG_IXGBE_DCB
965u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
966u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
967#endif
968int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
969int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
970 struct netdev_fcoe_hbainfo *info);
971u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
972#endif
973#ifdef CONFIG_DEBUG_FS
974void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
975void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
976void ixgbe_dbg_init(void);
977void ixgbe_dbg_exit(void);
978#else
979static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
980static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
981static inline void ixgbe_dbg_init(void) {}
982static inline void ixgbe_dbg_exit(void) {}
983#endif
984static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
985{
986 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
987}
988
989void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
990void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
991void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
992void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
993void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
994void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *);
995void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb);
996static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
997 union ixgbe_adv_rx_desc *rx_desc,
998 struct sk_buff *skb)
999{
1000 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) {
1001 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb);
1002 return;
1003 }
1004
1005 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1006 return;
1007
1008 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
1009
1010
1011
1012
1013 rx_ring->last_rx_timestamp = jiffies;
1014}
1015
1016int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
1017int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
1018void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
1019void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
1020void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter);
1021#ifdef CONFIG_PCI_IOV
1022void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
1023#endif
1024
1025netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
1026 struct ixgbe_adapter *adapter,
1027 struct ixgbe_ring *tx_ring);
1028u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);
1029void ixgbe_store_reta(struct ixgbe_adapter *adapter);
1030s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1031 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
1032#endif
1033