linux/drivers/net/ethernet/neterion/s2io.h
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   1/************************************************************************
   2 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3 * Copyright(c) 2002-2010 Exar Corp.
   4
   5 * This software may be used and distributed according to the terms of
   6 * the GNU General Public License (GPL), incorporated herein by reference.
   7 * Drivers based on or derived from this code fall under the GPL and must
   8 * retain the authorship, copyright and license notice.  This file is not
   9 * a complete program and may only be used when the entire operating
  10 * system is licensed under the GPL.
  11 * See the file COPYING in this distribution for more information.
  12 ************************************************************************/
  13#ifndef _S2IO_H
  14#define _S2IO_H
  15
  16#define TBD 0
  17#define s2BIT(loc)              (0x8000000000000000ULL >> (loc))
  18#define vBIT(val, loc, sz)      (((u64)val) << (64-loc-sz))
  19#define INV(d)  ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
  20
  21#undef SUCCESS
  22#define SUCCESS 0
  23#define FAILURE -1
  24#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
  25#define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
  26#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
  27#define S2IO_BIT_RESET 1
  28#define S2IO_BIT_SET 2
  29#define CHECKBIT(value, nbit) (value & (1 << nbit))
  30
  31/* Maximum time to flicker LED when asked to identify NIC using ethtool */
  32#define MAX_FLICKER_TIME        60000 /* 60 Secs */
  33
  34/* Maximum outstanding splits to be configured into xena. */
  35enum {
  36        XENA_ONE_SPLIT_TRANSACTION = 0,
  37        XENA_TWO_SPLIT_TRANSACTION = 1,
  38        XENA_THREE_SPLIT_TRANSACTION = 2,
  39        XENA_FOUR_SPLIT_TRANSACTION = 3,
  40        XENA_EIGHT_SPLIT_TRANSACTION = 4,
  41        XENA_TWELVE_SPLIT_TRANSACTION = 5,
  42        XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
  43        XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
  44};
  45#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
  46
  47/*  OS concerned variables and constants */
  48#define WATCH_DOG_TIMEOUT               15*HZ
  49#define EFILL                           0x1234
  50#define ALIGN_SIZE                      127
  51#define PCIX_COMMAND_REGISTER           0x62
  52
  53/*
  54 * Debug related variables.
  55 */
  56/* different debug levels. */
  57#define ERR_DBG         0
  58#define INIT_DBG        1
  59#define INFO_DBG        2
  60#define TX_DBG          3
  61#define INTR_DBG        4
  62
  63/* Global variable that defines the present debug level of the driver. */
  64static int debug_level = ERR_DBG;
  65
  66/* DEBUG message print. */
  67#define DBG_PRINT(dbg_level, fmt, args...) do {                 \
  68        if (dbg_level <= debug_level)                           \
  69                pr_info(fmt, ##args);                           \
  70        } while (0)
  71
  72/* Protocol assist features of the NIC */
  73#define L3_CKSUM_OK 0xFFFF
  74#define L4_CKSUM_OK 0xFFFF
  75#define S2IO_JUMBO_SIZE 9600
  76
  77/* Driver statistics maintained by driver */
  78struct swStat {
  79        unsigned long long single_ecc_errs;
  80        unsigned long long double_ecc_errs;
  81        unsigned long long parity_err_cnt;
  82        unsigned long long serious_err_cnt;
  83        unsigned long long soft_reset_cnt;
  84        unsigned long long fifo_full_cnt;
  85        unsigned long long ring_full_cnt[8];
  86        /* LRO statistics */
  87        unsigned long long clubbed_frms_cnt;
  88        unsigned long long sending_both;
  89        unsigned long long outof_sequence_pkts;
  90        unsigned long long flush_max_pkts;
  91        unsigned long long sum_avg_pkts_aggregated;
  92        unsigned long long num_aggregations;
  93        /* Other statistics */
  94        unsigned long long mem_alloc_fail_cnt;
  95        unsigned long long pci_map_fail_cnt;
  96        unsigned long long watchdog_timer_cnt;
  97        unsigned long long mem_allocated;
  98        unsigned long long mem_freed;
  99        unsigned long long link_up_cnt;
 100        unsigned long long link_down_cnt;
 101        unsigned long long link_up_time;
 102        unsigned long long link_down_time;
 103
 104        /* Transfer Code statistics */
 105        unsigned long long tx_buf_abort_cnt;
 106        unsigned long long tx_desc_abort_cnt;
 107        unsigned long long tx_parity_err_cnt;
 108        unsigned long long tx_link_loss_cnt;
 109        unsigned long long tx_list_proc_err_cnt;
 110
 111        unsigned long long rx_parity_err_cnt;
 112        unsigned long long rx_abort_cnt;
 113        unsigned long long rx_parity_abort_cnt;
 114        unsigned long long rx_rda_fail_cnt;
 115        unsigned long long rx_unkn_prot_cnt;
 116        unsigned long long rx_fcs_err_cnt;
 117        unsigned long long rx_buf_size_err_cnt;
 118        unsigned long long rx_rxd_corrupt_cnt;
 119        unsigned long long rx_unkn_err_cnt;
 120
 121        /* Error/alarm statistics*/
 122        unsigned long long tda_err_cnt;
 123        unsigned long long pfc_err_cnt;
 124        unsigned long long pcc_err_cnt;
 125        unsigned long long tti_err_cnt;
 126        unsigned long long lso_err_cnt;
 127        unsigned long long tpa_err_cnt;
 128        unsigned long long sm_err_cnt;
 129        unsigned long long mac_tmac_err_cnt;
 130        unsigned long long mac_rmac_err_cnt;
 131        unsigned long long xgxs_txgxs_err_cnt;
 132        unsigned long long xgxs_rxgxs_err_cnt;
 133        unsigned long long rc_err_cnt;
 134        unsigned long long prc_pcix_err_cnt;
 135        unsigned long long rpa_err_cnt;
 136        unsigned long long rda_err_cnt;
 137        unsigned long long rti_err_cnt;
 138        unsigned long long mc_err_cnt;
 139
 140};
 141
 142/* Xpak releated alarm and warnings */
 143struct xpakStat {
 144        u64 alarm_transceiver_temp_high;
 145        u64 alarm_transceiver_temp_low;
 146        u64 alarm_laser_bias_current_high;
 147        u64 alarm_laser_bias_current_low;
 148        u64 alarm_laser_output_power_high;
 149        u64 alarm_laser_output_power_low;
 150        u64 warn_transceiver_temp_high;
 151        u64 warn_transceiver_temp_low;
 152        u64 warn_laser_bias_current_high;
 153        u64 warn_laser_bias_current_low;
 154        u64 warn_laser_output_power_high;
 155        u64 warn_laser_output_power_low;
 156        u64 xpak_regs_stat;
 157        u32 xpak_timer_count;
 158};
 159
 160
 161/* The statistics block of Xena */
 162struct stat_block {
 163/* Tx MAC statistics counters. */
 164        __le32 tmac_data_octets;
 165        __le32 tmac_frms;
 166        __le64 tmac_drop_frms;
 167        __le32 tmac_bcst_frms;
 168        __le32 tmac_mcst_frms;
 169        __le64 tmac_pause_ctrl_frms;
 170        __le32 tmac_ucst_frms;
 171        __le32 tmac_ttl_octets;
 172        __le32 tmac_any_err_frms;
 173        __le32 tmac_nucst_frms;
 174        __le64 tmac_ttl_less_fb_octets;
 175        __le64 tmac_vld_ip_octets;
 176        __le32 tmac_drop_ip;
 177        __le32 tmac_vld_ip;
 178        __le32 tmac_rst_tcp;
 179        __le32 tmac_icmp;
 180        __le64 tmac_tcp;
 181        __le32 reserved_0;
 182        __le32 tmac_udp;
 183
 184/* Rx MAC Statistics counters. */
 185        __le32 rmac_data_octets;
 186        __le32 rmac_vld_frms;
 187        __le64 rmac_fcs_err_frms;
 188        __le64 rmac_drop_frms;
 189        __le32 rmac_vld_bcst_frms;
 190        __le32 rmac_vld_mcst_frms;
 191        __le32 rmac_out_rng_len_err_frms;
 192        __le32 rmac_in_rng_len_err_frms;
 193        __le64 rmac_long_frms;
 194        __le64 rmac_pause_ctrl_frms;
 195        __le64 rmac_unsup_ctrl_frms;
 196        __le32 rmac_accepted_ucst_frms;
 197        __le32 rmac_ttl_octets;
 198        __le32 rmac_discarded_frms;
 199        __le32 rmac_accepted_nucst_frms;
 200        __le32 reserved_1;
 201        __le32 rmac_drop_events;
 202        __le64 rmac_ttl_less_fb_octets;
 203        __le64 rmac_ttl_frms;
 204        __le64 reserved_2;
 205        __le32 rmac_usized_frms;
 206        __le32 reserved_3;
 207        __le32 rmac_frag_frms;
 208        __le32 rmac_osized_frms;
 209        __le32 reserved_4;
 210        __le32 rmac_jabber_frms;
 211        __le64 rmac_ttl_64_frms;
 212        __le64 rmac_ttl_65_127_frms;
 213        __le64 reserved_5;
 214        __le64 rmac_ttl_128_255_frms;
 215        __le64 rmac_ttl_256_511_frms;
 216        __le64 reserved_6;
 217        __le64 rmac_ttl_512_1023_frms;
 218        __le64 rmac_ttl_1024_1518_frms;
 219        __le32 rmac_ip;
 220        __le32 reserved_7;
 221        __le64 rmac_ip_octets;
 222        __le32 rmac_drop_ip;
 223        __le32 rmac_hdr_err_ip;
 224        __le32 reserved_8;
 225        __le32 rmac_icmp;
 226        __le64 rmac_tcp;
 227        __le32 rmac_err_drp_udp;
 228        __le32 rmac_udp;
 229        __le64 rmac_xgmii_err_sym;
 230        __le64 rmac_frms_q0;
 231        __le64 rmac_frms_q1;
 232        __le64 rmac_frms_q2;
 233        __le64 rmac_frms_q3;
 234        __le64 rmac_frms_q4;
 235        __le64 rmac_frms_q5;
 236        __le64 rmac_frms_q6;
 237        __le64 rmac_frms_q7;
 238        __le16 rmac_full_q3;
 239        __le16 rmac_full_q2;
 240        __le16 rmac_full_q1;
 241        __le16 rmac_full_q0;
 242        __le16 rmac_full_q7;
 243        __le16 rmac_full_q6;
 244        __le16 rmac_full_q5;
 245        __le16 rmac_full_q4;
 246        __le32 reserved_9;
 247        __le32 rmac_pause_cnt;
 248        __le64 rmac_xgmii_data_err_cnt;
 249        __le64 rmac_xgmii_ctrl_err_cnt;
 250        __le32 rmac_err_tcp;
 251        __le32 rmac_accepted_ip;
 252
 253/* PCI/PCI-X Read transaction statistics. */
 254        __le32 new_rd_req_cnt;
 255        __le32 rd_req_cnt;
 256        __le32 rd_rtry_cnt;
 257        __le32 new_rd_req_rtry_cnt;
 258
 259/* PCI/PCI-X Write/Read transaction statistics. */
 260        __le32 wr_req_cnt;
 261        __le32 wr_rtry_rd_ack_cnt;
 262        __le32 new_wr_req_rtry_cnt;
 263        __le32 new_wr_req_cnt;
 264        __le32 wr_disc_cnt;
 265        __le32 wr_rtry_cnt;
 266
 267/*      PCI/PCI-X Write / DMA Transaction statistics. */
 268        __le32 txp_wr_cnt;
 269        __le32 rd_rtry_wr_ack_cnt;
 270        __le32 txd_wr_cnt;
 271        __le32 txd_rd_cnt;
 272        __le32 rxd_wr_cnt;
 273        __le32 rxd_rd_cnt;
 274        __le32 rxf_wr_cnt;
 275        __le32 txf_rd_cnt;
 276
 277/* Tx MAC statistics overflow counters. */
 278        __le32 tmac_data_octets_oflow;
 279        __le32 tmac_frms_oflow;
 280        __le32 tmac_bcst_frms_oflow;
 281        __le32 tmac_mcst_frms_oflow;
 282        __le32 tmac_ucst_frms_oflow;
 283        __le32 tmac_ttl_octets_oflow;
 284        __le32 tmac_any_err_frms_oflow;
 285        __le32 tmac_nucst_frms_oflow;
 286        __le64 tmac_vlan_frms;
 287        __le32 tmac_drop_ip_oflow;
 288        __le32 tmac_vld_ip_oflow;
 289        __le32 tmac_rst_tcp_oflow;
 290        __le32 tmac_icmp_oflow;
 291        __le32 tpa_unknown_protocol;
 292        __le32 tmac_udp_oflow;
 293        __le32 reserved_10;
 294        __le32 tpa_parse_failure;
 295
 296/* Rx MAC Statistics overflow counters. */
 297        __le32 rmac_data_octets_oflow;
 298        __le32 rmac_vld_frms_oflow;
 299        __le32 rmac_vld_bcst_frms_oflow;
 300        __le32 rmac_vld_mcst_frms_oflow;
 301        __le32 rmac_accepted_ucst_frms_oflow;
 302        __le32 rmac_ttl_octets_oflow;
 303        __le32 rmac_discarded_frms_oflow;
 304        __le32 rmac_accepted_nucst_frms_oflow;
 305        __le32 rmac_usized_frms_oflow;
 306        __le32 rmac_drop_events_oflow;
 307        __le32 rmac_frag_frms_oflow;
 308        __le32 rmac_osized_frms_oflow;
 309        __le32 rmac_ip_oflow;
 310        __le32 rmac_jabber_frms_oflow;
 311        __le32 rmac_icmp_oflow;
 312        __le32 rmac_drop_ip_oflow;
 313        __le32 rmac_err_drp_udp_oflow;
 314        __le32 rmac_udp_oflow;
 315        __le32 reserved_11;
 316        __le32 rmac_pause_cnt_oflow;
 317        __le64 rmac_ttl_1519_4095_frms;
 318        __le64 rmac_ttl_4096_8191_frms;
 319        __le64 rmac_ttl_8192_max_frms;
 320        __le64 rmac_ttl_gt_max_frms;
 321        __le64 rmac_osized_alt_frms;
 322        __le64 rmac_jabber_alt_frms;
 323        __le64 rmac_gt_max_alt_frms;
 324        __le64 rmac_vlan_frms;
 325        __le32 rmac_len_discard;
 326        __le32 rmac_fcs_discard;
 327        __le32 rmac_pf_discard;
 328        __le32 rmac_da_discard;
 329        __le32 rmac_red_discard;
 330        __le32 rmac_rts_discard;
 331        __le32 reserved_12;
 332        __le32 rmac_ingm_full_discard;
 333        __le32 reserved_13;
 334        __le32 rmac_accepted_ip_oflow;
 335        __le32 reserved_14;
 336        __le32 link_fault_cnt;
 337        u8  buffer[20];
 338        struct swStat sw_stat;
 339        struct xpakStat xpak_stat;
 340};
 341
 342/* Default value for 'vlan_strip_tag' configuration parameter */
 343#define NO_STRIP_IN_PROMISC 2
 344
 345/*
 346 * Structures representing different init time configuration
 347 * parameters of the NIC.
 348 */
 349
 350#define MAX_TX_FIFOS 8
 351#define MAX_RX_RINGS 8
 352
 353#define FIFO_DEFAULT_NUM        5
 354#define FIFO_UDP_MAX_NUM                        2 /* 0 - even, 1 -odd ports */
 355#define FIFO_OTHER_MAX_NUM                      1
 356
 357
 358#define MAX_RX_DESC_1  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 128)
 359#define MAX_RX_DESC_2  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 86)
 360#define MAX_TX_DESC    (MAX_AVAILABLE_TXDS)
 361
 362/* FIFO mappings for all possible number of fifos configured */
 363static const int fifo_map[][MAX_TX_FIFOS] = {
 364        {0, 0, 0, 0, 0, 0, 0, 0},
 365        {0, 0, 0, 0, 1, 1, 1, 1},
 366        {0, 0, 0, 1, 1, 1, 2, 2},
 367        {0, 0, 1, 1, 2, 2, 3, 3},
 368        {0, 0, 1, 1, 2, 2, 3, 4},
 369        {0, 0, 1, 1, 2, 3, 4, 5},
 370        {0, 0, 1, 2, 3, 4, 5, 6},
 371        {0, 1, 2, 3, 4, 5, 6, 7},
 372};
 373
 374static const u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
 375
 376/* Maintains Per FIFO related information. */
 377struct tx_fifo_config {
 378#define MAX_AVAILABLE_TXDS      8192
 379        u32 fifo_len;           /* specifies len of FIFO up to 8192, ie no of TxDLs */
 380/* Priority definition */
 381#define TX_FIFO_PRI_0               0   /*Highest */
 382#define TX_FIFO_PRI_1               1
 383#define TX_FIFO_PRI_2               2
 384#define TX_FIFO_PRI_3               3
 385#define TX_FIFO_PRI_4               4
 386#define TX_FIFO_PRI_5               5
 387#define TX_FIFO_PRI_6               6
 388#define TX_FIFO_PRI_7               7   /*lowest */
 389        u8 fifo_priority;       /* specifies pointer level for FIFO */
 390        /* user should not set twos fifos with same pri */
 391        u8 f_no_snoop;
 392#define NO_SNOOP_TXD                0x01
 393#define NO_SNOOP_TXD_BUFFER          0x02
 394};
 395
 396
 397/* Maintains per Ring related information */
 398struct rx_ring_config {
 399        u32 num_rxd;            /*No of RxDs per Rx Ring */
 400#define RX_RING_PRI_0               0   /* highest */
 401#define RX_RING_PRI_1               1
 402#define RX_RING_PRI_2               2
 403#define RX_RING_PRI_3               3
 404#define RX_RING_PRI_4               4
 405#define RX_RING_PRI_5               5
 406#define RX_RING_PRI_6               6
 407#define RX_RING_PRI_7               7   /* lowest */
 408
 409        u8 ring_priority;       /*Specifies service priority of ring */
 410        /* OSM should not set any two rings with same priority */
 411        u8 ring_org;            /*Organization of ring */
 412#define RING_ORG_BUFF1          0x01
 413#define RX_RING_ORG_BUFF3       0x03
 414#define RX_RING_ORG_BUFF5       0x05
 415
 416        u8 f_no_snoop;
 417#define NO_SNOOP_RXD                0x01
 418#define NO_SNOOP_RXD_BUFFER         0x02
 419};
 420
 421/* This structure provides contains values of the tunable parameters
 422 * of the H/W
 423 */
 424struct config_param {
 425/* Tx Side */
 426        u32 tx_fifo_num;        /*Number of Tx FIFOs */
 427
 428        /* 0-No steering, 1-Priority steering, 2-Default fifo map */
 429#define NO_STEERING                             0
 430#define TX_PRIORITY_STEERING                    0x1
 431#define TX_DEFAULT_STEERING                     0x2
 432        u8 tx_steering_type;
 433
 434        u8 fifo_mapping[MAX_TX_FIFOS];
 435        struct tx_fifo_config tx_cfg[MAX_TX_FIFOS];     /*Per-Tx FIFO config */
 436        u32 max_txds;           /*Max no. of Tx buffer descriptor per TxDL */
 437        u64 tx_intr_type;
 438#define INTA    0
 439#define MSI_X   2
 440        u8 intr_type;
 441        u8 napi;
 442
 443        /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
 444
 445/* Rx Side */
 446        u32 rx_ring_num;        /*Number of receive rings */
 447#define MAX_RX_BLOCKS_PER_RING  150
 448
 449        struct rx_ring_config rx_cfg[MAX_RX_RINGS];     /*Per-Rx Ring config */
 450
 451#define HEADER_ETHERNET_II_802_3_SIZE 14
 452#define HEADER_802_2_SIZE              3
 453#define HEADER_SNAP_SIZE               5
 454#define HEADER_VLAN_SIZE               4
 455
 456#define MIN_MTU                       46
 457#define MAX_PYLD                    1500
 458#define MAX_MTU                     (MAX_PYLD+18)
 459#define MAX_MTU_VLAN                (MAX_PYLD+22)
 460#define MAX_PYLD_JUMBO              9600
 461#define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)
 462#define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)
 463        u16 bus_speed;
 464        int max_mc_addr;        /* xena=64 herc=256 */
 465        int max_mac_addr;       /* xena=16 herc=64 */
 466        int mc_start_offset;    /* xena=16 herc=64 */
 467        u8 multiq;
 468};
 469
 470/* Structure representing MAC Addrs */
 471struct mac_addr {
 472        u8 mac_addr[ETH_ALEN];
 473};
 474
 475/* Structure that represent every FIFO element in the BAR1
 476 * Address location.
 477 */
 478struct TxFIFO_element {
 479        u64 TxDL_Pointer;
 480
 481        u64 List_Control;
 482#define TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
 483#define TX_FIFO_FIRST_LIST             s2BIT(14)
 484#define TX_FIFO_LAST_LIST              s2BIT(15)
 485#define TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
 486#define TX_FIFO_SPECIAL_FUNC           s2BIT(23)
 487#define TX_FIFO_DS_NO_SNOOP            s2BIT(31)
 488#define TX_FIFO_BUFF_NO_SNOOP          s2BIT(30)
 489};
 490
 491/* Tx descriptor structure */
 492struct TxD {
 493        u64 Control_1;
 494/* bit mask */
 495#define TXD_LIST_OWN_XENA       s2BIT(7)
 496#define TXD_T_CODE              (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
 497#define TXD_T_CODE_OK(val)      (|(val & TXD_T_CODE))
 498#define GET_TXD_T_CODE(val)     ((val & TXD_T_CODE)<<12)
 499#define TXD_GATHER_CODE         (s2BIT(22) | s2BIT(23))
 500#define TXD_GATHER_CODE_FIRST   s2BIT(22)
 501#define TXD_GATHER_CODE_LAST    s2BIT(23)
 502#define TXD_TCP_LSO_EN          s2BIT(30)
 503#define TXD_UDP_COF_EN          s2BIT(31)
 504#define TXD_UFO_EN              s2BIT(31) | s2BIT(30)
 505#define TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
 506#define TXD_UFO_MSS(val)        vBIT(val,34,14)
 507#define TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
 508
 509        u64 Control_2;
 510#define TXD_TX_CKO_CONTROL      (s2BIT(5)|s2BIT(6)|s2BIT(7))
 511#define TXD_TX_CKO_IPV4_EN      s2BIT(5)
 512#define TXD_TX_CKO_TCP_EN       s2BIT(6)
 513#define TXD_TX_CKO_UDP_EN       s2BIT(7)
 514#define TXD_VLAN_ENABLE         s2BIT(15)
 515#define TXD_VLAN_TAG(val)       vBIT(val,16,16)
 516#define TXD_INT_NUMBER(val)     vBIT(val,34,6)
 517#define TXD_INT_TYPE_PER_LIST   s2BIT(47)
 518#define TXD_INT_TYPE_UTILZ      s2BIT(46)
 519#define TXD_SET_MARKER         vBIT(0x6,0,4)
 520
 521        u64 Buffer_Pointer;
 522        u64 Host_Control;       /* reserved for host */
 523};
 524
 525/* Structure to hold the phy and virt addr of every TxDL. */
 526struct list_info_hold {
 527        dma_addr_t list_phy_addr;
 528        void *list_virt_addr;
 529};
 530
 531/* Rx descriptor structure for 1 buffer mode */
 532struct RxD_t {
 533        u64 Host_Control;       /* reserved for host */
 534        u64 Control_1;
 535#define RXD_OWN_XENA            s2BIT(7)
 536#define RXD_T_CODE              (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
 537#define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)
 538#define RXD_FRAME_VLAN_TAG      s2BIT(24)
 539#define RXD_FRAME_PROTO_IPV4    s2BIT(27)
 540#define RXD_FRAME_PROTO_IPV6    s2BIT(28)
 541#define RXD_FRAME_IP_FRAG       s2BIT(29)
 542#define RXD_FRAME_PROTO_TCP     s2BIT(30)
 543#define RXD_FRAME_PROTO_UDP     s2BIT(31)
 544#define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
 545#define RXD_GET_L3_CKSUM(val)   ((u16)(val>> 16) & 0xFFFF)
 546#define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)
 547
 548        u64 Control_2;
 549#define THE_RXD_MARK            0x3
 550#define SET_RXD_MARKER          vBIT(THE_RXD_MARK, 0, 2)
 551#define GET_RXD_MARKER(ctrl)    ((ctrl & SET_RXD_MARKER) >> 62)
 552
 553#define MASK_VLAN_TAG           vBIT(0xFFFF,48,16)
 554#define SET_VLAN_TAG(val)       vBIT(val,48,16)
 555#define SET_NUM_TAG(val)       vBIT(val,16,32)
 556
 557
 558};
 559/* Rx descriptor structure for 1 buffer mode */
 560struct RxD1 {
 561        struct RxD_t h;
 562
 563#define MASK_BUFFER0_SIZE_1       vBIT(0x3FFF,2,14)
 564#define SET_BUFFER0_SIZE_1(val)   vBIT(val,2,14)
 565#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
 566        (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
 567        u64 Buffer0_ptr;
 568};
 569/* Rx descriptor structure for 3 or 2 buffer mode */
 570
 571struct RxD3 {
 572        struct RxD_t h;
 573
 574#define MASK_BUFFER0_SIZE_3       vBIT(0xFF,2,14)
 575#define MASK_BUFFER1_SIZE_3       vBIT(0xFFFF,16,16)
 576#define MASK_BUFFER2_SIZE_3       vBIT(0xFFFF,32,16)
 577#define SET_BUFFER0_SIZE_3(val)   vBIT(val,8,8)
 578#define SET_BUFFER1_SIZE_3(val)   vBIT(val,16,16)
 579#define SET_BUFFER2_SIZE_3(val)   vBIT(val,32,16)
 580#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
 581        (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
 582#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
 583        (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
 584#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
 585        (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
 586#define BUF0_LEN        40
 587#define BUF1_LEN        1
 588
 589        u64 Buffer0_ptr;
 590        u64 Buffer1_ptr;
 591        u64 Buffer2_ptr;
 592};
 593
 594
 595/* Structure that represents the Rx descriptor block which contains
 596 * 128 Rx descriptors.
 597 */
 598struct RxD_block {
 599#define MAX_RXDS_PER_BLOCK_1            127
 600        struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
 601
 602        u64 reserved_0;
 603#define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
 604        u64 reserved_1;         /* 0xFEFFFFFFFFFFFFFF to mark last
 605                                 * Rxd in this blk */
 606        u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
 607        u64 pNext_RxD_Blk_physical;     /* Buff0_ptr.In a 32 bit arch
 608                                         * the upper 32 bits should
 609                                         * be 0 */
 610};
 611
 612#define SIZE_OF_BLOCK   4096
 613
 614#define RXD_MODE_1      0 /* One Buffer mode */
 615#define RXD_MODE_3B     1 /* Two Buffer mode */
 616
 617/* Structure to hold virtual addresses of Buf0 and Buf1 in
 618 * 2buf mode. */
 619struct buffAdd {
 620        void *ba_0_org;
 621        void *ba_1_org;
 622        void *ba_0;
 623        void *ba_1;
 624};
 625
 626/* Structure which stores all the MAC control parameters */
 627
 628/* This structure stores the offset of the RxD in the ring
 629 * from which the Rx Interrupt processor can start picking
 630 * up the RxDs for processing.
 631 */
 632struct rx_curr_get_info {
 633        u32 block_index;
 634        u32 offset;
 635        u32 ring_len;
 636};
 637
 638struct rx_curr_put_info {
 639        u32 block_index;
 640        u32 offset;
 641        u32 ring_len;
 642};
 643
 644/* This structure stores the offset of the TxDl in the FIFO
 645 * from which the Tx Interrupt processor can start picking
 646 * up the TxDLs for send complete interrupt processing.
 647 */
 648struct tx_curr_get_info {
 649        u32 offset;
 650        u32 fifo_len;
 651};
 652
 653struct tx_curr_put_info {
 654        u32 offset;
 655        u32 fifo_len;
 656};
 657
 658struct rxd_info {
 659        void *virt_addr;
 660        dma_addr_t dma_addr;
 661};
 662
 663/* Structure that holds the Phy and virt addresses of the Blocks */
 664struct rx_block_info {
 665        void *block_virt_addr;
 666        dma_addr_t block_dma_addr;
 667        struct rxd_info *rxds;
 668};
 669
 670/* Data structure to represent a LRO session */
 671struct lro {
 672        struct sk_buff  *parent;
 673        struct sk_buff  *last_frag;
 674        u8              *l2h;
 675        struct iphdr    *iph;
 676        struct tcphdr   *tcph;
 677        u32             tcp_next_seq;
 678        __be32          tcp_ack;
 679        int             total_len;
 680        int             frags_len;
 681        int             sg_num;
 682        int             in_use;
 683        __be16          window;
 684        u16             vlan_tag;
 685        u32             cur_tsval;
 686        __be32          cur_tsecr;
 687        u8              saw_ts;
 688} ____cacheline_aligned;
 689
 690/* Ring specific structure */
 691struct ring_info {
 692        /* The ring number */
 693        int ring_no;
 694
 695        /* per-ring buffer counter */
 696        u32 rx_bufs_left;
 697
 698#define MAX_LRO_SESSIONS       32
 699        struct lro lro0_n[MAX_LRO_SESSIONS];
 700        u8              lro;
 701
 702        /* copy of sp->rxd_mode flag */
 703        int rxd_mode;
 704
 705        /* Number of rxds per block for the rxd_mode */
 706        int rxd_count;
 707
 708        /* copy of sp pointer */
 709        struct s2io_nic *nic;
 710
 711        /* copy of sp->dev pointer */
 712        struct net_device *dev;
 713
 714        /* copy of sp->pdev pointer */
 715        struct pci_dev *pdev;
 716
 717        /* Per ring napi struct */
 718        struct napi_struct napi;
 719
 720        unsigned long interrupt_count;
 721
 722        /*
 723         *  Place holders for the virtual and physical addresses of
 724         *  all the Rx Blocks
 725         */
 726        struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
 727        int block_count;
 728        int pkt_cnt;
 729
 730        /*
 731         * Put pointer info which indictes which RxD has to be replenished
 732         * with a new buffer.
 733         */
 734        struct rx_curr_put_info rx_curr_put_info;
 735
 736        /*
 737         * Get pointer info which indictes which is the last RxD that was
 738         * processed by the driver.
 739         */
 740        struct rx_curr_get_info rx_curr_get_info;
 741
 742        /* interface MTU value */
 743        unsigned mtu;
 744
 745        /* Buffer Address store. */
 746        struct buffAdd **ba;
 747} ____cacheline_aligned;
 748
 749/* Fifo specific structure */
 750struct fifo_info {
 751        /* FIFO number */
 752        int fifo_no;
 753
 754        /* Maximum TxDs per TxDL */
 755        int max_txds;
 756
 757        /* Place holder of all the TX List's Phy and Virt addresses. */
 758        struct list_info_hold *list_info;
 759
 760        /*
 761         * Current offset within the tx FIFO where driver would write
 762         * new Tx frame
 763         */
 764        struct tx_curr_put_info tx_curr_put_info;
 765
 766        /*
 767         * Current offset within tx FIFO from where the driver would start freeing
 768         * the buffers
 769         */
 770        struct tx_curr_get_info tx_curr_get_info;
 771#define FIFO_QUEUE_START 0
 772#define FIFO_QUEUE_STOP 1
 773        int queue_state;
 774
 775        /* copy of sp->dev pointer */
 776        struct net_device *dev;
 777
 778        /* copy of multiq status */
 779        u8 multiq;
 780
 781        /* Per fifo lock */
 782        spinlock_t tx_lock;
 783
 784        /* Per fifo UFO in band structure */
 785        u64 *ufo_in_band_v;
 786
 787        struct s2io_nic *nic;
 788} ____cacheline_aligned;
 789
 790/* Information related to the Tx and Rx FIFOs and Rings of Xena
 791 * is maintained in this structure.
 792 */
 793struct mac_info {
 794/* tx side stuff */
 795        /* logical pointer of start of each Tx FIFO */
 796        struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
 797
 798        /* Fifo specific structure */
 799        struct fifo_info fifos[MAX_TX_FIFOS];
 800
 801        /* Save virtual address of TxD page with zero DMA addr(if any) */
 802        void *zerodma_virt_addr;
 803
 804/* rx side stuff */
 805        /* Ring specific structure */
 806        struct ring_info rings[MAX_RX_RINGS];
 807
 808        u16 rmac_pause_time;
 809        u16 mc_pause_threshold_q0q3;
 810        u16 mc_pause_threshold_q4q7;
 811
 812        void *stats_mem;        /* orignal pointer to allocated mem */
 813        dma_addr_t stats_mem_phy;       /* Physical address of the stat block */
 814        u32 stats_mem_sz;
 815        struct stat_block *stats_info;  /* Logical address of the stat block */
 816};
 817
 818/* Default Tunable parameters of the NIC. */
 819#define DEFAULT_FIFO_0_LEN 4096
 820#define DEFAULT_FIFO_1_7_LEN 512
 821#define SMALL_BLK_CNT   30
 822#define LARGE_BLK_CNT   100
 823
 824/*
 825 * Structure to keep track of the MSI-X vectors and the corresponding
 826 * argument registered against each vector
 827 */
 828#define MAX_REQUESTED_MSI_X     9
 829struct s2io_msix_entry
 830{
 831        u16 vector;
 832        u16 entry;
 833        void *arg;
 834
 835        u8 type;
 836#define        MSIX_ALARM_TYPE         1
 837#define        MSIX_RING_TYPE          2
 838
 839        u8 in_use;
 840#define MSIX_REGISTERED_SUCCESS 0xAA
 841};
 842
 843struct msix_info_st {
 844        u64 addr;
 845        u64 data;
 846};
 847
 848/* These flags represent the devices temporary state */
 849enum s2io_device_state_t
 850{
 851        __S2IO_STATE_LINK_TASK=0,
 852        __S2IO_STATE_CARD_UP
 853};
 854
 855/* Structure representing one instance of the NIC */
 856struct s2io_nic {
 857        int rxd_mode;
 858        /*
 859         * Count of packets to be processed in a given iteration, it will be indicated
 860         * by the quota field of the device structure when NAPI is enabled.
 861         */
 862        int pkts_to_process;
 863        struct net_device *dev;
 864        struct mac_info mac_control;
 865        struct config_param config;
 866        struct pci_dev *pdev;
 867        void __iomem *bar0;
 868        void __iomem *bar1;
 869#define MAX_MAC_SUPPORTED   16
 870#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
 871
 872        struct mac_addr def_mac_addr[256];
 873
 874        struct net_device_stats stats;
 875        int high_dma_flag;
 876        int device_enabled_once;
 877
 878        char name[60];
 879
 880        /* Timer that handles I/O errors/exceptions */
 881        struct timer_list alarm_timer;
 882
 883        /* Space to back up the PCI config space */
 884        u32 config_space[256 / sizeof(u32)];
 885
 886#define PROMISC     1
 887#define ALL_MULTI   2
 888
 889#define MAX_ADDRS_SUPPORTED 64
 890        u16 mc_addr_count;
 891
 892        u16 m_cast_flg;
 893        u16 all_multi_pos;
 894        u16 promisc_flg;
 895
 896        /*  Restart timer, used to restart NIC if the device is stuck and
 897         *  a schedule task that will set the correct Link state once the
 898         *  NIC's PHY has stabilized after a state change.
 899         */
 900        struct work_struct rst_timer_task;
 901        struct work_struct set_link_task;
 902
 903        /* Flag that can be used to turn on or turn off the Rx checksum
 904         * offload feature.
 905         */
 906        int rx_csum;
 907
 908        /* Below variables are used for fifo selection to transmit a packet */
 909        u16 fifo_selector[MAX_TX_FIFOS];
 910
 911        /* Total fifos for tcp packets */
 912        u8 total_tcp_fifos;
 913
 914        /*
 915        * Beginning index of udp for udp packets
 916        * Value will be equal to
 917        * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
 918        */
 919        u8 udp_fifo_idx;
 920
 921        u8 total_udp_fifos;
 922
 923        /*
 924         * Beginning index of fifo for all other packets
 925         * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
 926        */
 927        u8 other_fifo_idx;
 928
 929        struct napi_struct napi;
 930        /*  after blink, the adapter must be restored with original
 931         *  values.
 932         */
 933        u64 adapt_ctrl_org;
 934
 935        /* Last known link state. */
 936        u16 last_link_state;
 937#define LINK_DOWN       1
 938#define LINK_UP         2
 939
 940        int task_flag;
 941        unsigned long long start_time;
 942        int vlan_strip_flag;
 943#define MSIX_FLG                0xA5
 944        int num_entries;
 945        struct msix_entry *entries;
 946        int msi_detected;
 947        wait_queue_head_t msi_wait;
 948        struct s2io_msix_entry *s2io_entries;
 949        char desc[MAX_REQUESTED_MSI_X][25];
 950
 951        int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
 952
 953        struct msix_info_st msix_info[0x3f];
 954
 955#define XFRAME_I_DEVICE         1
 956#define XFRAME_II_DEVICE        2
 957        u8 device_type;
 958
 959        unsigned long   clubbed_frms_cnt;
 960        unsigned long   sending_both;
 961        u16             lro_max_aggr_per_sess;
 962        volatile unsigned long state;
 963        u64             general_int_mask;
 964
 965#define VPD_STRING_LEN 80
 966        u8  product_name[VPD_STRING_LEN];
 967        u8  serial_num[VPD_STRING_LEN];
 968};
 969
 970#define RESET_ERROR 1
 971#define CMD_ERROR   2
 972
 973/*  OS related system calls */
 974#ifndef readq
 975static inline u64 readq(void __iomem *addr)
 976{
 977        u64 ret = 0;
 978        ret = readl(addr + 4);
 979        ret <<= 32;
 980        ret |= readl(addr);
 981
 982        return ret;
 983}
 984#endif
 985
 986#ifndef writeq
 987static inline void writeq(u64 val, void __iomem *addr)
 988{
 989        writel((u32) (val), addr);
 990        writel((u32) (val >> 32), (addr + 4));
 991}
 992#endif
 993
 994/*
 995 * Some registers have to be written in a particular order to
 996 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
 997 * is used to perform such ordered writes. Defines UF (Upper First)
 998 * and LF (Lower First) will be used to specify the required write order.
 999 */
1000#define UF      1
1001#define LF      2
1002static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
1003{
1004        if (order == LF) {
1005                writel((u32) (val), addr);
1006                (void) readl(addr);
1007                writel((u32) (val >> 32), (addr + 4));
1008                (void) readl(addr + 4);
1009        } else {
1010                writel((u32) (val >> 32), (addr + 4));
1011                (void) readl(addr + 4);
1012                writel((u32) (val), addr);
1013                (void) readl(addr);
1014        }
1015}
1016
1017/*  Interrupt related values of Xena */
1018
1019#define ENABLE_INTRS    1
1020#define DISABLE_INTRS   2
1021
1022/*  Highest level interrupt blocks */
1023#define TX_PIC_INTR     (0x0001<<0)
1024#define TX_DMA_INTR     (0x0001<<1)
1025#define TX_MAC_INTR     (0x0001<<2)
1026#define TX_XGXS_INTR    (0x0001<<3)
1027#define TX_TRAFFIC_INTR (0x0001<<4)
1028#define RX_PIC_INTR     (0x0001<<5)
1029#define RX_DMA_INTR     (0x0001<<6)
1030#define RX_MAC_INTR     (0x0001<<7)
1031#define RX_XGXS_INTR    (0x0001<<8)
1032#define RX_TRAFFIC_INTR (0x0001<<9)
1033#define MC_INTR         (0x0001<<10)
1034#define ENA_ALL_INTRS    (   TX_PIC_INTR     | \
1035                            TX_DMA_INTR     | \
1036                            TX_MAC_INTR     | \
1037                            TX_XGXS_INTR    | \
1038                            TX_TRAFFIC_INTR | \
1039                            RX_PIC_INTR     | \
1040                            RX_DMA_INTR     | \
1041                            RX_MAC_INTR     | \
1042                            RX_XGXS_INTR    | \
1043                            RX_TRAFFIC_INTR | \
1044                            MC_INTR )
1045
1046/*  Interrupt masks for the general interrupt mask register */
1047#define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL
1048
1049#define TXPIC_INT_M         s2BIT(0)
1050#define TXDMA_INT_M         s2BIT(1)
1051#define TXMAC_INT_M         s2BIT(2)
1052#define TXXGXS_INT_M        s2BIT(3)
1053#define TXTRAFFIC_INT_M     s2BIT(8)
1054#define PIC_RX_INT_M        s2BIT(32)
1055#define RXDMA_INT_M         s2BIT(33)
1056#define RXMAC_INT_M         s2BIT(34)
1057#define MC_INT_M            s2BIT(35)
1058#define RXXGXS_INT_M        s2BIT(36)
1059#define RXTRAFFIC_INT_M     s2BIT(40)
1060
1061/*  PIC level Interrupts TODO*/
1062
1063/*  DMA level Inressupts */
1064#define TXDMA_PFC_INT_M     s2BIT(0)
1065#define TXDMA_PCC_INT_M     s2BIT(2)
1066
1067/*  PFC block interrupts */
1068#define PFC_MISC_ERR_1      s2BIT(0)    /* Interrupt to indicate FIFO full */
1069
1070/* PCC block interrupts. */
1071#define PCC_FB_ECC_ERR     vBIT(0xff, 16, 8)    /* Interrupt to indicate
1072                                                   PCC_FB_ECC Error. */
1073
1074#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1075/*
1076 * Prototype declaration.
1077 */
1078static int s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre);
1079static void s2io_rem_nic(struct pci_dev *pdev);
1080static int init_shared_mem(struct s2io_nic *sp);
1081static void free_shared_mem(struct s2io_nic *sp);
1082static int init_nic(struct s2io_nic *nic);
1083static int rx_intr_handler(struct ring_info *ring_data, int budget);
1084static void s2io_txpic_intr_handle(struct s2io_nic *sp);
1085static void tx_intr_handler(struct fifo_info *fifo_data);
1086static void s2io_handle_errors(void * dev_id);
1087
1088static void s2io_tx_watchdog(struct net_device *dev);
1089static void s2io_set_multicast(struct net_device *dev);
1090static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1091static void s2io_link(struct s2io_nic * sp, int link);
1092static void s2io_reset(struct s2io_nic * sp);
1093static int s2io_poll_msix(struct napi_struct *napi, int budget);
1094static int s2io_poll_inta(struct napi_struct *napi, int budget);
1095static void s2io_init_pci(struct s2io_nic * sp);
1096static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
1097static void s2io_alarm_handle(unsigned long data);
1098static irqreturn_t
1099s2io_msix_ring_handle(int irq, void *dev_id);
1100static irqreturn_t
1101s2io_msix_fifo_handle(int irq, void *dev_id);
1102static irqreturn_t s2io_isr(int irq, void *dev_id);
1103static int verify_xena_quiescence(struct s2io_nic *sp);
1104static const struct ethtool_ops netdev_ethtool_ops;
1105static void s2io_set_link(struct work_struct *work);
1106static int s2io_set_swapper(struct s2io_nic * sp);
1107static void s2io_card_down(struct s2io_nic *nic);
1108static int s2io_card_up(struct s2io_nic *nic);
1109static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1110                                        int bit_state);
1111static int s2io_add_isr(struct s2io_nic * sp);
1112static void s2io_rem_isr(struct s2io_nic * sp);
1113
1114static void restore_xmsi_data(struct s2io_nic *nic);
1115static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
1116static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
1117static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
1118static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
1119static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
1120static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
1121
1122static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
1123        u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
1124        struct s2io_nic *sp);
1125static void clear_lro_session(struct lro *lro);
1126static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag);
1127static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1128static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1129                           struct sk_buff *skb, u32 tcp_len);
1130static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1131
1132static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1133                                              pci_channel_state_t state);
1134static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1135static void s2io_io_resume(struct pci_dev *pdev);
1136
1137#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1138#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1139#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1140
1141#define S2IO_PARM_INT(X, def_val) \
1142        static unsigned int X = def_val;\
1143                module_param(X , uint, 0);
1144
1145#endif                          /* _S2IO_H */
1146