linux/drivers/net/irda/nsc-ircc.c
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   1/*********************************************************************
   2 *                
   3 * Filename:      nsc-ircc.c
   4 * Version:       1.0
   5 * Description:   Driver for the NSC PC'108 and PC'338 IrDA chipsets
   6 * Status:        Stable.
   7 * Author:        Dag Brattli <dagb@cs.uit.no>
   8 * Created at:    Sat Nov  7 21:43:15 1998
   9 * Modified at:   Wed Mar  1 11:29:34 2000
  10 * Modified by:   Dag Brattli <dagb@cs.uit.no>
  11 * 
  12 *     Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
  13 *     Copyright (c) 1998 Lichen Wang, <lwang@actisys.com>
  14 *     Copyright (c) 1998 Actisys Corp., www.actisys.com
  15 *     Copyright (c) 2000-2004 Jean Tourrilhes <jt@hpl.hp.com>
  16 *     All Rights Reserved
  17 *      
  18 *     This program is free software; you can redistribute it and/or 
  19 *     modify it under the terms of the GNU General Public License as 
  20 *     published by the Free Software Foundation; either version 2 of 
  21 *     the License, or (at your option) any later version.
  22 *  
  23 *     Neither Dag Brattli nor University of Tromsø admit liability nor
  24 *     provide warranty for any of this software. This material is 
  25 *     provided "AS-IS" and at no charge.
  26 *
  27 *     Notice that all functions that needs to access the chip in _any_
  28 *     way, must save BSR register on entry, and restore it on exit. 
  29 *     It is _very_ important to follow this policy!
  30 *
  31 *         __u8 bank;
  32 *     
  33 *         bank = inb(iobase+BSR);
  34 *  
  35 *         do_your_stuff_here();
  36 *
  37 *         outb(bank, iobase+BSR);
  38 *
  39 *    If you find bugs in this file, its very likely that the same bug
  40 *    will also be in w83977af_ir.c since the implementations are quite
  41 *    similar.
  42 *     
  43 ********************************************************************/
  44
  45#include <linux/module.h>
  46#include <linux/gfp.h>
  47
  48#include <linux/kernel.h>
  49#include <linux/types.h>
  50#include <linux/skbuff.h>
  51#include <linux/netdevice.h>
  52#include <linux/ioport.h>
  53#include <linux/delay.h>
  54#include <linux/init.h>
  55#include <linux/interrupt.h>
  56#include <linux/rtnetlink.h>
  57#include <linux/dma-mapping.h>
  58#include <linux/pnp.h>
  59#include <linux/platform_device.h>
  60
  61#include <asm/io.h>
  62#include <asm/dma.h>
  63#include <asm/byteorder.h>
  64
  65#include <net/irda/wrapper.h>
  66#include <net/irda/irda.h>
  67#include <net/irda/irda_device.h>
  68
  69#include "nsc-ircc.h"
  70
  71#define CHIP_IO_EXTENT 8
  72#define BROKEN_DONGLE_ID
  73
  74static char *driver_name = "nsc-ircc";
  75
  76/* Power Management */
  77#define NSC_IRCC_DRIVER_NAME                  "nsc-ircc"
  78static int nsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
  79static int nsc_ircc_resume(struct platform_device *dev);
  80
  81static struct platform_driver nsc_ircc_driver = {
  82        .suspend        = nsc_ircc_suspend,
  83        .resume         = nsc_ircc_resume,
  84        .driver         = {
  85                .name   = NSC_IRCC_DRIVER_NAME,
  86        },
  87};
  88
  89/* Module parameters */
  90static int qos_mtt_bits = 0x07;  /* 1 ms or more */
  91static int dongle_id;
  92
  93/* Use BIOS settions by default, but user may supply module parameters */
  94static unsigned int io[]  = { ~0, ~0, ~0, ~0, ~0 };
  95static unsigned int irq[] = {  0,  0,  0,  0,  0 };
  96static unsigned int dma[] = {  0,  0,  0,  0,  0 };
  97
  98static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info);
  99static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info);
 100static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info);
 101static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info);
 102static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info);
 103static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info);
 104#ifdef CONFIG_PNP
 105static int nsc_ircc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id);
 106#endif
 107
 108/* These are the known NSC chips */
 109static nsc_chip_t chips[] = {
 110/*  Name, {cfg registers}, chip id index reg, chip id expected value, revision mask */
 111        { "PC87108", { 0x150, 0x398, 0xea }, 0x05, 0x10, 0xf0, 
 112          nsc_ircc_probe_108, nsc_ircc_init_108 },
 113        { "PC87338", { 0x398, 0x15c, 0x2e }, 0x08, 0xb0, 0xf8, 
 114          nsc_ircc_probe_338, nsc_ircc_init_338 },
 115        /* Contributed by Steffen Pingel - IBM X40 */
 116        { "PC8738x", { 0x164e, 0x4e, 0x2e }, 0x20, 0xf4, 0xff,
 117          nsc_ircc_probe_39x, nsc_ircc_init_39x },
 118        /* Contributed by Jan Frey - IBM A30/A31 */
 119        { "PC8739x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xea, 0xff, 
 120          nsc_ircc_probe_39x, nsc_ircc_init_39x },
 121        /* IBM ThinkPads using PC8738x (T60/X60/Z60) */
 122        { "IBM-PC8738x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xf4, 0xff,
 123          nsc_ircc_probe_39x, nsc_ircc_init_39x },
 124        /* IBM ThinkPads using PC8394T (T43/R52/?) */
 125        { "IBM-PC8394T", { 0x2e, 0x4e, 0x0 }, 0x20, 0xf9, 0xff,
 126          nsc_ircc_probe_39x, nsc_ircc_init_39x },
 127        { NULL }
 128};
 129
 130static struct nsc_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL, NULL };
 131
 132static char *dongle_types[] = {
 133        "Differential serial interface",
 134        "Differential serial interface",
 135        "Reserved",
 136        "Reserved",
 137        "Sharp RY5HD01",
 138        "Reserved",
 139        "Single-ended serial interface",
 140        "Consumer-IR only",
 141        "HP HSDL-2300, HP HSDL-3600/HSDL-3610",
 142        "IBM31T1100 or Temic TFDS6000/TFDS6500",
 143        "Reserved",
 144        "Reserved",
 145        "HP HSDL-1100/HSDL-2100",
 146        "HP HSDL-1100/HSDL-2100",
 147        "Supports SIR Mode only",
 148        "No dongle connected",
 149};
 150
 151/* PNP probing */
 152static chipio_t pnp_info;
 153static const struct pnp_device_id nsc_ircc_pnp_table[] = {
 154        { .id = "NSC6001", .driver_data = 0 },
 155        { .id = "HWPC224", .driver_data = 0 },
 156        { .id = "IBM0071", .driver_data = NSC_FORCE_DONGLE_TYPE9 },
 157        { }
 158};
 159
 160MODULE_DEVICE_TABLE(pnp, nsc_ircc_pnp_table);
 161
 162static struct pnp_driver nsc_ircc_pnp_driver = {
 163#ifdef CONFIG_PNP
 164        .name = "nsc-ircc",
 165        .id_table = nsc_ircc_pnp_table,
 166        .probe = nsc_ircc_pnp_probe,
 167#endif
 168};
 169
 170/* Some prototypes */
 171static int  nsc_ircc_open(chipio_t *info);
 172static int  nsc_ircc_close(struct nsc_ircc_cb *self);
 173static int  nsc_ircc_setup(chipio_t *info);
 174static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self);
 175static int  nsc_ircc_dma_receive(struct nsc_ircc_cb *self); 
 176static int  nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase);
 177static netdev_tx_t  nsc_ircc_hard_xmit_sir(struct sk_buff *skb,
 178                                                 struct net_device *dev);
 179static netdev_tx_t  nsc_ircc_hard_xmit_fir(struct sk_buff *skb,
 180                                                 struct net_device *dev);
 181static int  nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
 182static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase);
 183static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 baud);
 184static int  nsc_ircc_is_receiving(struct nsc_ircc_cb *self);
 185static int  nsc_ircc_read_dongle_id (int iobase);
 186static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id);
 187
 188static int  nsc_ircc_net_open(struct net_device *dev);
 189static int  nsc_ircc_net_close(struct net_device *dev);
 190static int  nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 191
 192/* Globals */
 193static int pnp_registered;
 194static int pnp_succeeded;
 195
 196/*
 197 * Function nsc_ircc_init ()
 198 *
 199 *    Initialize chip. Just try to find out how many chips we are dealing with
 200 *    and where they are
 201 */
 202static int __init nsc_ircc_init(void)
 203{
 204        chipio_t info;
 205        nsc_chip_t *chip;
 206        int ret;
 207        int cfg_base;
 208        int cfg, id;
 209        int reg;
 210        int i = 0;
 211
 212        ret = platform_driver_register(&nsc_ircc_driver);
 213        if (ret) {
 214                net_err_ratelimited("%s, Can't register driver!\n",
 215                                    driver_name);
 216                return ret;
 217        }
 218
 219        /* Register with PnP subsystem to detect disable ports */
 220        ret = pnp_register_driver(&nsc_ircc_pnp_driver);
 221
 222        if (!ret)
 223                pnp_registered = 1;
 224
 225        ret = -ENODEV;
 226
 227        /* Probe for all the NSC chipsets we know about */
 228        for (chip = chips; chip->name ; chip++) {
 229                pr_debug("%s(), Probing for %s ...\n", __func__,
 230                         chip->name);
 231                
 232                /* Try all config registers for this chip */
 233                for (cfg = 0; cfg < ARRAY_SIZE(chip->cfg); cfg++) {
 234                        cfg_base = chip->cfg[cfg];
 235                        if (!cfg_base)
 236                                continue;
 237
 238                        /* Read index register */
 239                        reg = inb(cfg_base);
 240                        if (reg == 0xff) {
 241                                pr_debug("%s() no chip at 0x%03x\n",
 242                                         __func__, cfg_base);
 243                                continue;
 244                        }
 245                        
 246                        /* Read chip identification register */
 247                        outb(chip->cid_index, cfg_base);
 248                        id = inb(cfg_base+1);
 249                        if ((id & chip->cid_mask) == chip->cid_value) {
 250                                pr_debug("%s() Found %s chip, revision=%d\n",
 251                                         __func__, chip->name,
 252                                         id & ~chip->cid_mask);
 253
 254                                /*
 255                                 * If we found a correct PnP setting,
 256                                 * we first try it.
 257                                 */
 258                                if (pnp_succeeded) {
 259                                        memset(&info, 0, sizeof(chipio_t));
 260                                        info.cfg_base = cfg_base;
 261                                        info.fir_base = pnp_info.fir_base;
 262                                        info.dma = pnp_info.dma;
 263                                        info.irq = pnp_info.irq;
 264
 265                                        if (info.fir_base < 0x2000) {
 266                                                net_info_ratelimited("%s, chip->init\n",
 267                                                                     driver_name);
 268                                                chip->init(chip, &info);
 269                                        } else
 270                                                chip->probe(chip, &info);
 271
 272                                        if (nsc_ircc_open(&info) >= 0)
 273                                                ret = 0;
 274                                }
 275
 276                                /*
 277                                 * Opening based on PnP values failed.
 278                                 * Let's fallback to user values, or probe
 279                                 * the chip.
 280                                 */
 281                                if (ret) {
 282                                        pr_debug("%s, PnP init failed\n",
 283                                                 driver_name);
 284                                        memset(&info, 0, sizeof(chipio_t));
 285                                        info.cfg_base = cfg_base;
 286                                        info.fir_base = io[i];
 287                                        info.dma = dma[i];
 288                                        info.irq = irq[i];
 289
 290                                        /*
 291                                         * If the user supplies the base address, then
 292                                         * we init the chip, if not we probe the values
 293                                         * set by the BIOS
 294                                         */
 295                                        if (io[i] < 0x2000) {
 296                                                chip->init(chip, &info);
 297                                        } else
 298                                                chip->probe(chip, &info);
 299
 300                                        if (nsc_ircc_open(&info) >= 0)
 301                                                ret = 0;
 302                                }
 303                                i++;
 304                        } else {
 305                                pr_debug("%s(), Wrong chip id=0x%02x\n",
 306                                         __func__, id);
 307                        }
 308                } 
 309        }
 310
 311        if (ret) {
 312                platform_driver_unregister(&nsc_ircc_driver);
 313                pnp_unregister_driver(&nsc_ircc_pnp_driver);
 314                pnp_registered = 0;
 315        }
 316
 317        return ret;
 318}
 319
 320/*
 321 * Function nsc_ircc_cleanup ()
 322 *
 323 *    Close all configured chips
 324 *
 325 */
 326static void __exit nsc_ircc_cleanup(void)
 327{
 328        int i;
 329
 330        for (i = 0; i < ARRAY_SIZE(dev_self); i++) {
 331                if (dev_self[i])
 332                        nsc_ircc_close(dev_self[i]);
 333        }
 334
 335        platform_driver_unregister(&nsc_ircc_driver);
 336
 337        if (pnp_registered)
 338                pnp_unregister_driver(&nsc_ircc_pnp_driver);
 339
 340        pnp_registered = 0;
 341}
 342
 343static const struct net_device_ops nsc_ircc_sir_ops = {
 344        .ndo_open       = nsc_ircc_net_open,
 345        .ndo_stop       = nsc_ircc_net_close,
 346        .ndo_start_xmit = nsc_ircc_hard_xmit_sir,
 347        .ndo_do_ioctl   = nsc_ircc_net_ioctl,
 348};
 349
 350static const struct net_device_ops nsc_ircc_fir_ops = {
 351        .ndo_open       = nsc_ircc_net_open,
 352        .ndo_stop       = nsc_ircc_net_close,
 353        .ndo_start_xmit = nsc_ircc_hard_xmit_fir,
 354        .ndo_do_ioctl   = nsc_ircc_net_ioctl,
 355};
 356
 357/*
 358 * Function nsc_ircc_open (iobase, irq)
 359 *
 360 *    Open driver instance
 361 *
 362 */
 363static int __init nsc_ircc_open(chipio_t *info)
 364{
 365        struct net_device *dev;
 366        struct nsc_ircc_cb *self;
 367        void *ret;
 368        int err, chip_index;
 369
 370        for (chip_index = 0; chip_index < ARRAY_SIZE(dev_self); chip_index++) {
 371                if (!dev_self[chip_index])
 372                        break;
 373        }
 374
 375        if (chip_index == ARRAY_SIZE(dev_self)) {
 376                net_err_ratelimited("%s(), maximum number of supported chips reached!\n",
 377                                    __func__);
 378                return -ENOMEM;
 379        }
 380
 381        net_info_ratelimited("%s, Found chip at base=0x%03x\n",
 382                             driver_name, info->cfg_base);
 383
 384        if ((nsc_ircc_setup(info)) == -1)
 385                return -1;
 386
 387        net_info_ratelimited("%s, driver loaded (Dag Brattli)\n", driver_name);
 388
 389        dev = alloc_irdadev(sizeof(struct nsc_ircc_cb));
 390        if (dev == NULL) {
 391                net_err_ratelimited("%s(), can't allocate memory for control block!\n",
 392                                    __func__);
 393                return -ENOMEM;
 394        }
 395
 396        self = netdev_priv(dev);
 397        self->netdev = dev;
 398        spin_lock_init(&self->lock);
 399   
 400        /* Need to store self somewhere */
 401        dev_self[chip_index] = self;
 402        self->index = chip_index;
 403
 404        /* Initialize IO */
 405        self->io.cfg_base  = info->cfg_base;
 406        self->io.fir_base  = info->fir_base;
 407        self->io.irq       = info->irq;
 408        self->io.fir_ext   = CHIP_IO_EXTENT;
 409        self->io.dma       = info->dma;
 410        self->io.fifo_size = 32;
 411        
 412        /* Reserve the ioports that we need */
 413        ret = request_region(self->io.fir_base, self->io.fir_ext, driver_name);
 414        if (!ret) {
 415                net_warn_ratelimited("%s(), can't get iobase of 0x%03x\n",
 416                                     __func__, self->io.fir_base);
 417                err = -ENODEV;
 418                goto out1;
 419        }
 420
 421        /* Initialize QoS for this device */
 422        irda_init_max_qos_capabilies(&self->qos);
 423        
 424        /* The only value we must override it the baudrate */
 425        self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
 426                IR_115200|IR_576000|IR_1152000 |(IR_4000000 << 8);
 427        
 428        self->qos.min_turn_time.bits = qos_mtt_bits;
 429        irda_qos_bits_to_value(&self->qos);
 430        
 431        /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
 432        self->rx_buff.truesize = 14384; 
 433        self->tx_buff.truesize = 14384;
 434
 435        /* Allocate memory if needed */
 436        self->rx_buff.head =
 437                dma_zalloc_coherent(NULL, self->rx_buff.truesize,
 438                                    &self->rx_buff_dma, GFP_KERNEL);
 439        if (self->rx_buff.head == NULL) {
 440                err = -ENOMEM;
 441                goto out2;
 442
 443        }
 444        
 445        self->tx_buff.head =
 446                dma_zalloc_coherent(NULL, self->tx_buff.truesize,
 447                                    &self->tx_buff_dma, GFP_KERNEL);
 448        if (self->tx_buff.head == NULL) {
 449                err = -ENOMEM;
 450                goto out3;
 451        }
 452
 453        self->rx_buff.in_frame = FALSE;
 454        self->rx_buff.state = OUTSIDE_FRAME;
 455        self->tx_buff.data = self->tx_buff.head;
 456        self->rx_buff.data = self->rx_buff.head;
 457        
 458        /* Reset Tx queue info */
 459        self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
 460        self->tx_fifo.tail = self->tx_buff.head;
 461
 462        /* Override the network functions we need to use */
 463        dev->netdev_ops = &nsc_ircc_sir_ops;
 464
 465        err = register_netdev(dev);
 466        if (err) {
 467                net_err_ratelimited("%s(), register_netdev() failed!\n",
 468                                    __func__);
 469                goto out4;
 470        }
 471        net_info_ratelimited("IrDA: Registered device %s\n", dev->name);
 472
 473        /* Check if user has supplied a valid dongle id or not */
 474        if ((dongle_id <= 0) ||
 475            (dongle_id >= ARRAY_SIZE(dongle_types))) {
 476                dongle_id = nsc_ircc_read_dongle_id(self->io.fir_base);
 477                
 478                net_info_ratelimited("%s, Found dongle: %s\n",
 479                                     driver_name, dongle_types[dongle_id]);
 480        } else {
 481                net_info_ratelimited("%s, Using dongle: %s\n",
 482                                     driver_name, dongle_types[dongle_id]);
 483        }
 484        
 485        self->io.dongle_id = dongle_id;
 486        nsc_ircc_init_dongle_interface(self->io.fir_base, dongle_id);
 487
 488        self->pldev = platform_device_register_simple(NSC_IRCC_DRIVER_NAME,
 489                                                      self->index, NULL, 0);
 490        if (IS_ERR(self->pldev)) {
 491                err = PTR_ERR(self->pldev);
 492                goto out5;
 493        }
 494        platform_set_drvdata(self->pldev, self);
 495
 496        return chip_index;
 497
 498 out5:
 499        unregister_netdev(dev);
 500 out4:
 501        dma_free_coherent(NULL, self->tx_buff.truesize,
 502                          self->tx_buff.head, self->tx_buff_dma);
 503 out3:
 504        dma_free_coherent(NULL, self->rx_buff.truesize,
 505                          self->rx_buff.head, self->rx_buff_dma);
 506 out2:
 507        release_region(self->io.fir_base, self->io.fir_ext);
 508 out1:
 509        free_netdev(dev);
 510        dev_self[chip_index] = NULL;
 511        return err;
 512}
 513
 514/*
 515 * Function nsc_ircc_close (self)
 516 *
 517 *    Close driver instance
 518 *
 519 */
 520static int __exit nsc_ircc_close(struct nsc_ircc_cb *self)
 521{
 522        int iobase;
 523
 524        IRDA_ASSERT(self != NULL, return -1;);
 525
 526        iobase = self->io.fir_base;
 527
 528        platform_device_unregister(self->pldev);
 529
 530        /* Remove netdevice */
 531        unregister_netdev(self->netdev);
 532
 533        /* Release the PORT that this driver is using */
 534        pr_debug("%s(), Releasing Region %03x\n",
 535                 __func__, self->io.fir_base);
 536        release_region(self->io.fir_base, self->io.fir_ext);
 537
 538        if (self->tx_buff.head)
 539                dma_free_coherent(NULL, self->tx_buff.truesize,
 540                                  self->tx_buff.head, self->tx_buff_dma);
 541        
 542        if (self->rx_buff.head)
 543                dma_free_coherent(NULL, self->rx_buff.truesize,
 544                                  self->rx_buff.head, self->rx_buff_dma);
 545
 546        dev_self[self->index] = NULL;
 547        free_netdev(self->netdev);
 548        
 549        return 0;
 550}
 551
 552/*
 553 * Function nsc_ircc_init_108 (iobase, cfg_base, irq, dma)
 554 *
 555 *    Initialize the NSC '108 chip
 556 *
 557 */
 558static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info)
 559{
 560        int cfg_base = info->cfg_base;
 561        __u8 temp=0;
 562
 563        outb(2, cfg_base);      /* Mode Control Register (MCTL) */
 564        outb(0x00, cfg_base+1); /* Disable device */
 565        
 566        /* Base Address and Interrupt Control Register (BAIC) */
 567        outb(CFG_108_BAIC, cfg_base);
 568        switch (info->fir_base) {
 569        case 0x3e8: outb(0x14, cfg_base+1); break;
 570        case 0x2e8: outb(0x15, cfg_base+1); break;
 571        case 0x3f8: outb(0x16, cfg_base+1); break;
 572        case 0x2f8: outb(0x17, cfg_base+1); break;
 573        default: net_err_ratelimited("%s(), invalid base_address\n", __func__);
 574        }
 575        
 576        /* Control Signal Routing Register (CSRT) */
 577        switch (info->irq) {
 578        case 3:  temp = 0x01; break;
 579        case 4:  temp = 0x02; break;
 580        case 5:  temp = 0x03; break;
 581        case 7:  temp = 0x04; break;
 582        case 9:  temp = 0x05; break;
 583        case 11: temp = 0x06; break;
 584        case 15: temp = 0x07; break;
 585        default: net_err_ratelimited("%s(), invalid irq\n", __func__);
 586        }
 587        outb(CFG_108_CSRT, cfg_base);
 588        
 589        switch (info->dma) {    
 590        case 0: outb(0x08+temp, cfg_base+1); break;
 591        case 1: outb(0x10+temp, cfg_base+1); break;
 592        case 3: outb(0x18+temp, cfg_base+1); break;
 593        default: net_err_ratelimited("%s(), invalid dma\n", __func__);
 594        }
 595        
 596        outb(CFG_108_MCTL, cfg_base);      /* Mode Control Register (MCTL) */
 597        outb(0x03, cfg_base+1); /* Enable device */
 598
 599        return 0;
 600}
 601
 602/*
 603 * Function nsc_ircc_probe_108 (chip, info)
 604 *
 605 *    
 606 *
 607 */
 608static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info) 
 609{
 610        int cfg_base = info->cfg_base;
 611        int reg;
 612
 613        /* Read address and interrupt control register (BAIC) */
 614        outb(CFG_108_BAIC, cfg_base);
 615        reg = inb(cfg_base+1);
 616        
 617        switch (reg & 0x03) {
 618        case 0:
 619                info->fir_base = 0x3e8;
 620                break;
 621        case 1:
 622                info->fir_base = 0x2e8;
 623                break;
 624        case 2:
 625                info->fir_base = 0x3f8;
 626                break;
 627        case 3:
 628                info->fir_base = 0x2f8;
 629                break;
 630        }
 631        info->sir_base = info->fir_base;
 632        pr_debug("%s(), probing fir_base=0x%03x\n", __func__,
 633                 info->fir_base);
 634
 635        /* Read control signals routing register (CSRT) */
 636        outb(CFG_108_CSRT, cfg_base);
 637        reg = inb(cfg_base+1);
 638
 639        switch (reg & 0x07) {
 640        case 0:
 641                info->irq = -1;
 642                break;
 643        case 1:
 644                info->irq = 3;
 645                break;
 646        case 2:
 647                info->irq = 4;
 648                break;
 649        case 3:
 650                info->irq = 5;
 651                break;
 652        case 4:
 653                info->irq = 7;
 654                break;
 655        case 5:
 656                info->irq = 9;
 657                break;
 658        case 6:
 659                info->irq = 11;
 660                break;
 661        case 7:
 662                info->irq = 15;
 663                break;
 664        }
 665        pr_debug("%s(), probing irq=%d\n", __func__, info->irq);
 666
 667        /* Currently we only read Rx DMA but it will also be used for Tx */
 668        switch ((reg >> 3) & 0x03) {
 669        case 0:
 670                info->dma = -1;
 671                break;
 672        case 1:
 673                info->dma = 0;
 674                break;
 675        case 2:
 676                info->dma = 1;
 677                break;
 678        case 3:
 679                info->dma = 3;
 680                break;
 681        }
 682        pr_debug("%s(), probing dma=%d\n", __func__, info->dma);
 683
 684        /* Read mode control register (MCTL) */
 685        outb(CFG_108_MCTL, cfg_base);
 686        reg = inb(cfg_base+1);
 687
 688        info->enabled = reg & 0x01;
 689        info->suspended = !((reg >> 1) & 0x01);
 690
 691        return 0;
 692}
 693
 694/*
 695 * Function nsc_ircc_init_338 (chip, info)
 696 *
 697 *    Initialize the NSC '338 chip. Remember that the 87338 needs two 
 698 *    consecutive writes to the data registers while CPU interrupts are
 699 *    disabled. The 97338 does not require this, but shouldn't be any
 700 *    harm if we do it anyway.
 701 */
 702static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info) 
 703{
 704        /* No init yet */
 705        
 706        return 0;
 707}
 708
 709/*
 710 * Function nsc_ircc_probe_338 (chip, info)
 711 *
 712 *    
 713 *
 714 */
 715static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info) 
 716{
 717        int cfg_base = info->cfg_base;
 718        int reg, com = 0;
 719        int pnp;
 720
 721        /* Read function enable register (FER) */
 722        outb(CFG_338_FER, cfg_base);
 723        reg = inb(cfg_base+1);
 724
 725        info->enabled = (reg >> 2) & 0x01;
 726
 727        /* Check if we are in Legacy or PnP mode */
 728        outb(CFG_338_PNP0, cfg_base);
 729        reg = inb(cfg_base+1);
 730        
 731        pnp = (reg >> 3) & 0x01;
 732        if (pnp) {
 733                pr_debug("(), Chip is in PnP mode\n");
 734                outb(0x46, cfg_base);
 735                reg = (inb(cfg_base+1) & 0xfe) << 2;
 736
 737                outb(0x47, cfg_base);
 738                reg |= ((inb(cfg_base+1) & 0xfc) << 8);
 739
 740                info->fir_base = reg;
 741        } else {
 742                /* Read function address register (FAR) */
 743                outb(CFG_338_FAR, cfg_base);
 744                reg = inb(cfg_base+1);
 745                
 746                switch ((reg >> 4) & 0x03) {
 747                case 0:
 748                        info->fir_base = 0x3f8;
 749                        break;
 750                case 1:
 751                        info->fir_base = 0x2f8;
 752                        break;
 753                case 2:
 754                        com = 3;
 755                        break;
 756                case 3:
 757                        com = 4;
 758                        break;
 759                }
 760                
 761                if (com) {
 762                        switch ((reg >> 6) & 0x03) {
 763                        case 0:
 764                                if (com == 3)
 765                                        info->fir_base = 0x3e8;
 766                                else
 767                                        info->fir_base = 0x2e8;
 768                                break;
 769                        case 1:
 770                                if (com == 3)
 771                                        info->fir_base = 0x338;
 772                                else
 773                                        info->fir_base = 0x238;
 774                                break;
 775                        case 2:
 776                                if (com == 3)
 777                                        info->fir_base = 0x2e8;
 778                                else
 779                                        info->fir_base = 0x2e0;
 780                                break;
 781                        case 3:
 782                                if (com == 3)
 783                                        info->fir_base = 0x220;
 784                                else
 785                                        info->fir_base = 0x228;
 786                                break;
 787                        }
 788                }
 789        }
 790        info->sir_base = info->fir_base;
 791
 792        /* Read PnP register 1 (PNP1) */
 793        outb(CFG_338_PNP1, cfg_base);
 794        reg = inb(cfg_base+1);
 795        
 796        info->irq = reg >> 4;
 797        
 798        /* Read PnP register 3 (PNP3) */
 799        outb(CFG_338_PNP3, cfg_base);
 800        reg = inb(cfg_base+1);
 801
 802        info->dma = (reg & 0x07) - 1;
 803
 804        /* Read power and test register (PTR) */
 805        outb(CFG_338_PTR, cfg_base);
 806        reg = inb(cfg_base+1);
 807
 808        info->suspended = reg & 0x01;
 809
 810        return 0;
 811}
 812
 813
 814/*
 815 * Function nsc_ircc_init_39x (chip, info)
 816 *
 817 *    Now that we know it's a '39x (see probe below), we need to
 818 *    configure it so we can use it.
 819 *
 820 * The NSC '338 chip is a Super I/O chip with a "bank" architecture,
 821 * the configuration of the different functionality (serial, parallel,
 822 * floppy...) are each in a different bank (Logical Device Number).
 823 * The base address, irq and dma configuration registers are common
 824 * to all functionalities (index 0x30 to 0x7F).
 825 * There is only one configuration register specific to the
 826 * serial port, CFG_39X_SPC.
 827 * JeanII
 828 *
 829 * Note : this code was written by Jan Frey <janfrey@web.de>
 830 */
 831static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info) 
 832{
 833        int cfg_base = info->cfg_base;
 834        int enabled;
 835
 836        /* User is sure about his config... accept it. */
 837        pr_debug("%s(): nsc_ircc_init_39x (user settings): io=0x%04x, irq=%d, dma=%d\n",
 838                 __func__, info->fir_base, info->irq, info->dma);
 839
 840        /* Access bank for SP2 */
 841        outb(CFG_39X_LDN, cfg_base);
 842        outb(0x02, cfg_base+1);
 843
 844        /* Configure SP2 */
 845
 846        /* We want to enable the device if not enabled */
 847        outb(CFG_39X_ACT, cfg_base);
 848        enabled = inb(cfg_base+1) & 0x01;
 849        
 850        if (!enabled) {
 851                /* Enable the device */
 852                outb(CFG_39X_SIOCF1, cfg_base);
 853                outb(0x01, cfg_base+1);
 854                /* May want to update info->enabled. Jean II */
 855        }
 856
 857        /* Enable UART bank switching (bit 7) ; Sets the chip to normal
 858         * power mode (wake up from sleep mode) (bit 1) */
 859        outb(CFG_39X_SPC, cfg_base);
 860        outb(0x82, cfg_base+1);
 861
 862        return 0;
 863}
 864
 865/*
 866 * Function nsc_ircc_probe_39x (chip, info)
 867 *
 868 *    Test if we really have a '39x chip at the given address
 869 *
 870 * Note : this code was written by Jan Frey <janfrey@web.de>
 871 */
 872static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info) 
 873{
 874        int cfg_base = info->cfg_base;
 875        int reg1, reg2, irq, irqt, dma1, dma2;
 876        int enabled, susp;
 877
 878        pr_debug("%s(), nsc_ircc_probe_39x, base=%d\n",
 879                 __func__, cfg_base);
 880
 881        /* This function should be executed with irq off to avoid
 882         * another driver messing with the Super I/O bank - Jean II */
 883
 884        /* Access bank for SP2 */
 885        outb(CFG_39X_LDN, cfg_base);
 886        outb(0x02, cfg_base+1);
 887
 888        /* Read infos about SP2 ; store in info struct */
 889        outb(CFG_39X_BASEH, cfg_base);
 890        reg1 = inb(cfg_base+1);
 891        outb(CFG_39X_BASEL, cfg_base);
 892        reg2 = inb(cfg_base+1);
 893        info->fir_base = (reg1 << 8) | reg2;
 894
 895        outb(CFG_39X_IRQNUM, cfg_base);
 896        irq = inb(cfg_base+1);
 897        outb(CFG_39X_IRQSEL, cfg_base);
 898        irqt = inb(cfg_base+1);
 899        info->irq = irq;
 900
 901        outb(CFG_39X_DMA0, cfg_base);
 902        dma1 = inb(cfg_base+1);
 903        outb(CFG_39X_DMA1, cfg_base);
 904        dma2 = inb(cfg_base+1);
 905        info->dma = dma1 -1;
 906
 907        outb(CFG_39X_ACT, cfg_base);
 908        info->enabled = enabled = inb(cfg_base+1) & 0x01;
 909        
 910        outb(CFG_39X_SPC, cfg_base);
 911        susp = 1 - ((inb(cfg_base+1) & 0x02) >> 1);
 912
 913        pr_debug("%s(): io=0x%02x%02x, irq=%d (type %d), rxdma=%d, txdma=%d, enabled=%d (suspended=%d)\n",
 914                 __func__, reg1, reg2, irq, irqt, dma1, dma2, enabled, susp);
 915
 916        /* Configure SP2 */
 917
 918        /* We want to enable the device if not enabled */
 919        outb(CFG_39X_ACT, cfg_base);
 920        enabled = inb(cfg_base+1) & 0x01;
 921        
 922        if (!enabled) {
 923                /* Enable the device */
 924                outb(CFG_39X_SIOCF1, cfg_base);
 925                outb(0x01, cfg_base+1);
 926                /* May want to update info->enabled. Jean II */
 927        }
 928
 929        /* Enable UART bank switching (bit 7) ; Sets the chip to normal
 930         * power mode (wake up from sleep mode) (bit 1) */
 931        outb(CFG_39X_SPC, cfg_base);
 932        outb(0x82, cfg_base+1);
 933
 934        return 0;
 935}
 936
 937#ifdef CONFIG_PNP
 938/* PNP probing */
 939static int nsc_ircc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id)
 940{
 941        memset(&pnp_info, 0, sizeof(chipio_t));
 942        pnp_info.irq = -1;
 943        pnp_info.dma = -1;
 944        pnp_succeeded = 1;
 945
 946        if (id->driver_data & NSC_FORCE_DONGLE_TYPE9)
 947                dongle_id = 0x9;
 948
 949        /* There doesn't seem to be any way of getting the cfg_base.
 950         * On my box, cfg_base is in the PnP descriptor of the
 951         * motherboard. Oh well... Jean II */
 952
 953        if (pnp_port_valid(dev, 0) &&
 954                !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED))
 955                pnp_info.fir_base = pnp_port_start(dev, 0);
 956
 957        if (pnp_irq_valid(dev, 0) &&
 958                !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED))
 959                pnp_info.irq = pnp_irq(dev, 0);
 960
 961        if (pnp_dma_valid(dev, 0) &&
 962                !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED))
 963                pnp_info.dma = pnp_dma(dev, 0);
 964
 965        pr_debug("%s() : From PnP, found firbase 0x%03X ; irq %d ; dma %d.\n",
 966                 __func__, pnp_info.fir_base, pnp_info.irq, pnp_info.dma);
 967
 968        if((pnp_info.fir_base == 0) ||
 969           (pnp_info.irq == -1) || (pnp_info.dma == -1)) {
 970                /* Returning an error will disable the device. Yuck ! */
 971                //return -EINVAL;
 972                pnp_succeeded = 0;
 973        }
 974
 975        return 0;
 976}
 977#endif
 978
 979/*
 980 * Function nsc_ircc_setup (info)
 981 *
 982 *    Returns non-negative on success.
 983 *
 984 */
 985static int nsc_ircc_setup(chipio_t *info)
 986{
 987        int version;
 988        int iobase = info->fir_base;
 989
 990        /* Read the Module ID */
 991        switch_bank(iobase, BANK3);
 992        version = inb(iobase+MID);
 993
 994        pr_debug("%s() Driver %s Found chip version %02x\n",
 995                 __func__, driver_name, version);
 996
 997        /* Should be 0x2? */
 998        if (0x20 != (version & 0xf0)) {
 999                net_err_ratelimited("%s, Wrong chip version %02x\n",
1000                                    driver_name, version);
1001                return -1;
1002        }
1003
1004        /* Switch to advanced mode */
1005        switch_bank(iobase, BANK2);
1006        outb(ECR1_EXT_SL, iobase+ECR1);
1007        switch_bank(iobase, BANK0);
1008        
1009        /* Set FIFO threshold to TX17, RX16, reset and enable FIFO's */
1010        switch_bank(iobase, BANK0);
1011        outb(FCR_RXTH|FCR_TXTH|FCR_TXSR|FCR_RXSR|FCR_FIFO_EN, iobase+FCR);
1012
1013        outb(0x03, iobase+LCR);         /* 8 bit word length */
1014        outb(MCR_SIR, iobase+MCR);      /* Start at SIR-mode, also clears LSR*/
1015
1016        /* Set FIFO size to 32 */
1017        switch_bank(iobase, BANK2);
1018        outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2);
1019
1020        /* IRCR2: FEND_MD is not set */
1021        switch_bank(iobase, BANK5);
1022        outb(0x02, iobase+4);
1023
1024        /* Make sure that some defaults are OK */
1025        switch_bank(iobase, BANK6);
1026        outb(0x20, iobase+0); /* Set 32 bits FIR CRC */
1027        outb(0x0a, iobase+1); /* Set MIR pulse width */
1028        outb(0x0d, iobase+2); /* Set SIR pulse width to 1.6us */
1029        outb(0x2a, iobase+4); /* Set beginning frag, and preamble length */
1030
1031        /* Enable receive interrupts */
1032        switch_bank(iobase, BANK0);
1033        outb(IER_RXHDL_IE, iobase+IER);
1034
1035        return 0;
1036}
1037
1038/*
1039 * Function nsc_ircc_read_dongle_id (void)
1040 *
1041 * Try to read dongle identification. This procedure needs to be executed
1042 * once after power-on/reset. It also needs to be used whenever you suspect
1043 * that the user may have plugged/unplugged the IrDA Dongle.
1044 */
1045static int nsc_ircc_read_dongle_id (int iobase)
1046{
1047        int dongle_id;
1048        __u8 bank;
1049
1050        bank = inb(iobase+BSR);
1051
1052        /* Select Bank 7 */
1053        switch_bank(iobase, BANK7);
1054        
1055        /* IRCFG4: IRSL0_DS and IRSL21_DS are cleared */
1056        outb(0x00, iobase+7);
1057        
1058        /* ID0, 1, and 2 are pulled up/down very slowly */
1059        udelay(50);
1060        
1061        /* IRCFG1: read the ID bits */
1062        dongle_id = inb(iobase+4) & 0x0f;
1063
1064#ifdef BROKEN_DONGLE_ID
1065        if (dongle_id == 0x0a)
1066                dongle_id = 0x09;
1067#endif  
1068        /* Go back to  bank 0 before returning */
1069        switch_bank(iobase, BANK0);
1070
1071        outb(bank, iobase+BSR);
1072
1073        return dongle_id;
1074}
1075
1076/*
1077 * Function nsc_ircc_init_dongle_interface (iobase, dongle_id)
1078 *
1079 *     This function initializes the dongle for the transceiver that is
1080 *     used. This procedure needs to be executed once after
1081 *     power-on/reset. It also needs to be used whenever you suspect that
1082 *     the dongle is changed. 
1083 */
1084static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id)
1085{
1086        int bank;
1087
1088        /* Save current bank */
1089        bank = inb(iobase+BSR);
1090
1091        /* Select Bank 7 */
1092        switch_bank(iobase, BANK7);
1093        
1094        /* IRCFG4: set according to dongle_id */
1095        switch (dongle_id) {
1096        case 0x00: /* same as */
1097        case 0x01: /* Differential serial interface */
1098                pr_debug("%s(), %s not defined by irda yet\n",
1099                         __func__, dongle_types[dongle_id]);
1100                break;
1101        case 0x02: /* same as */
1102        case 0x03: /* Reserved */
1103                pr_debug("%s(), %s not defined by irda yet\n",
1104                         __func__, dongle_types[dongle_id]);
1105                break;
1106        case 0x04: /* Sharp RY5HD01 */
1107                break;
1108        case 0x05: /* Reserved, but this is what the Thinkpad reports */
1109                pr_debug("%s(), %s not defined by irda yet\n",
1110                         __func__, dongle_types[dongle_id]);
1111                break;
1112        case 0x06: /* Single-ended serial interface */
1113                pr_debug("%s(), %s not defined by irda yet\n",
1114                         __func__, dongle_types[dongle_id]);
1115                break;
1116        case 0x07: /* Consumer-IR only */
1117                pr_debug("%s(), %s is not for IrDA mode\n",
1118                         __func__, dongle_types[dongle_id]);
1119                break;
1120        case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
1121                pr_debug("%s(), %s\n",
1122                         __func__, dongle_types[dongle_id]);
1123                break;
1124        case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
1125                outb(0x28, iobase+7); /* Set irsl[0-2] as output */
1126                break;
1127        case 0x0A: /* same as */
1128        case 0x0B: /* Reserved */
1129                pr_debug("%s(), %s not defined by irda yet\n",
1130                         __func__, dongle_types[dongle_id]);
1131                break;
1132        case 0x0C: /* same as */
1133        case 0x0D: /* HP HSDL-1100/HSDL-2100 */
1134                /* 
1135                 * Set irsl0 as input, irsl[1-2] as output, and separate 
1136                 * inputs are used for SIR and MIR/FIR 
1137                 */
1138                outb(0x48, iobase+7); 
1139                break;
1140        case 0x0E: /* Supports SIR Mode only */
1141                outb(0x28, iobase+7); /* Set irsl[0-2] as output */
1142                break;
1143        case 0x0F: /* No dongle connected */
1144                pr_debug("%s(), %s\n",
1145                         __func__, dongle_types[dongle_id]);
1146
1147                switch_bank(iobase, BANK0);
1148                outb(0x62, iobase+MCR);
1149                break;
1150        default: 
1151                pr_debug("%s(), invalid dongle_id %#x",
1152                         __func__, dongle_id);
1153        }
1154        
1155        /* IRCFG1: IRSL1 and 2 are set to IrDA mode */
1156        outb(0x00, iobase+4);
1157
1158        /* Restore bank register */
1159        outb(bank, iobase+BSR);
1160        
1161} /* set_up_dongle_interface */
1162
1163/*
1164 * Function nsc_ircc_change_dongle_speed (iobase, speed, dongle_id)
1165 *
1166 *    Change speed of the attach dongle
1167 *
1168 */
1169static void nsc_ircc_change_dongle_speed(int iobase, int speed, int dongle_id)
1170{
1171        __u8 bank;
1172
1173        /* Save current bank */
1174        bank = inb(iobase+BSR);
1175
1176        /* Select Bank 7 */
1177        switch_bank(iobase, BANK7);
1178        
1179        /* IRCFG1: set according to dongle_id */
1180        switch (dongle_id) {
1181        case 0x00: /* same as */
1182        case 0x01: /* Differential serial interface */
1183                pr_debug("%s(), %s not defined by irda yet\n",
1184                         __func__, dongle_types[dongle_id]);
1185                break;
1186        case 0x02: /* same as */
1187        case 0x03: /* Reserved */
1188                pr_debug("%s(), %s not defined by irda yet\n",
1189                         __func__, dongle_types[dongle_id]);
1190                break;
1191        case 0x04: /* Sharp RY5HD01 */
1192                break;
1193        case 0x05: /* Reserved */
1194                pr_debug("%s(), %s not defined by irda yet\n",
1195                         __func__, dongle_types[dongle_id]);
1196                break;
1197        case 0x06: /* Single-ended serial interface */
1198                pr_debug("%s(), %s not defined by irda yet\n",
1199                         __func__, dongle_types[dongle_id]);
1200                break;
1201        case 0x07: /* Consumer-IR only */
1202                pr_debug("%s(), %s is not for IrDA mode\n",
1203                         __func__, dongle_types[dongle_id]);
1204                break;
1205        case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
1206                pr_debug("%s(), %s\n",
1207                         __func__, dongle_types[dongle_id]);
1208                outb(0x00, iobase+4);
1209                if (speed > 115200)
1210                        outb(0x01, iobase+4);
1211                break;
1212        case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
1213                outb(0x01, iobase+4);
1214
1215                if (speed == 4000000) {
1216                        /* There was a cli() there, but we now are already
1217                         * under spin_lock_irqsave() - JeanII */
1218                        outb(0x81, iobase+4);
1219                        outb(0x80, iobase+4);
1220                } else
1221                        outb(0x00, iobase+4);
1222                break;
1223        case 0x0A: /* same as */
1224        case 0x0B: /* Reserved */
1225                pr_debug("%s(), %s not defined by irda yet\n",
1226                         __func__, dongle_types[dongle_id]);
1227                break;
1228        case 0x0C: /* same as */
1229        case 0x0D: /* HP HSDL-1100/HSDL-2100 */
1230                break;
1231        case 0x0E: /* Supports SIR Mode only */
1232                break;
1233        case 0x0F: /* No dongle connected */
1234                pr_debug("%s(), %s is not for IrDA mode\n",
1235                         __func__, dongle_types[dongle_id]);
1236
1237                switch_bank(iobase, BANK0); 
1238                outb(0x62, iobase+MCR);
1239                break;
1240        default: 
1241                pr_debug("%s(), invalid data_rate\n", __func__);
1242        }
1243        /* Restore bank register */
1244        outb(bank, iobase+BSR);
1245}
1246
1247/*
1248 * Function nsc_ircc_change_speed (self, baud)
1249 *
1250 *    Change the speed of the device
1251 *
1252 * This function *must* be called with irq off and spin-lock.
1253 */
1254static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 speed)
1255{
1256        struct net_device *dev;
1257        __u8 mcr = MCR_SIR;
1258        int iobase; 
1259        __u8 bank;
1260        __u8 ier;                  /* Interrupt enable register */
1261
1262        pr_debug("%s(), speed=%d\n", __func__, speed);
1263
1264        IRDA_ASSERT(self != NULL, return 0;);
1265
1266        dev = self->netdev;
1267        iobase = self->io.fir_base;
1268
1269        /* Update accounting for new speed */
1270        self->io.speed = speed;
1271
1272        /* Save current bank */
1273        bank = inb(iobase+BSR);
1274
1275        /* Disable interrupts */
1276        switch_bank(iobase, BANK0);
1277        outb(0, iobase+IER);
1278
1279        /* Select Bank 2 */
1280        switch_bank(iobase, BANK2);
1281
1282        outb(0x00, iobase+BGDH);
1283        switch (speed) {
1284        case 9600:   outb(0x0c, iobase+BGDL); break;
1285        case 19200:  outb(0x06, iobase+BGDL); break;
1286        case 38400:  outb(0x03, iobase+BGDL); break;
1287        case 57600:  outb(0x02, iobase+BGDL); break;
1288        case 115200: outb(0x01, iobase+BGDL); break;
1289        case 576000:
1290                switch_bank(iobase, BANK5);
1291                
1292                /* IRCR2: MDRS is set */
1293                outb(inb(iobase+4) | 0x04, iobase+4);
1294               
1295                mcr = MCR_MIR;
1296                pr_debug("%s(), handling baud of 576000\n", __func__);
1297                break;
1298        case 1152000:
1299                mcr = MCR_MIR;
1300                pr_debug("%s(), handling baud of 1152000\n", __func__);
1301                break;
1302        case 4000000:
1303                mcr = MCR_FIR;
1304                pr_debug("%s(), handling baud of 4000000\n", __func__);
1305                break;
1306        default:
1307                mcr = MCR_FIR;
1308                pr_debug("%s(), unknown baud rate of %d\n",
1309                         __func__, speed);
1310                break;
1311        }
1312
1313        /* Set appropriate speed mode */
1314        switch_bank(iobase, BANK0);
1315        outb(mcr | MCR_TX_DFR, iobase+MCR);
1316
1317        /* Give some hits to the transceiver */
1318        nsc_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
1319
1320        /* Set FIFO threshold to TX17, RX16 */
1321        switch_bank(iobase, BANK0);
1322        outb(0x00, iobase+FCR);
1323        outb(FCR_FIFO_EN, iobase+FCR);
1324        outb(FCR_RXTH|     /* Set Rx FIFO threshold */
1325             FCR_TXTH|     /* Set Tx FIFO threshold */
1326             FCR_TXSR|     /* Reset Tx FIFO */
1327             FCR_RXSR|     /* Reset Rx FIFO */
1328             FCR_FIFO_EN,  /* Enable FIFOs */
1329             iobase+FCR);
1330        
1331        /* Set FIFO size to 32 */
1332        switch_bank(iobase, BANK2);
1333        outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2);
1334        
1335        /* Enable some interrupts so we can receive frames */
1336        switch_bank(iobase, BANK0); 
1337        if (speed > 115200) {
1338                /* Install FIR xmit handler */
1339                dev->netdev_ops = &nsc_ircc_fir_ops;
1340                ier = IER_SFIF_IE;
1341                nsc_ircc_dma_receive(self);
1342        } else {
1343                /* Install SIR xmit handler */
1344                dev->netdev_ops = &nsc_ircc_sir_ops;
1345                ier = IER_RXHDL_IE;
1346        }
1347        /* Set our current interrupt mask */
1348        outb(ier, iobase+IER);
1349        
1350        /* Restore BSR */
1351        outb(bank, iobase+BSR);
1352
1353        /* Make sure interrupt handlers keep the proper interrupt mask */
1354        return ier;
1355}
1356
1357/*
1358 * Function nsc_ircc_hard_xmit (skb, dev)
1359 *
1360 *    Transmit the frame!
1361 *
1362 */
1363static netdev_tx_t nsc_ircc_hard_xmit_sir(struct sk_buff *skb,
1364                                                struct net_device *dev)
1365{
1366        struct nsc_ircc_cb *self;
1367        unsigned long flags;
1368        int iobase;
1369        __s32 speed;
1370        __u8 bank;
1371        
1372        self = netdev_priv(dev);
1373
1374        IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1375
1376        iobase = self->io.fir_base;
1377
1378        netif_stop_queue(dev);
1379                
1380        /* Make sure tests *& speed change are atomic */
1381        spin_lock_irqsave(&self->lock, flags);
1382        
1383        /* Check if we need to change the speed */
1384        speed = irda_get_next_speed(skb);
1385        if ((speed != self->io.speed) && (speed != -1)) {
1386                /* Check for empty frame. */
1387                if (!skb->len) {
1388                        /* If we just sent a frame, we get called before
1389                         * the last bytes get out (because of the SIR FIFO).
1390                         * If this is the case, let interrupt handler change
1391                         * the speed itself... Jean II */
1392                        if (self->io.direction == IO_RECV) {
1393                                nsc_ircc_change_speed(self, speed); 
1394                                /* TODO : For SIR->SIR, the next packet
1395                                 * may get corrupted - Jean II */
1396                                netif_wake_queue(dev);
1397                        } else {
1398                                self->new_speed = speed;
1399                                /* Queue will be restarted after speed change
1400                                 * to make sure packets gets through the
1401                                 * proper xmit handler - Jean II */
1402                        }
1403                        netif_trans_update(dev);
1404                        spin_unlock_irqrestore(&self->lock, flags);
1405                        dev_kfree_skb(skb);
1406                        return NETDEV_TX_OK;
1407                } else
1408                        self->new_speed = speed;
1409        }
1410
1411        /* Save current bank */
1412        bank = inb(iobase+BSR);
1413        
1414        self->tx_buff.data = self->tx_buff.head;
1415        
1416        self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, 
1417                                           self->tx_buff.truesize);
1418
1419        dev->stats.tx_bytes += self->tx_buff.len;
1420        
1421        /* Add interrupt on tx low level (will fire immediately) */
1422        switch_bank(iobase, BANK0);
1423        outb(IER_TXLDL_IE, iobase+IER);
1424        
1425        /* Restore bank register */
1426        outb(bank, iobase+BSR);
1427
1428        netif_trans_update(dev);
1429        spin_unlock_irqrestore(&self->lock, flags);
1430
1431        dev_kfree_skb(skb);
1432
1433        return NETDEV_TX_OK;
1434}
1435
1436static netdev_tx_t nsc_ircc_hard_xmit_fir(struct sk_buff *skb,
1437                                                struct net_device *dev)
1438{
1439        struct nsc_ircc_cb *self;
1440        unsigned long flags;
1441        int iobase;
1442        __s32 speed;
1443        __u8 bank;
1444        int mtt, diff;
1445        
1446        self = netdev_priv(dev);
1447        iobase = self->io.fir_base;
1448
1449        netif_stop_queue(dev);
1450        
1451        /* Make sure tests *& speed change are atomic */
1452        spin_lock_irqsave(&self->lock, flags);
1453
1454        /* Check if we need to change the speed */
1455        speed = irda_get_next_speed(skb);
1456        if ((speed != self->io.speed) && (speed != -1)) {
1457                /* Check for empty frame. */
1458                if (!skb->len) {
1459                        /* If we are currently transmitting, defer to
1460                         * interrupt handler. - Jean II */
1461                        if(self->tx_fifo.len == 0) {
1462                                nsc_ircc_change_speed(self, speed); 
1463                                netif_wake_queue(dev);
1464                        } else {
1465                                self->new_speed = speed;
1466                                /* Keep queue stopped :
1467                                 * the speed change operation may change the
1468                                 * xmit handler, and we want to make sure
1469                                 * the next packet get through the proper
1470                                 * Tx path, so block the Tx queue until
1471                                 * the speed change has been done.
1472                                 * Jean II */
1473                        }
1474                        netif_trans_update(dev);
1475                        spin_unlock_irqrestore(&self->lock, flags);
1476                        dev_kfree_skb(skb);
1477                        return NETDEV_TX_OK;
1478                } else {
1479                        /* Change speed after current frame */
1480                        self->new_speed = speed;
1481                }
1482        }
1483
1484        /* Save current bank */
1485        bank = inb(iobase+BSR);
1486
1487        /* Register and copy this frame to DMA memory */
1488        self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
1489        self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
1490        self->tx_fifo.tail += skb->len;
1491
1492        dev->stats.tx_bytes += skb->len;
1493
1494        skb_copy_from_linear_data(skb, self->tx_fifo.queue[self->tx_fifo.free].start,
1495                      skb->len);
1496        self->tx_fifo.len++;
1497        self->tx_fifo.free++;
1498
1499        /* Start transmit only if there is currently no transmit going on */
1500        if (self->tx_fifo.len == 1) {
1501                /* Check if we must wait the min turn time or not */
1502                mtt = irda_get_mtt(skb);
1503                if (mtt) {
1504                        /* Check how much time we have used already */
1505                        diff = ktime_us_delta(ktime_get(), self->stamp);
1506                        
1507                        /* Check if the mtt is larger than the time we have
1508                         * already used by all the protocol processing
1509                         */
1510                        if (mtt > diff) {
1511                                mtt -= diff;
1512
1513                                /* 
1514                                 * Use timer if delay larger than 125 us, and
1515                                 * use udelay for smaller values which should
1516                                 * be acceptable
1517                                 */
1518                                if (mtt > 125) {
1519                                        /* Adjust for timer resolution */
1520                                        mtt = mtt / 125;
1521                                        
1522                                        /* Setup timer */
1523                                        switch_bank(iobase, BANK4);
1524                                        outb(mtt & 0xff, iobase+TMRL);
1525                                        outb((mtt >> 8) & 0x0f, iobase+TMRH);
1526                                        
1527                                        /* Start timer */
1528                                        outb(IRCR1_TMR_EN, iobase+IRCR1);
1529                                        self->io.direction = IO_XMIT;
1530                                        
1531                                        /* Enable timer interrupt */
1532                                        switch_bank(iobase, BANK0);
1533                                        outb(IER_TMR_IE, iobase+IER);
1534                                        
1535                                        /* Timer will take care of the rest */
1536                                        goto out; 
1537                                } else
1538                                        udelay(mtt);
1539                        }
1540                }               
1541                /* Enable DMA interrupt */
1542                switch_bank(iobase, BANK0);
1543                outb(IER_DMA_IE, iobase+IER);
1544
1545                /* Transmit frame */
1546                nsc_ircc_dma_xmit(self, iobase);
1547        }
1548 out:
1549        /* Not busy transmitting anymore if window is not full,
1550         * and if we don't need to change speed */
1551        if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0))
1552                netif_wake_queue(self->netdev);
1553
1554        /* Restore bank register */
1555        outb(bank, iobase+BSR);
1556
1557        netif_trans_update(dev);
1558        spin_unlock_irqrestore(&self->lock, flags);
1559        dev_kfree_skb(skb);
1560
1561        return NETDEV_TX_OK;
1562}
1563
1564/*
1565 * Function nsc_ircc_dma_xmit (self, iobase)
1566 *
1567 *    Transmit data using DMA
1568 *
1569 */
1570static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase)
1571{
1572        int bsr;
1573
1574        /* Save current bank */
1575        bsr = inb(iobase+BSR);
1576
1577        /* Disable DMA */
1578        switch_bank(iobase, BANK0);
1579        outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1580        
1581        self->io.direction = IO_XMIT;
1582        
1583        /* Choose transmit DMA channel  */ 
1584        switch_bank(iobase, BANK2);
1585        outb(ECR1_DMASWP|ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1);
1586        
1587        irda_setup_dma(self->io.dma, 
1588                       ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
1589                        self->tx_buff.head) + self->tx_buff_dma,
1590                       self->tx_fifo.queue[self->tx_fifo.ptr].len, 
1591                       DMA_TX_MODE);
1592
1593        /* Enable DMA and SIR interaction pulse */
1594        switch_bank(iobase, BANK0);     
1595        outb(inb(iobase+MCR)|MCR_TX_DFR|MCR_DMA_EN|MCR_IR_PLS, iobase+MCR);
1596
1597        /* Restore bank register */
1598        outb(bsr, iobase+BSR);
1599}
1600
1601/*
1602 * Function nsc_ircc_pio_xmit (self, iobase)
1603 *
1604 *    Transmit data using PIO. Returns the number of bytes that actually
1605 *    got transferred
1606 *
1607 */
1608static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
1609{
1610        int actual = 0;
1611        __u8 bank;
1612        
1613        /* Save current bank */
1614        bank = inb(iobase+BSR);
1615
1616        switch_bank(iobase, BANK0);
1617        if (!(inb_p(iobase+LSR) & LSR_TXEMP)) {
1618                pr_debug("%s(), warning, FIFO not empty yet!\n",
1619                         __func__);
1620
1621                /* FIFO may still be filled to the Tx interrupt threshold */
1622                fifo_size -= 17;
1623        }
1624
1625        /* Fill FIFO with current frame */
1626        while ((fifo_size-- > 0) && (actual < len)) {
1627                /* Transmit next byte */
1628                outb(buf[actual++], iobase+TXD);
1629        }
1630        
1631        pr_debug("%s(), fifo_size %d ; %d sent of %d\n",
1632                 __func__, fifo_size, actual, len);
1633        
1634        /* Restore bank */
1635        outb(bank, iobase+BSR);
1636
1637        return actual;
1638}
1639
1640/*
1641 * Function nsc_ircc_dma_xmit_complete (self)
1642 *
1643 *    The transfer of a frame in finished. This function will only be called 
1644 *    by the interrupt handler
1645 *
1646 */
1647static int nsc_ircc_dma_xmit_complete(struct nsc_ircc_cb *self)
1648{
1649        int iobase;
1650        __u8 bank;
1651        int ret = TRUE;
1652
1653        iobase = self->io.fir_base;
1654
1655        /* Save current bank */
1656        bank = inb(iobase+BSR);
1657
1658        /* Disable DMA */
1659        switch_bank(iobase, BANK0);
1660        outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1661        
1662        /* Check for underrun! */
1663        if (inb(iobase+ASCR) & ASCR_TXUR) {
1664                self->netdev->stats.tx_errors++;
1665                self->netdev->stats.tx_fifo_errors++;
1666                
1667                /* Clear bit, by writing 1 into it */
1668                outb(ASCR_TXUR, iobase+ASCR);
1669        } else {
1670                self->netdev->stats.tx_packets++;
1671        }
1672
1673        /* Finished with this frame, so prepare for next */
1674        self->tx_fifo.ptr++;
1675        self->tx_fifo.len--;
1676
1677        /* Any frames to be sent back-to-back? */
1678        if (self->tx_fifo.len) {
1679                nsc_ircc_dma_xmit(self, iobase);
1680                
1681                /* Not finished yet! */
1682                ret = FALSE;
1683        } else {
1684                /* Reset Tx FIFO info */
1685                self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1686                self->tx_fifo.tail = self->tx_buff.head;
1687        }
1688
1689        /* Make sure we have room for more frames and
1690         * that we don't need to change speed */
1691        if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0)) {
1692                /* Not busy transmitting anymore */
1693                /* Tell the network layer, that we can accept more frames */
1694                netif_wake_queue(self->netdev);
1695        }
1696
1697        /* Restore bank */
1698        outb(bank, iobase+BSR);
1699        
1700        return ret;
1701}
1702
1703/*
1704 * Function nsc_ircc_dma_receive (self)
1705 *
1706 *    Get ready for receiving a frame. The device will initiate a DMA
1707 *    if it starts to receive a frame.
1708 *
1709 */
1710static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self) 
1711{
1712        int iobase;
1713        __u8 bsr;
1714
1715        iobase = self->io.fir_base;
1716
1717        /* Reset Tx FIFO info */
1718        self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1719        self->tx_fifo.tail = self->tx_buff.head;
1720
1721        /* Save current bank */
1722        bsr = inb(iobase+BSR);
1723
1724        /* Disable DMA */
1725        switch_bank(iobase, BANK0);
1726        outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1727
1728        /* Choose DMA Rx, DMA Fairness, and Advanced mode */
1729        switch_bank(iobase, BANK2);
1730        outb(ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1);
1731
1732        self->io.direction = IO_RECV;
1733        self->rx_buff.data = self->rx_buff.head;
1734        
1735        /* Reset Rx FIFO. This will also flush the ST_FIFO */
1736        switch_bank(iobase, BANK0);
1737        outb(FCR_RXSR|FCR_FIFO_EN, iobase+FCR);
1738
1739        self->st_fifo.len = self->st_fifo.pending_bytes = 0;
1740        self->st_fifo.tail = self->st_fifo.head = 0;
1741        
1742        irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1743                       DMA_RX_MODE);
1744
1745        /* Enable DMA */
1746        switch_bank(iobase, BANK0);
1747        outb(inb(iobase+MCR)|MCR_DMA_EN, iobase+MCR);
1748
1749        /* Restore bank register */
1750        outb(bsr, iobase+BSR);
1751        
1752        return 0;
1753}
1754
1755/*
1756 * Function nsc_ircc_dma_receive_complete (self)
1757 *
1758 *    Finished with receiving frames
1759 *
1760 *    
1761 */
1762static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase)
1763{
1764        struct st_fifo *st_fifo;
1765        struct sk_buff *skb;
1766        __u8 status;
1767        __u8 bank;
1768        int len;
1769
1770        st_fifo = &self->st_fifo;
1771
1772        /* Save current bank */
1773        bank = inb(iobase+BSR);
1774        
1775        /* Read all entries in status FIFO */
1776        switch_bank(iobase, BANK5);
1777        while ((status = inb(iobase+FRM_ST)) & FRM_ST_VLD) {
1778                /* We must empty the status FIFO no matter what */
1779                len = inb(iobase+RFLFL) | ((inb(iobase+RFLFH) & 0x1f) << 8);
1780
1781                if (st_fifo->tail >= MAX_RX_WINDOW) {
1782                        pr_debug("%s(), window is full!\n", __func__);
1783                        continue;
1784                }
1785                        
1786                st_fifo->entries[st_fifo->tail].status = status;
1787                st_fifo->entries[st_fifo->tail].len = len;
1788                st_fifo->pending_bytes += len;
1789                st_fifo->tail++;
1790                st_fifo->len++;
1791        }
1792        /* Try to process all entries in status FIFO */
1793        while (st_fifo->len > 0) {
1794                /* Get first entry */
1795                status = st_fifo->entries[st_fifo->head].status;
1796                len    = st_fifo->entries[st_fifo->head].len;
1797                st_fifo->pending_bytes -= len;
1798                st_fifo->head++;
1799                st_fifo->len--;
1800
1801                /* Check for errors */
1802                if (status & FRM_ST_ERR_MSK) {
1803                        if (status & FRM_ST_LOST_FR) {
1804                                /* Add number of lost frames to stats */
1805                                self->netdev->stats.rx_errors += len;
1806                        } else {
1807                                /* Skip frame */
1808                                self->netdev->stats.rx_errors++;
1809                                
1810                                self->rx_buff.data += len;
1811                        
1812                                if (status & FRM_ST_MAX_LEN)
1813                                        self->netdev->stats.rx_length_errors++;
1814                                
1815                                if (status & FRM_ST_PHY_ERR) 
1816                                        self->netdev->stats.rx_frame_errors++;
1817                                
1818                                if (status & FRM_ST_BAD_CRC) 
1819                                        self->netdev->stats.rx_crc_errors++;
1820                        }
1821                        /* The errors below can be reported in both cases */
1822                        if (status & FRM_ST_OVR1)
1823                                self->netdev->stats.rx_fifo_errors++;
1824                        
1825                        if (status & FRM_ST_OVR2)
1826                                self->netdev->stats.rx_fifo_errors++;
1827                } else {
1828                        /*  
1829                         * First we must make sure that the frame we
1830                         * want to deliver is all in main memory. If we
1831                         * cannot tell, then we check if the Rx FIFO is
1832                         * empty. If not then we will have to take a nap
1833                         * and try again later.  
1834                         */
1835                        if (st_fifo->pending_bytes < self->io.fifo_size) {
1836                                switch_bank(iobase, BANK0);
1837                                if (inb(iobase+LSR) & LSR_RXDA) {
1838                                        /* Put this entry back in fifo */
1839                                        st_fifo->head--;
1840                                        st_fifo->len++;
1841                                        st_fifo->pending_bytes += len;
1842                                        st_fifo->entries[st_fifo->head].status = status;
1843                                        st_fifo->entries[st_fifo->head].len = len;
1844                                        /*  
1845                                         * DMA not finished yet, so try again 
1846                                         * later, set timer value, resolution 
1847                                         * 125 us 
1848                                         */
1849                                        switch_bank(iobase, BANK4);
1850                                        outb(0x02, iobase+TMRL); /* x 125 us */
1851                                        outb(0x00, iobase+TMRH);
1852
1853                                        /* Start timer */
1854                                        outb(IRCR1_TMR_EN, iobase+IRCR1);
1855
1856                                        /* Restore bank register */
1857                                        outb(bank, iobase+BSR);
1858                                        
1859                                        return FALSE; /* I'll be back! */
1860                                }
1861                        }
1862
1863                        /* 
1864                         * Remember the time we received this frame, so we can
1865                         * reduce the min turn time a bit since we will know
1866                         * how much time we have used for protocol processing
1867                         */
1868                        self->stamp = ktime_get();
1869
1870                        skb = dev_alloc_skb(len+1);
1871                        if (skb == NULL)  {
1872                                self->netdev->stats.rx_dropped++;
1873
1874                                /* Restore bank register */
1875                                outb(bank, iobase+BSR);
1876
1877                                return FALSE;
1878                        }
1879                        
1880                        /* Make sure IP header gets aligned */
1881                        skb_reserve(skb, 1); 
1882
1883                        /* Copy frame without CRC */
1884                        if (self->io.speed < 4000000) {
1885                                skb_put(skb, len-2);
1886                                skb_copy_to_linear_data(skb,
1887                                                        self->rx_buff.data,
1888                                                        len - 2);
1889                        } else {
1890                                skb_put(skb, len-4);
1891                                skb_copy_to_linear_data(skb,
1892                                                        self->rx_buff.data,
1893                                                        len - 4);
1894                        }
1895
1896                        /* Move to next frame */
1897                        self->rx_buff.data += len;
1898                        self->netdev->stats.rx_bytes += len;
1899                        self->netdev->stats.rx_packets++;
1900
1901                        skb->dev = self->netdev;
1902                        skb_reset_mac_header(skb);
1903                        skb->protocol = htons(ETH_P_IRDA);
1904                        netif_rx(skb);
1905                }
1906        }
1907        /* Restore bank register */
1908        outb(bank, iobase+BSR);
1909
1910        return TRUE;
1911}
1912
1913/*
1914 * Function nsc_ircc_pio_receive (self)
1915 *
1916 *    Receive all data in receiver FIFO
1917 *
1918 */
1919static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self) 
1920{
1921        __u8 byte;
1922        int iobase;
1923
1924        iobase = self->io.fir_base;
1925        
1926        /*  Receive all characters in Rx FIFO */
1927        do {
1928                byte = inb(iobase+RXD);
1929                async_unwrap_char(self->netdev, &self->netdev->stats,
1930                                  &self->rx_buff, byte);
1931        } while (inb(iobase+LSR) & LSR_RXDA); /* Data available */      
1932}
1933
1934/*
1935 * Function nsc_ircc_sir_interrupt (self, eir)
1936 *
1937 *    Handle SIR interrupt
1938 *
1939 */
1940static void nsc_ircc_sir_interrupt(struct nsc_ircc_cb *self, int eir)
1941{
1942        int actual;
1943
1944        /* Check if transmit FIFO is low on data */
1945        if (eir & EIR_TXLDL_EV) {
1946                /* Write data left in transmit buffer */
1947                actual = nsc_ircc_pio_write(self->io.fir_base, 
1948                                           self->tx_buff.data, 
1949                                           self->tx_buff.len, 
1950                                           self->io.fifo_size);
1951                self->tx_buff.data += actual;
1952                self->tx_buff.len  -= actual;
1953                
1954                self->io.direction = IO_XMIT;
1955
1956                /* Check if finished */
1957                if (self->tx_buff.len > 0)
1958                        self->ier = IER_TXLDL_IE;
1959                else { 
1960
1961                        self->netdev->stats.tx_packets++;
1962                        netif_wake_queue(self->netdev);
1963                        self->ier = IER_TXEMP_IE;
1964                }
1965                        
1966        }
1967        /* Check if transmission has completed */
1968        if (eir & EIR_TXEMP_EV) {
1969                /* Turn around and get ready to receive some data */
1970                self->io.direction = IO_RECV;
1971                self->ier = IER_RXHDL_IE;
1972                /* Check if we need to change the speed?
1973                 * Need to be after self->io.direction to avoid race with
1974                 * nsc_ircc_hard_xmit_sir() - Jean II */
1975                if (self->new_speed) {
1976                        pr_debug("%s(), Changing speed!\n", __func__);
1977                        self->ier = nsc_ircc_change_speed(self,
1978                                                          self->new_speed);
1979                        self->new_speed = 0;
1980                        netif_wake_queue(self->netdev);
1981
1982                        /* Check if we are going to FIR */
1983                        if (self->io.speed > 115200) {
1984                                /* No need to do anymore SIR stuff */
1985                                return;
1986                        }
1987                }
1988        }
1989
1990        /* Rx FIFO threshold or timeout */
1991        if (eir & EIR_RXHDL_EV) {
1992                nsc_ircc_pio_receive(self);
1993
1994                /* Keep receiving */
1995                self->ier = IER_RXHDL_IE;
1996        }
1997}
1998
1999/*
2000 * Function nsc_ircc_fir_interrupt (self, eir)
2001 *
2002 *    Handle MIR/FIR interrupt
2003 *
2004 */
2005static void nsc_ircc_fir_interrupt(struct nsc_ircc_cb *self, int iobase, 
2006                                   int eir)
2007{
2008        __u8 bank;
2009
2010        bank = inb(iobase+BSR);
2011        
2012        /* Status FIFO event*/
2013        if (eir & EIR_SFIF_EV) {
2014                /* Check if DMA has finished */
2015                if (nsc_ircc_dma_receive_complete(self, iobase)) {
2016                        /* Wait for next status FIFO interrupt */
2017                        self->ier = IER_SFIF_IE;
2018                } else {
2019                        self->ier = IER_SFIF_IE | IER_TMR_IE;
2020                }
2021        } else if (eir & EIR_TMR_EV) { /* Timer finished */
2022                /* Disable timer */
2023                switch_bank(iobase, BANK4);
2024                outb(0, iobase+IRCR1);
2025
2026                /* Clear timer event */
2027                switch_bank(iobase, BANK0);
2028                outb(ASCR_CTE, iobase+ASCR);
2029
2030                /* Check if this is a Tx timer interrupt */
2031                if (self->io.direction == IO_XMIT) {
2032                        nsc_ircc_dma_xmit(self, iobase);
2033
2034                        /* Interrupt on DMA */
2035                        self->ier = IER_DMA_IE;
2036                } else {
2037                        /* Check (again) if DMA has finished */
2038                        if (nsc_ircc_dma_receive_complete(self, iobase)) {
2039                                self->ier = IER_SFIF_IE;
2040                        } else {
2041                                self->ier = IER_SFIF_IE | IER_TMR_IE;
2042                        }
2043                }
2044        } else if (eir & EIR_DMA_EV) {
2045                /* Finished with all transmissions? */
2046                if (nsc_ircc_dma_xmit_complete(self)) {
2047                        if(self->new_speed != 0) {
2048                                /* As we stop the Tx queue, the speed change
2049                                 * need to be done when the Tx fifo is
2050                                 * empty. Ask for a Tx done interrupt */
2051                                self->ier = IER_TXEMP_IE;
2052                        } else {
2053                                /* Check if there are more frames to be
2054                                 * transmitted */
2055                                if (irda_device_txqueue_empty(self->netdev)) {
2056                                        /* Prepare for receive */
2057                                        nsc_ircc_dma_receive(self);
2058                                        self->ier = IER_SFIF_IE;
2059                                } else
2060                                        net_warn_ratelimited("%s(), potential Tx queue lockup !\n",
2061                                                             __func__);
2062                        }
2063                } else {
2064                        /*  Not finished yet, so interrupt on DMA again */
2065                        self->ier = IER_DMA_IE;
2066                }
2067        } else if (eir & EIR_TXEMP_EV) {
2068                /* The Tx FIFO has totally drained out, so now we can change
2069                 * the speed... - Jean II */
2070                self->ier = nsc_ircc_change_speed(self, self->new_speed);
2071                self->new_speed = 0;
2072                netif_wake_queue(self->netdev);
2073                /* Note : nsc_ircc_change_speed() restarted Rx fifo */
2074        }
2075
2076        outb(bank, iobase+BSR);
2077}
2078
2079/*
2080 * Function nsc_ircc_interrupt (irq, dev_id, regs)
2081 *
2082 *    An interrupt from the chip has arrived. Time to do some work
2083 *
2084 */
2085static irqreturn_t nsc_ircc_interrupt(int irq, void *dev_id)
2086{
2087        struct net_device *dev = dev_id;
2088        struct nsc_ircc_cb *self;
2089        __u8 bsr, eir;
2090        int iobase;
2091
2092        self = netdev_priv(dev);
2093
2094        spin_lock(&self->lock); 
2095
2096        iobase = self->io.fir_base;
2097
2098        bsr = inb(iobase+BSR);  /* Save current bank */
2099
2100        switch_bank(iobase, BANK0);     
2101        self->ier = inb(iobase+IER); 
2102        eir = inb(iobase+EIR) & self->ier; /* Mask out the interesting ones */ 
2103
2104        outb(0, iobase+IER); /* Disable interrupts */
2105        
2106        if (eir) {
2107                /* Dispatch interrupt handler for the current speed */
2108                if (self->io.speed > 115200)
2109                        nsc_ircc_fir_interrupt(self, iobase, eir);
2110                else
2111                        nsc_ircc_sir_interrupt(self, eir);
2112        }
2113        
2114        outb(self->ier, iobase+IER); /* Restore interrupts */
2115        outb(bsr, iobase+BSR);       /* Restore bank register */
2116
2117        spin_unlock(&self->lock);
2118        return IRQ_RETVAL(eir);
2119}
2120
2121/*
2122 * Function nsc_ircc_is_receiving (self)
2123 *
2124 *    Return TRUE is we are currently receiving a frame
2125 *
2126 */
2127static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self)
2128{
2129        unsigned long flags;
2130        int status = FALSE;
2131        int iobase;
2132        __u8 bank;
2133
2134        IRDA_ASSERT(self != NULL, return FALSE;);
2135
2136        spin_lock_irqsave(&self->lock, flags);
2137
2138        if (self->io.speed > 115200) {
2139                iobase = self->io.fir_base;
2140
2141                /* Check if rx FIFO is not empty */
2142                bank = inb(iobase+BSR);
2143                switch_bank(iobase, BANK2);
2144                if ((inb(iobase+RXFLV) & 0x3f) != 0) {
2145                        /* We are receiving something */
2146                        status =  TRUE;
2147                }
2148                outb(bank, iobase+BSR);
2149        } else 
2150                status = (self->rx_buff.state != OUTSIDE_FRAME);
2151        
2152        spin_unlock_irqrestore(&self->lock, flags);
2153
2154        return status;
2155}
2156
2157/*
2158 * Function nsc_ircc_net_open (dev)
2159 *
2160 *    Start the device
2161 *
2162 */
2163static int nsc_ircc_net_open(struct net_device *dev)
2164{
2165        struct nsc_ircc_cb *self;
2166        int iobase;
2167        char hwname[32];
2168        __u8 bank;
2169        
2170        
2171        IRDA_ASSERT(dev != NULL, return -1;);
2172        self = netdev_priv(dev);
2173        
2174        IRDA_ASSERT(self != NULL, return 0;);
2175        
2176        iobase = self->io.fir_base;
2177        
2178        if (request_irq(self->io.irq, nsc_ircc_interrupt, 0, dev->name, dev)) {
2179                net_warn_ratelimited("%s, unable to allocate irq=%d\n",
2180                                     driver_name, self->io.irq);
2181                return -EAGAIN;
2182        }
2183        /*
2184         * Always allocate the DMA channel after the IRQ, and clean up on 
2185         * failure.
2186         */
2187        if (request_dma(self->io.dma, dev->name)) {
2188                net_warn_ratelimited("%s, unable to allocate dma=%d\n",
2189                                     driver_name, self->io.dma);
2190                free_irq(self->io.irq, dev);
2191                return -EAGAIN;
2192        }
2193        
2194        /* Save current bank */
2195        bank = inb(iobase+BSR);
2196        
2197        /* turn on interrupts */
2198        switch_bank(iobase, BANK0);
2199        outb(IER_LS_IE | IER_RXHDL_IE, iobase+IER);
2200
2201        /* Restore bank register */
2202        outb(bank, iobase+BSR);
2203
2204        /* Ready to play! */
2205        netif_start_queue(dev);
2206        
2207        /* Give self a hardware name */
2208        sprintf(hwname, "NSC-FIR @ 0x%03x", self->io.fir_base);
2209
2210        /* 
2211         * Open new IrLAP layer instance, now that everything should be
2212         * initialized properly 
2213         */
2214        self->irlap = irlap_open(dev, &self->qos, hwname);
2215
2216        return 0;
2217}
2218
2219/*
2220 * Function nsc_ircc_net_close (dev)
2221 *
2222 *    Stop the device
2223 *
2224 */
2225static int nsc_ircc_net_close(struct net_device *dev)
2226{
2227        struct nsc_ircc_cb *self;
2228        int iobase;
2229        __u8 bank;
2230
2231        
2232        IRDA_ASSERT(dev != NULL, return -1;);
2233
2234        self = netdev_priv(dev);
2235        IRDA_ASSERT(self != NULL, return 0;);
2236
2237        /* Stop device */
2238        netif_stop_queue(dev);
2239        
2240        /* Stop and remove instance of IrLAP */
2241        if (self->irlap)
2242                irlap_close(self->irlap);
2243        self->irlap = NULL;
2244        
2245        iobase = self->io.fir_base;
2246
2247        disable_dma(self->io.dma);
2248
2249        /* Save current bank */
2250        bank = inb(iobase+BSR);
2251
2252        /* Disable interrupts */
2253        switch_bank(iobase, BANK0);
2254        outb(0, iobase+IER); 
2255       
2256        free_irq(self->io.irq, dev);
2257        free_dma(self->io.dma);
2258
2259        /* Restore bank register */
2260        outb(bank, iobase+BSR);
2261
2262        return 0;
2263}
2264
2265/*
2266 * Function nsc_ircc_net_ioctl (dev, rq, cmd)
2267 *
2268 *    Process IOCTL commands for this device
2269 *
2270 */
2271static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2272{
2273        struct if_irda_req *irq = (struct if_irda_req *) rq;
2274        struct nsc_ircc_cb *self;
2275        unsigned long flags;
2276        int ret = 0;
2277
2278        IRDA_ASSERT(dev != NULL, return -1;);
2279
2280        self = netdev_priv(dev);
2281
2282        IRDA_ASSERT(self != NULL, return -1;);
2283
2284        pr_debug("%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
2285        
2286        switch (cmd) {
2287        case SIOCSBANDWIDTH: /* Set bandwidth */
2288                if (!capable(CAP_NET_ADMIN)) {
2289                        ret = -EPERM;
2290                        break;
2291                }
2292                spin_lock_irqsave(&self->lock, flags);
2293                nsc_ircc_change_speed(self, irq->ifr_baudrate);
2294                spin_unlock_irqrestore(&self->lock, flags);
2295                break;
2296        case SIOCSMEDIABUSY: /* Set media busy */
2297                if (!capable(CAP_NET_ADMIN)) {
2298                        ret = -EPERM;
2299                        break;
2300                }
2301                irda_device_set_media_busy(self->netdev, TRUE);
2302                break;
2303        case SIOCGRECEIVING: /* Check if we are receiving right now */
2304                /* This is already protected */
2305                irq->ifr_receiving = nsc_ircc_is_receiving(self);
2306                break;
2307        default:
2308                ret = -EOPNOTSUPP;
2309        }
2310        return ret;
2311}
2312
2313static int nsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
2314{
2315        struct nsc_ircc_cb *self = platform_get_drvdata(dev);
2316        int bank;
2317        unsigned long flags;
2318        int iobase = self->io.fir_base;
2319
2320        if (self->io.suspended)
2321                return 0;
2322
2323        pr_debug("%s, Suspending\n", driver_name);
2324
2325        rtnl_lock();
2326        if (netif_running(self->netdev)) {
2327                netif_device_detach(self->netdev);
2328                spin_lock_irqsave(&self->lock, flags);
2329                /* Save current bank */
2330                bank = inb(iobase+BSR);
2331
2332                /* Disable interrupts */
2333                switch_bank(iobase, BANK0);
2334                outb(0, iobase+IER);
2335
2336                /* Restore bank register */
2337                outb(bank, iobase+BSR);
2338
2339                spin_unlock_irqrestore(&self->lock, flags);
2340                free_irq(self->io.irq, self->netdev);
2341                disable_dma(self->io.dma);
2342        }
2343        self->io.suspended = 1;
2344        rtnl_unlock();
2345
2346        return 0;
2347}
2348
2349static int nsc_ircc_resume(struct platform_device *dev)
2350{
2351        struct nsc_ircc_cb *self = platform_get_drvdata(dev);
2352        unsigned long flags;
2353
2354        if (!self->io.suspended)
2355                return 0;
2356
2357        pr_debug("%s, Waking up\n", driver_name);
2358
2359        rtnl_lock();
2360        nsc_ircc_setup(&self->io);
2361        nsc_ircc_init_dongle_interface(self->io.fir_base, self->io.dongle_id);
2362
2363        if (netif_running(self->netdev)) {
2364                if (request_irq(self->io.irq, nsc_ircc_interrupt, 0,
2365                                self->netdev->name, self->netdev)) {
2366                        net_warn_ratelimited("%s, unable to allocate irq=%d\n",
2367                                             driver_name, self->io.irq);
2368
2369                        /*
2370                         * Don't fail resume process, just kill this
2371                         * network interface
2372                         */
2373                        unregister_netdevice(self->netdev);
2374                } else {
2375                        spin_lock_irqsave(&self->lock, flags);
2376                        nsc_ircc_change_speed(self, self->io.speed);
2377                        spin_unlock_irqrestore(&self->lock, flags);
2378                        netif_device_attach(self->netdev);
2379                }
2380
2381        } else {
2382                spin_lock_irqsave(&self->lock, flags);
2383                nsc_ircc_change_speed(self, 9600);
2384                spin_unlock_irqrestore(&self->lock, flags);
2385        }
2386        self->io.suspended = 0;
2387        rtnl_unlock();
2388
2389        return 0;
2390}
2391
2392MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
2393MODULE_DESCRIPTION("NSC IrDA Device Driver");
2394MODULE_LICENSE("GPL");
2395
2396
2397module_param(qos_mtt_bits, int, 0);
2398MODULE_PARM_DESC(qos_mtt_bits, "Minimum Turn Time");
2399module_param_array(io, int, NULL, 0);
2400MODULE_PARM_DESC(io, "Base I/O addresses");
2401module_param_array(irq, int, NULL, 0);
2402MODULE_PARM_DESC(irq, "IRQ lines");
2403module_param_array(dma, int, NULL, 0);
2404MODULE_PARM_DESC(dma, "DMA channels");
2405module_param(dongle_id, int, 0);
2406MODULE_PARM_DESC(dongle_id, "Type-id of used dongle");
2407
2408module_init(nsc_ircc_init);
2409module_exit(nsc_ircc_cleanup);
2410
2411