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25#ifndef __ACX_H__
26#define __ACX_H__
27
28#include "wlcore.h"
29#include "cmd.h"
30
31
32
33
34
35
36
37#define WL1271_ACX_INTR_WATCHDOG BIT(0)
38
39#define WL1271_ACX_INTR_INIT_COMPLETE BIT(1)
40
41#define WL1271_ACX_INTR_EVENT_A BIT(2)
42
43#define WL1271_ACX_INTR_EVENT_B BIT(3)
44
45#define WL1271_ACX_INTR_CMD_COMPLETE BIT(4)
46
47#define WL1271_ACX_INTR_HW_AVAILABLE BIT(5)
48
49#define WL1271_ACX_INTR_DATA BIT(6)
50
51#define WL1271_ACX_INTR_TRACE_A BIT(7)
52
53#define WL1271_ACX_INTR_TRACE_B BIT(8)
54
55#define WL1271_ACX_SW_INTR_WATCHDOG BIT(9)
56
57#define WL1271_ACX_INTR_ALL 0xFFFFFFFF
58
59
60#define WLCORE_ALL_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \
61 WL1271_ACX_INTR_EVENT_A | \
62 WL1271_ACX_INTR_EVENT_B | \
63 WL1271_ACX_INTR_HW_AVAILABLE | \
64 WL1271_ACX_INTR_DATA | \
65 WL1271_ACX_SW_INTR_WATCHDOG)
66
67
68struct acx_header {
69 struct wl1271_cmd_header cmd;
70
71
72 __le16 id;
73
74
75 __le16 len;
76} __packed;
77
78struct acx_error_counter {
79 struct acx_header header;
80
81
82
83
84 __le32 PLCP_error;
85
86
87
88
89 __le32 FCS_error;
90
91
92
93
94 __le32 valid_frame;
95
96
97
98 __le32 seq_num_miss;
99} __packed;
100
101enum wl12xx_role {
102 WL1271_ROLE_STA = 0,
103 WL1271_ROLE_IBSS,
104 WL1271_ROLE_AP,
105 WL1271_ROLE_DEVICE,
106 WL1271_ROLE_P2P_CL,
107 WL1271_ROLE_P2P_GO,
108 WL1271_ROLE_MESH_POINT,
109
110 WL12XX_INVALID_ROLE_TYPE = 0xff
111};
112
113enum wl1271_psm_mode {
114
115 WL1271_PSM_CAM = 0,
116
117
118 WL1271_PSM_PS = 1,
119
120
121 WL1271_PSM_ELP = 2,
122
123 WL1271_PSM_MAX = WL1271_PSM_ELP,
124
125
126 WL1271_PSM_ILLEGAL = 0xff
127};
128
129struct acx_sleep_auth {
130 struct acx_header header;
131
132
133
134
135
136 u8 sleep_auth;
137 u8 padding[3];
138} __packed;
139
140enum {
141 HOSTIF_PCI_MASTER_HOST_INDIRECT,
142 HOSTIF_PCI_MASTER_HOST_DIRECT,
143 HOSTIF_SLAVE,
144 HOSTIF_PKT_RING,
145 HOSTIF_DONTCARE = 0xFF
146};
147
148#define DEFAULT_UCAST_PRIORITY 0
149#define DEFAULT_RX_Q_PRIORITY 0
150#define DEFAULT_RXQ_PRIORITY 0
151#define DEFAULT_RXQ_TYPE 0x07
152#define TRACE_BUFFER_MAX_SIZE 256
153
154#define DP_RX_PACKET_RING_CHUNK_SIZE 1600
155#define DP_TX_PACKET_RING_CHUNK_SIZE 1600
156#define DP_RX_PACKET_RING_CHUNK_NUM 2
157#define DP_TX_PACKET_RING_CHUNK_NUM 2
158#define DP_TX_COMPLETE_TIME_OUT 20
159
160#define TX_MSDU_LIFETIME_MIN 0
161#define TX_MSDU_LIFETIME_MAX 3000
162#define TX_MSDU_LIFETIME_DEF 512
163#define RX_MSDU_LIFETIME_MIN 0
164#define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
165#define RX_MSDU_LIFETIME_DEF 512000
166
167struct acx_rx_msdu_lifetime {
168 struct acx_header header;
169
170
171
172
173
174 __le32 lifetime;
175} __packed;
176
177enum acx_slot_type {
178 SLOT_TIME_LONG = 0,
179 SLOT_TIME_SHORT = 1,
180 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
181 MAX_SLOT_TIMES = 0xFF
182};
183
184#define STATION_WONE_INDEX 0
185
186struct acx_slot {
187 struct acx_header header;
188
189 u8 role_id;
190 u8 wone_index;
191 u8 slot_time;
192 u8 reserved[5];
193} __packed;
194
195
196#define ACX_MC_ADDRESS_GROUP_MAX (8)
197#define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
198
199struct acx_dot11_grp_addr_tbl {
200 struct acx_header header;
201
202 u8 role_id;
203 u8 enabled;
204 u8 num_groups;
205 u8 pad[1];
206 u8 mac_table[ADDRESS_GROUP_MAX_LEN];
207} __packed;
208
209struct acx_rx_timeout {
210 struct acx_header header;
211
212 u8 role_id;
213 u8 reserved;
214 __le16 ps_poll_timeout;
215 __le16 upsd_timeout;
216 u8 padding[2];
217} __packed;
218
219struct acx_rts_threshold {
220 struct acx_header header;
221
222 u8 role_id;
223 u8 reserved;
224 __le16 threshold;
225} __packed;
226
227struct acx_beacon_filter_option {
228 struct acx_header header;
229
230 u8 role_id;
231 u8 enable;
232
233
234
235
236
237
238
239 u8 max_num_beacons;
240 u8 pad[1];
241} __packed;
242
243
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249
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253
254
255
256
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264
265
266
267#define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
268#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
269#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
270#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
271#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
272 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
273 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
274 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
275
276struct acx_beacon_filter_ie_table {
277 struct acx_header header;
278
279 u8 role_id;
280 u8 num_ie;
281 u8 pad[2];
282 u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
283} __packed;
284
285struct acx_conn_monit_params {
286 struct acx_header header;
287
288 u8 role_id;
289 u8 padding[3];
290 __le32 synch_fail_thold;
291 __le32 bss_lose_timeout;
292} __packed;
293
294struct acx_bt_wlan_coex {
295 struct acx_header header;
296
297 u8 enable;
298 u8 pad[3];
299} __packed;
300
301struct acx_bt_wlan_coex_param {
302 struct acx_header header;
303
304 __le32 params[WLCORE_CONF_SG_PARAMS_MAX];
305 u8 param_idx;
306 u8 padding[3];
307} __packed;
308
309struct acx_dco_itrim_params {
310 struct acx_header header;
311
312 u8 enable;
313 u8 padding[3];
314 __le32 timeout;
315} __packed;
316
317struct acx_energy_detection {
318 struct acx_header header;
319
320
321 __le16 rx_cca_threshold;
322 u8 tx_energy_detection;
323 u8 pad;
324} __packed;
325
326struct acx_beacon_broadcast {
327 struct acx_header header;
328
329 u8 role_id;
330
331 u8 rx_broadcast_in_ps;
332
333 __le16 beacon_rx_timeout;
334 __le16 broadcast_timeout;
335
336
337 u8 ps_poll_threshold;
338 u8 pad[1];
339} __packed;
340
341struct acx_event_mask {
342 struct acx_header header;
343
344 __le32 event_mask;
345 __le32 high_event_mask;
346} __packed;
347
348#define SCAN_PASSIVE BIT(0)
349#define SCAN_5GHZ_BAND BIT(1)
350#define SCAN_TRIGGERED BIT(2)
351#define SCAN_PRIORITY_HIGH BIT(3)
352
353
354#define DF_ENCRYPTION_DISABLE 0x01
355#define DF_SNIFF_MODE_ENABLE 0x80
356
357struct acx_feature_config {
358 struct acx_header header;
359
360 u8 role_id;
361 u8 padding[3];
362 __le32 options;
363 __le32 data_flow_options;
364} __packed;
365
366struct acx_current_tx_power {
367 struct acx_header header;
368
369 u8 role_id;
370 u8 current_tx_power;
371 u8 padding[2];
372} __packed;
373
374struct acx_wake_up_condition {
375 struct acx_header header;
376
377 u8 role_id;
378 u8 wake_up_event;
379 u8 listen_interval;
380 u8 pad[1];
381} __packed;
382
383struct acx_aid {
384 struct acx_header header;
385
386
387
388
389 u8 role_id;
390 u8 reserved;
391 __le16 aid;
392} __packed;
393
394enum acx_preamble_type {
395 ACX_PREAMBLE_LONG = 0,
396 ACX_PREAMBLE_SHORT = 1
397};
398
399struct acx_preamble {
400 struct acx_header header;
401
402
403
404
405
406 u8 role_id;
407 u8 preamble;
408 u8 padding[2];
409} __packed;
410
411enum acx_ctsprotect_type {
412 CTSPROTECT_DISABLE = 0,
413 CTSPROTECT_ENABLE = 1
414};
415
416struct acx_ctsprotect {
417 struct acx_header header;
418 u8 role_id;
419 u8 ctsprotect;
420 u8 padding[2];
421} __packed;
422
423struct acx_rate_class {
424 __le32 enabled_rates;
425 u8 short_retry_limit;
426 u8 long_retry_limit;
427 u8 aflags;
428 u8 reserved;
429};
430
431struct acx_rate_policy {
432 struct acx_header header;
433
434 __le32 rate_policy_idx;
435 struct acx_rate_class rate_policy;
436} __packed;
437
438struct acx_ac_cfg {
439 struct acx_header header;
440 u8 role_id;
441 u8 ac;
442 u8 aifsn;
443 u8 cw_min;
444 __le16 cw_max;
445 __le16 tx_op_limit;
446} __packed;
447
448struct acx_tid_config {
449 struct acx_header header;
450 u8 role_id;
451 u8 queue_id;
452 u8 channel_type;
453 u8 tsid;
454 u8 ps_scheme;
455 u8 ack_policy;
456 u8 padding[2];
457 __le32 apsd_conf[2];
458} __packed;
459
460struct acx_frag_threshold {
461 struct acx_header header;
462 __le16 frag_threshold;
463 u8 padding[2];
464} __packed;
465
466struct acx_tx_config_options {
467 struct acx_header header;
468 __le16 tx_compl_timeout;
469 __le16 tx_compl_threshold;
470} __packed;
471
472struct wl12xx_acx_config_memory {
473 struct acx_header header;
474
475 u8 rx_mem_block_num;
476 u8 tx_min_mem_block_num;
477 u8 num_stations;
478 u8 num_ssid_profiles;
479 __le32 total_tx_descriptors;
480 u8 dyn_mem_enable;
481 u8 tx_free_req;
482 u8 rx_free_req;
483 u8 tx_min;
484 u8 fwlog_blocks;
485 u8 padding[3];
486} __packed;
487
488struct wl1271_acx_mem_map {
489 struct acx_header header;
490
491 __le32 code_start;
492 __le32 code_end;
493
494 __le32 wep_defkey_start;
495 __le32 wep_defkey_end;
496
497 __le32 sta_table_start;
498 __le32 sta_table_end;
499
500 __le32 packet_template_start;
501 __le32 packet_template_end;
502
503
504 __le32 tx_result;
505 __le32 tx_result_queue_start;
506
507 __le32 queue_memory_start;
508 __le32 queue_memory_end;
509
510 __le32 packet_memory_pool_start;
511 __le32 packet_memory_pool_end;
512
513 __le32 debug_buffer1_start;
514 __le32 debug_buffer1_end;
515
516 __le32 debug_buffer2_start;
517 __le32 debug_buffer2_end;
518
519
520 __le32 num_tx_mem_blocks;
521
522
523 __le32 num_rx_mem_blocks;
524
525
526 u8 *tx_cbuf;
527 u8 *rx_cbuf;
528 __le32 rx_ctrl;
529 __le32 tx_ctrl;
530} __packed;
531
532struct wl1271_acx_rx_config_opt {
533 struct acx_header header;
534
535 __le16 mblk_threshold;
536 __le16 threshold;
537 __le16 timeout;
538 u8 queue_type;
539 u8 reserved;
540} __packed;
541
542
543struct wl1271_acx_bet_enable {
544 struct acx_header header;
545
546 u8 role_id;
547 u8 enable;
548 u8 max_consecutive;
549 u8 padding[1];
550} __packed;
551
552#define ACX_IPV4_VERSION 4
553#define ACX_IPV6_VERSION 6
554#define ACX_IPV4_ADDR_SIZE 4
555
556
557#define ACX_ARP_FILTER_ARP_FILTERING BIT(0)
558#define ACX_ARP_FILTER_AUTO_ARP BIT(1)
559
560struct wl1271_acx_arp_filter {
561 struct acx_header header;
562 u8 role_id;
563 u8 version;
564 u8 enable;
565 u8 padding[1];
566 u8 address[16];
567
568
569
570} __packed;
571
572struct wl1271_acx_pm_config {
573 struct acx_header header;
574
575 __le32 host_clk_settling_time;
576 u8 host_fast_wakeup_support;
577 u8 padding[3];
578} __packed;
579
580struct wl1271_acx_keep_alive_mode {
581 struct acx_header header;
582
583 u8 role_id;
584 u8 enabled;
585 u8 padding[2];
586} __packed;
587
588enum {
589 ACX_KEEP_ALIVE_NO_TX = 0,
590 ACX_KEEP_ALIVE_PERIOD_ONLY
591};
592
593enum {
594 ACX_KEEP_ALIVE_TPL_INVALID = 0,
595 ACX_KEEP_ALIVE_TPL_VALID
596};
597
598struct wl1271_acx_keep_alive_config {
599 struct acx_header header;
600
601 u8 role_id;
602 u8 index;
603 u8 tpl_validation;
604 u8 trigger;
605 __le32 period;
606} __packed;
607
608
609#define HOST_IF_CFG_RX_FIFO_ENABLE BIT(0)
610#define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1)
611#define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3)
612#define HOST_IF_CFG_RX_PAD_TO_SDIO_BLK BIT(4)
613#define HOST_IF_CFG_ADD_RX_ALIGNMENT BIT(6)
614
615enum {
616 WL1271_ACX_TRIG_TYPE_LEVEL = 0,
617 WL1271_ACX_TRIG_TYPE_EDGE,
618};
619
620enum {
621 WL1271_ACX_TRIG_DIR_LOW = 0,
622 WL1271_ACX_TRIG_DIR_HIGH,
623 WL1271_ACX_TRIG_DIR_BIDIR,
624};
625
626enum {
627 WL1271_ACX_TRIG_ENABLE = 1,
628 WL1271_ACX_TRIG_DISABLE,
629};
630
631enum {
632 WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0,
633 WL1271_ACX_TRIG_METRIC_RSSI_DATA,
634 WL1271_ACX_TRIG_METRIC_SNR_BEACON,
635 WL1271_ACX_TRIG_METRIC_SNR_DATA,
636};
637
638enum {
639 WL1271_ACX_TRIG_IDX_RSSI = 0,
640 WL1271_ACX_TRIG_COUNT = 8,
641};
642
643struct wl1271_acx_rssi_snr_trigger {
644 struct acx_header header;
645
646 u8 role_id;
647 u8 metric;
648 u8 type;
649 u8 dir;
650 __le16 threshold;
651 __le16 pacing;
652 u8 hysteresis;
653 u8 index;
654 u8 enable;
655 u8 padding[1];
656};
657
658struct wl1271_acx_rssi_snr_avg_weights {
659 struct acx_header header;
660
661 u8 role_id;
662 u8 padding[3];
663 u8 rssi_beacon;
664 u8 rssi_data;
665 u8 snr_beacon;
666 u8 snr_data;
667};
668
669
670
671#define WL12XX_HT_CAP_HT_OPERATION BIT(16)
672
673
674
675
676
677
678struct wl1271_acx_ht_capabilities {
679 struct acx_header header;
680
681
682 __le32 ht_capabilites;
683
684
685 u8 hlid;
686
687
688
689
690
691 u8 ampdu_max_length;
692
693
694 u8 ampdu_min_spacing;
695
696 u8 padding;
697} __packed;
698
699
700
701
702
703struct wl1271_acx_ht_information {
704 struct acx_header header;
705
706 u8 role_id;
707
708
709 u8 rifs_mode;
710
711
712 u8 ht_protection;
713
714
715 u8 gf_protection;
716
717
718 u8 ht_tx_burst_limit;
719
720
721
722
723
724
725
726
727 u8 dual_cts_protection;
728
729 u8 padding[2];
730} __packed;
731
732struct wl1271_acx_ba_initiator_policy {
733 struct acx_header header;
734
735
736 u8 role_id;
737
738
739
740
741
742 u8 tid_bitmap;
743
744
745 u8 win_size;
746
747 u8 padding1[1];
748
749
750 u16 inactivity_timeout;
751
752 u8 padding[2];
753} __packed;
754
755struct wl1271_acx_ba_receiver_setup {
756 struct acx_header header;
757
758
759 u8 hlid;
760
761 u8 tid;
762
763 u8 enable;
764
765
766 u8 win_size;
767
768
769 u16 ssn;
770
771 u8 padding[2];
772} __packed;
773
774struct wl12xx_acx_fw_tsf_information {
775 struct acx_header header;
776
777 u8 role_id;
778 u8 padding1[3];
779 __le32 current_tsf_high;
780 __le32 current_tsf_low;
781 __le32 last_bttt_high;
782 __le32 last_tbtt_low;
783 u8 last_dtim_count;
784 u8 padding2[3];
785} __packed;
786
787struct wl1271_acx_ps_rx_streaming {
788 struct acx_header header;
789
790 u8 role_id;
791 u8 tid;
792 u8 enable;
793
794
795 u8 period;
796
797
798 u8 timeout;
799 u8 padding[3];
800} __packed;
801
802struct wl1271_acx_ap_max_tx_retry {
803 struct acx_header header;
804
805 u8 role_id;
806 u8 padding_1;
807
808
809
810
811
812 __le16 max_tx_retry;
813} __packed;
814
815struct wl1271_acx_config_ps {
816 struct acx_header header;
817
818 u8 exit_retries;
819 u8 enter_retries;
820 u8 padding[2];
821 __le32 null_data_rate;
822} __packed;
823
824struct wl1271_acx_inconnection_sta {
825 struct acx_header header;
826
827 u8 addr[ETH_ALEN];
828 u8 role_id;
829 u8 padding;
830} __packed;
831
832
833
834
835
836struct wl1271_acx_fm_coex {
837 struct acx_header header;
838
839 u8 enable;
840
841
842
843
844 u8 swallow_period;
845
846
847
848
849 u8 n_divider_fref_set_1;
850
851
852
853
854 u8 n_divider_fref_set_2;
855
856
857
858
859 __le16 m_divider_fref_set_1;
860
861
862
863
864 __le16 m_divider_fref_set_2;
865
866
867
868
869 __le32 coex_pll_stabilization_time;
870
871
872
873
874 __le16 ldo_stabilization_time;
875
876
877
878
879
880
881
882
883 u8 fm_disturbed_band_margin;
884
885
886
887
888 u8 swallow_clk_diff;
889} __packed;
890
891#define ACX_RATE_MGMT_ALL_PARAMS 0xff
892struct wl12xx_acx_set_rate_mgmt_params {
893 struct acx_header header;
894
895 u8 index;
896 u8 padding1;
897 __le16 rate_retry_score;
898 __le16 per_add;
899 __le16 per_th1;
900 __le16 per_th2;
901 __le16 max_per;
902 u8 inverse_curiosity_factor;
903 u8 tx_fail_low_th;
904 u8 tx_fail_high_th;
905 u8 per_alpha_shift;
906 u8 per_add_shift;
907 u8 per_beta1_shift;
908 u8 per_beta2_shift;
909 u8 rate_check_up;
910 u8 rate_check_down;
911 u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES];
912 u8 padding2[2];
913} __packed;
914
915struct wl12xx_acx_config_hangover {
916 struct acx_header header;
917
918 __le32 recover_time;
919 u8 hangover_period;
920 u8 dynamic_mode;
921 u8 early_termination_mode;
922 u8 max_period;
923 u8 min_period;
924 u8 increase_delta;
925 u8 decrease_delta;
926 u8 quiet_time;
927 u8 increase_time;
928 u8 window_size;
929 u8 padding[2];
930} __packed;
931
932
933struct acx_default_rx_filter {
934 struct acx_header header;
935 u8 enable;
936
937
938 u8 default_action;
939
940 u8 pad[2];
941} __packed;
942
943
944struct acx_rx_filter_cfg {
945 struct acx_header header;
946
947 u8 enable;
948
949
950 u8 index;
951
952 u8 action;
953
954 u8 num_fields;
955 u8 fields[0];
956} __packed;
957
958struct acx_roaming_stats {
959 struct acx_header header;
960
961 u8 role_id;
962 u8 pad[3];
963 u32 missed_beacons;
964 u8 snr_data;
965 u8 snr_bacon;
966 s8 rssi_data;
967 s8 rssi_beacon;
968} __packed;
969
970enum {
971 ACX_WAKE_UP_CONDITIONS = 0x0000,
972 ACX_MEM_CFG = 0x0001,
973 ACX_SLOT = 0x0002,
974 ACX_AC_CFG = 0x0003,
975 ACX_MEM_MAP = 0x0004,
976 ACX_AID = 0x0005,
977 ACX_MEDIUM_USAGE = 0x0006,
978 ACX_STATISTICS = 0x0007,
979 ACX_PWR_CONSUMPTION_STATISTICS = 0x0008,
980 ACX_TID_CFG = 0x0009,
981 ACX_PS_RX_STREAMING = 0x000A,
982 ACX_BEACON_FILTER_OPT = 0x000B,
983 ACX_NOISE_HIST = 0x000C,
984 ACX_HDK_VERSION = 0x000D,
985 ACX_PD_THRESHOLD = 0x000E,
986 ACX_TX_CONFIG_OPT = 0x000F,
987 ACX_CCA_THRESHOLD = 0x0010,
988 ACX_EVENT_MBOX_MASK = 0x0011,
989 ACX_CONN_MONIT_PARAMS = 0x0012,
990 ACX_DISABLE_BROADCASTS = 0x0013,
991 ACX_BCN_DTIM_OPTIONS = 0x0014,
992 ACX_SG_ENABLE = 0x0015,
993 ACX_SG_CFG = 0x0016,
994 ACX_FM_COEX_CFG = 0x0017,
995 ACX_BEACON_FILTER_TABLE = 0x0018,
996 ACX_ARP_IP_FILTER = 0x0019,
997 ACX_ROAMING_STATISTICS_TBL = 0x001A,
998 ACX_RATE_POLICY = 0x001B,
999 ACX_CTS_PROTECTION = 0x001C,
1000 ACX_SLEEP_AUTH = 0x001D,
1001 ACX_PREAMBLE_TYPE = 0x001E,
1002 ACX_ERROR_CNT = 0x001F,
1003 ACX_IBSS_FILTER = 0x0020,
1004 ACX_SERVICE_PERIOD_TIMEOUT = 0x0021,
1005 ACX_TSF_INFO = 0x0022,
1006 ACX_CONFIG_PS_WMM = 0x0023,
1007 ACX_ENABLE_RX_DATA_FILTER = 0x0024,
1008 ACX_SET_RX_DATA_FILTER = 0x0025,
1009 ACX_GET_DATA_FILTER_STATISTICS = 0x0026,
1010 ACX_RX_CONFIG_OPT = 0x0027,
1011 ACX_FRAG_CFG = 0x0028,
1012 ACX_BET_ENABLE = 0x0029,
1013 ACX_RSSI_SNR_TRIGGER = 0x002A,
1014 ACX_RSSI_SNR_WEIGHTS = 0x002B,
1015 ACX_KEEP_ALIVE_MODE = 0x002C,
1016 ACX_SET_KEEP_ALIVE_CONFIG = 0x002D,
1017 ACX_BA_SESSION_INIT_POLICY = 0x002E,
1018 ACX_BA_SESSION_RX_SETUP = 0x002F,
1019 ACX_PEER_HT_CAP = 0x0030,
1020 ACX_HT_BSS_OPERATION = 0x0031,
1021 ACX_COEX_ACTIVITY = 0x0032,
1022 ACX_BURST_MODE = 0x0033,
1023 ACX_SET_RATE_MGMT_PARAMS = 0x0034,
1024 ACX_GET_RATE_MGMT_PARAMS = 0x0035,
1025 ACX_SET_RATE_ADAPT_PARAMS = 0x0036,
1026 ACX_SET_DCO_ITRIM_PARAMS = 0x0037,
1027 ACX_GEN_FW_CMD = 0x0038,
1028 ACX_HOST_IF_CFG_BITMAP = 0x0039,
1029 ACX_MAX_TX_FAILURE = 0x003A,
1030 ACX_UPDATE_INCONNECTION_STA_LIST = 0x003B,
1031 DOT11_RX_MSDU_LIFE_TIME = 0x003C,
1032 DOT11_CUR_TX_PWR = 0x003D,
1033 DOT11_RTS_THRESHOLD = 0x003E,
1034 DOT11_GROUP_ADDRESS_TBL = 0x003F,
1035 ACX_PM_CONFIG = 0x0040,
1036 ACX_CONFIG_PS = 0x0041,
1037 ACX_CONFIG_HANGOVER = 0x0042,
1038 ACX_FEATURE_CFG = 0x0043,
1039 ACX_PROTECTION_CFG = 0x0044,
1040};
1041
1042
1043int wl1271_acx_wake_up_conditions(struct wl1271 *wl,
1044 struct wl12xx_vif *wlvif,
1045 u8 wake_up_event, u8 listen_interval);
1046int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1047int wl1271_acx_tx_power(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1048 int power);
1049int wl1271_acx_feature_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1050int wl1271_acx_mem_map(struct wl1271 *wl,
1051 struct acx_header *mem_map, size_t len);
1052int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
1053int wl1271_acx_slot(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1054 enum acx_slot_type slot_time);
1055int wl1271_acx_group_address_tbl(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1056 bool enable, void *mc_list, u32 mc_list_len);
1057int wl1271_acx_service_period_timeout(struct wl1271 *wl,
1058 struct wl12xx_vif *wlvif);
1059int wl1271_acx_rts_threshold(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1060 u32 rts_threshold);
1061int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
1062int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1063 bool enable_filter);
1064int wl1271_acx_beacon_filter_table(struct wl1271 *wl,
1065 struct wl12xx_vif *wlvif);
1066int wl1271_acx_conn_monit_params(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1067 bool enable);
1068int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable);
1069int wl12xx_acx_sg_cfg(struct wl1271 *wl);
1070int wl1271_acx_cca_threshold(struct wl1271 *wl);
1071int wl1271_acx_bcn_dtim_options(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1072int wl1271_acx_aid(struct wl1271 *wl, struct wl12xx_vif *wlvif, u16 aid);
1073int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1074int wl1271_acx_set_preamble(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1075 enum acx_preamble_type preamble);
1076int wl1271_acx_cts_protect(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1077 enum acx_ctsprotect_type ctsprotect);
1078int wl1271_acx_statistics(struct wl1271 *wl, void *stats);
1079int wl1271_acx_sta_rate_policies(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1080int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c,
1081 u8 idx);
1082int wl1271_acx_ac_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1083 u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop);
1084int wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1085 u8 queue_id, u8 channel_type,
1086 u8 tsid, u8 ps_scheme, u8 ack_policy,
1087 u32 apsd_conf0, u32 apsd_conf1);
1088int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold);
1089int wl1271_acx_tx_config_options(struct wl1271 *wl);
1090int wl12xx_acx_mem_cfg(struct wl1271 *wl);
1091int wl1271_acx_init_mem_config(struct wl1271 *wl);
1092int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1093int wl1271_acx_smart_reflex(struct wl1271 *wl);
1094int wl1271_acx_bet_enable(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1095 bool enable);
1096int wl1271_acx_arp_ip_filter(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1097 u8 enable, __be32 address);
1098int wl1271_acx_pm_config(struct wl1271 *wl);
1099int wl1271_acx_keep_alive_mode(struct wl1271 *wl, struct wl12xx_vif *vif,
1100 bool enable);
1101int wl1271_acx_keep_alive_config(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1102 u8 index, u8 tpl_valid);
1103int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1104 bool enable, s16 thold, u8 hyst);
1105int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl,
1106 struct wl12xx_vif *wlvif);
1107int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
1108 struct ieee80211_sta_ht_cap *ht_cap,
1109 bool allow_ht_operation, u8 hlid);
1110int wl1271_acx_set_ht_information(struct wl1271 *wl,
1111 struct wl12xx_vif *wlvif,
1112 u16 ht_operation_mode);
1113int wl12xx_acx_set_ba_initiator_policy(struct wl1271 *wl,
1114 struct wl12xx_vif *wlvif);
1115int wl12xx_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index,
1116 u16 ssn, bool enable, u8 peer_hlid,
1117 u8 win_size);
1118int wl12xx_acx_tsf_info(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1119 u64 *mactime);
1120int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1121 bool enable);
1122int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1123int wl12xx_acx_config_ps(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1124int wl1271_acx_set_inconnection_sta(struct wl1271 *wl,
1125 struct wl12xx_vif *wlvif, u8 *addr);
1126int wl1271_acx_fm_coex(struct wl1271 *wl);
1127int wl12xx_acx_set_rate_mgmt_params(struct wl1271 *wl);
1128int wl12xx_acx_config_hangover(struct wl1271 *wl);
1129int wlcore_acx_average_rssi(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1130 s8 *avg_rssi);
1131
1132#ifdef CONFIG_PM
1133int wl1271_acx_default_rx_filter_enable(struct wl1271 *wl, bool enable,
1134 enum rx_filter_action action);
1135int wl1271_acx_set_rx_filter(struct wl1271 *wl, u8 index, bool enable,
1136 struct wl12xx_rx_filter *filter);
1137#endif
1138#endif
1139