LXR linux/drivers/net/wireless/zydas/zd1211rw/zd_rf

   1/* ZD1211 USB-WLAN driver for Linux
   2 *
   3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
   4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include <linux/kernel.h>
  21
  22#include "zd_rf.h"
  23#include "zd_usb.h"
  24#include "zd_chip.h"
  25
  26static const u32 rf2959_table[][2] = {
  27        RF_CHANNEL( 1) = { 0x181979, 0x1e6666 },
  28        RF_CHANNEL( 2) = { 0x181989, 0x1e6666 },
  29        RF_CHANNEL( 3) = { 0x181999, 0x1e6666 },
  30        RF_CHANNEL( 4) = { 0x1819a9, 0x1e6666 },
  31        RF_CHANNEL( 5) = { 0x1819b9, 0x1e6666 },
  32        RF_CHANNEL( 6) = { 0x1819c9, 0x1e6666 },
  33        RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 },
  34        RF_CHANNEL( 8) = { 0x1819e9, 0x1e6666 },
  35        RF_CHANNEL( 9) = { 0x1819f9, 0x1e6666 },
  36        RF_CHANNEL(10) = { 0x181a09, 0x1e6666 },
  37        RF_CHANNEL(11) = { 0x181a19, 0x1e6666 },
  38        RF_CHANNEL(12) = { 0x181a29, 0x1e6666 },
  39        RF_CHANNEL(13) = { 0x181a39, 0x1e6666 },
  40        RF_CHANNEL(14) = { 0x181a60, 0x1c0000 },
  41};
  42
  43#if 0
  44static int bits(u32 rw, int from, int to)
  45{
  46        rw &= ~(0xffffffffU << (to+1));
  47        rw >>= from;
  48        return rw;
  49}
  50
  51static int bit(u32 rw, int bit)
  52{
  53        return bits(rw, bit, bit);
  54}
  55
  56static void dump_regwrite(u32 rw)
  57{
  58        int reg = bits(rw, 18, 22);
  59        int rw_flag = bits(rw, 23, 23);
  60        PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
  61
  62        switch (reg) {
  63        case 0:
  64                PDEBUG("reg0 CFG1 ref_sel %d hybernate %d rf_vco_reg_en %d"
  65                       " if_vco_reg_en %d if_vga_en %d",
  66                       bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
  67                       bit(rw, 0));
  68                break;
  69        case 1:
  70                PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d"
  71                       " cpl1 %d pdp1 %d autocal_en1 %d ld_en1 %d ifloopr %d"
  72                       " ifloopc %d dac1 %d",
  73                       bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
  74                       bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
  75                       bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
  76                break;
  77        case 2:
  78                PDEBUG("reg2 IFPLL2 n1 %d num1 %d",
  79                       bits(rw, 6, 17), bits(rw, 0, 5));
  80                break;
  81        case 3:
  82                PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
  83                break;
  84        case 4:
  85                PDEBUG("reg4 IFPLL4 dn1 %#04x ct_def1 %d kv_def1 %d",
  86                       bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
  87                break;
  88        case 5:
  89                PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d"
  90                       " pdp %d autocal_en %d ld_en %d rfloopr %d rfloopc %d"
  91                       " dac %d",
  92                       bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
  93                       bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
  94                       bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
  95                break;
  96        case 6:
  97                PDEBUG("reg6 RFPLL2 n %d num %d",
  98                       bits(rw, 6, 17), bits(rw, 0, 5));
  99                break;
 100        case 7:
 101                PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
 102                break;
 103        case 8:
 104                PDEBUG("reg8 RFPLL4 dn %#06x ct_def %d kv_def %d",
 105                       bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
 106                break;
 107        case 9:
 108                PDEBUG("reg9 CAL1 tvco %d tlock %d m_ct_value %d ld_window %d",
 109                       bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
 110                       bits(rw, 0, 2));
 111                break;
 112        case 10:
 113                PDEBUG("reg10 TXRX1 rxdcfbbyps %d pcontrol %d txvgc %d"
 114                       " rxlpfbw %d txlpfbw %d txdiffmode %d txenmode %d"
 115                       " intbiasen %d tybypass %d",
 116                       bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
 117                       bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
 118                       bit(rw, 1), bit(rw, 0));
 119                break;
 120        case 11:
 121                PDEBUG("reg11 PCNT1 mid_bias %d p_desired %d pc_offset %d"
 122                        " tx_delay %d",
 123                        bits(rw, 15, 17), bits(rw, 9, 14), bits(rw, 3, 8),
 124                        bits(rw, 0, 2));
 125                break;
 126        case 12:
 127                PDEBUG("reg12 PCNT2 max_power %d mid_power %d min_power %d",
 128                       bits(rw, 12, 17), bits(rw, 6, 11), bits(rw, 0, 5));
 129                break;
 130        case 13:
 131                PDEBUG("reg13 VCOT1 rfpll vco comp %d ifpll vco comp %d"
 132                       " lobias %d if_biasbuf %d if_biasvco %d rf_biasbuf %d"
 133                       " rf_biasvco %d",
 134                       bit(rw, 17), bit(rw, 16), bit(rw, 15),
 135                       bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),
 136                       bits(rw, 0, 2));
 137                break;
 138        case 14:
 139                PDEBUG("reg14 IQCAL rx_acal %d rx_pcal %d"
 140                       " tx_acal %d tx_pcal %d",
 141                       bits(rw, 13, 17), bits(rw, 9, 12), bits(rw, 4, 8),
 142                       bits(rw, 0, 3));
 143                break;
 144        }
 145}
 146#endif /* 0 */
 147
 148static int rf2959_init_hw(struct zd_rf *rf)
 149{
 150        int r;
 151        struct zd_chip *chip = zd_rf_to_chip(rf);
 152
 153        static const struct zd_ioreq16 ioreqs[] = {
 154                { ZD_CR2,   0x1E }, { ZD_CR9,   0x20 }, { ZD_CR10,  0x89 },
 155                { ZD_CR11,  0x00 }, { ZD_CR15,  0xD0 }, { ZD_CR17,  0x68 },
 156                { ZD_CR19,  0x4a }, { ZD_CR20,  0x0c }, { ZD_CR21,  0x0E },
 157                { ZD_CR23,  0x48 },
 158                /* normal size for cca threshold */
 159                { ZD_CR24,  0x14 },
 160                /* { ZD_CR24,  0x20 }, */
 161                { ZD_CR26,  0x90 }, { ZD_CR27,  0x30 }, { ZD_CR29,  0x20 },
 162                { ZD_CR31,  0xb2 }, { ZD_CR32,  0x43 }, { ZD_CR33,  0x28 },
 163                { ZD_CR38,  0x30 }, { ZD_CR34,  0x0f }, { ZD_CR35,  0xF0 },
 164                { ZD_CR41,  0x2a }, { ZD_CR46,  0x7F }, { ZD_CR47,  0x1E },
 165                { ZD_CR51,  0xc5 }, { ZD_CR52,  0xc5 }, { ZD_CR53,  0xc5 },
 166                { ZD_CR79,  0x58 }, { ZD_CR80,  0x30 }, { ZD_CR81,  0x30 },
 167                { ZD_CR82,  0x00 }, { ZD_CR83,  0x24 }, { ZD_CR84,  0x04 },
 168                { ZD_CR85,  0x00 }, { ZD_CR86,  0x10 }, { ZD_CR87,  0x2A },
 169                { ZD_CR88,  0x10 }, { ZD_CR89,  0x24 }, { ZD_CR90,  0x18 },
 170                /* { ZD_CR91,  0x18 }, */
 171                /* should solve continuous CTS frame problems */
 172                { ZD_CR91,  0x00 },
 173                { ZD_CR92,  0x0a }, { ZD_CR93,  0x00 }, { ZD_CR94,  0x01 },
 174                { ZD_CR95,  0x00 }, { ZD_CR96,  0x40 }, { ZD_CR97,  0x37 },
 175                { ZD_CR98,  0x05 }, { ZD_CR99,  0x28 }, { ZD_CR100, 0x00 },
 176                { ZD_CR101, 0x13 }, { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 },
 177                { ZD_CR104, 0x18 }, { ZD_CR105, 0x12 },
 178                /* normal size */
 179                { ZD_CR106, 0x1a },
 180                /* { ZD_CR106, 0x22 }, */
 181                { ZD_CR107, 0x24 }, { ZD_CR108, 0x0a }, { ZD_CR109, 0x13 },
 182                { ZD_CR110, 0x2F }, { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 },
 183                { ZD_CR113, 0x27 }, { ZD_CR114, 0x27 }, { ZD_CR115, 0x40 },
 184                { ZD_CR116, 0x40 }, { ZD_CR117, 0xF0 }, { ZD_CR118, 0xF0 },
 185                { ZD_CR119, 0x16 },
 186                /* no TX continuation */
 187                { ZD_CR122, 0x00 },
 188                /* { ZD_CR122, 0xff }, */
 189                { ZD_CR127, 0x03 }, { ZD_CR131, 0x08 }, { ZD_CR138, 0x28 },
 190                { ZD_CR148, 0x44 }, { ZD_CR150, 0x10 }, { ZD_CR169, 0xBB },
 191                { ZD_CR170, 0xBB },
 192        };
 193
 194        static const u32 rv[] = {
 195                0x000007,  /* REG0(CFG1) */
 196                0x07dd43,  /* REG1(IFPLL1) */
 197                0x080959,  /* REG2(IFPLL2) */
 198                0x0e6666,
 199                0x116a57,  /* REG4 */
 200                0x17dd43,  /* REG5 */
 201                0x1819f9,  /* REG6 */
 202                0x1e6666,
 203                0x214554,
 204                0x25e7fa,
 205                0x27fffa,
 206                /* The Zydas driver somehow forgets to set this value. It's
 207                 * only set for Japan. We are using internal power control
 208                 * for now.
 209                 */
 210                0x294128, /* internal power */
 211                /* 0x28252c, */ /* External control TX power */
 212                /* ZD_CR31_CCK, ZD_CR51_6-36M, ZD_CR52_48M, ZD_CR53_54M */
 213                0x2c0000,
 214                0x300000,
 215                0x340000,  /* REG13(0xD) */
 216                0x381e0f,  /* REG14(0xE) */
 217                /* Bogus, RF2959's data sheet doesn't know register 27, which is
 218                 * actually referenced here. The commented 0x11 is 17.
 219                 */
 220                0x6c180f,  /* REG27(0x11) */
 221        };
 222
 223        r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 224        if (r)
 225                return r;
 226
 227        return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
 228}
 229
 230static int rf2959_set_channel(struct zd_rf *rf, u8 channel)
 231{
 232        int i, r;
 233        const u32 *rv = rf2959_table[channel-1];
 234        struct zd_chip *chip = zd_rf_to_chip(rf);
 235
 236        for (i = 0; i < 2; i++) {
 237                r = zd_rfwrite_locked(chip, rv[i], RF_RV_BITS);
 238                if (r)
 239                        return r;
 240        }
 241        return 0;
 242}
 243
 244static int rf2959_switch_radio_on(struct zd_rf *rf)
 245{
 246        static const struct zd_ioreq16 ioreqs[] = {
 247                { ZD_CR10, 0x89 },
 248                { ZD_CR11, 0x00 },
 249        };
 250        struct zd_chip *chip = zd_rf_to_chip(rf);
 251
 252        return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 253}
 254
 255static int rf2959_switch_radio_off(struct zd_rf *rf)
 256{
 257        static const struct zd_ioreq16 ioreqs[] = {
 258                { ZD_CR10, 0x15 },
 259                { ZD_CR11, 0x81 },
 260        };
 261        struct zd_chip *chip = zd_rf_to_chip(rf);
 262
 263        return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 264}
 265
 266int zd_rf_init_rf2959(struct zd_rf *rf)
 267{
 268        struct zd_chip *chip = zd_rf_to_chip(rf);
 269
 270        if (zd_chip_is_zd1211b(chip)) {
 271                dev_err(zd_chip_dev(chip),
 272                       "RF2959 is currently not supported for ZD1211B"
 273                       " devices\n");
 274                return -ENODEV;
 275        }
 276        rf->init_hw = rf2959_init_hw;
 277        rf->set_channel = rf2959_set_channel;
 278        rf->switch_radio_on = rf2959_switch_radio_on;
 279        rf->switch_radio_off = rf2959_switch_radio_off;
 280        return 0;
 281}
 282