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131#include <linux/types.h>
132#include <linux/kernel.h>
133#include <linux/spinlock.h>
134#include <linux/pci.h>
135#include <linux/init.h>
136#include <linux/slab.h>
137#include <linux/interrupt.h>
138
139#include <asm/byteorder.h>
140#include <asm/pdc.h>
141#include <asm/pdcpat.h>
142#include <asm/page.h>
143#include <asm/io.h>
144#ifdef CONFIG_SUPERIO
145#include <asm/superio.h>
146#endif
147
148#include <asm/ropes.h>
149#include "iosapic_private.h"
150
151#define MODULE_NAME "iosapic"
152
153
154#undef PCI_BRIDGE_FUNCS
155#undef DEBUG_IOSAPIC
156#undef DEBUG_IOSAPIC_IRT
157
158
159#ifdef DEBUG_IOSAPIC
160#define DBG(x...) printk(x)
161#else
162#define DBG(x...)
163#endif
164
165#ifdef DEBUG_IOSAPIC_IRT
166#define DBG_IRT(x...) printk(x)
167#else
168#define DBG_IRT(x...)
169#endif
170
171#ifdef CONFIG_64BIT
172#define COMPARE_IRTE_ADDR(irte, hpa) ((irte)->dest_iosapic_addr == (hpa))
173#else
174#define COMPARE_IRTE_ADDR(irte, hpa) \
175 ((irte)->dest_iosapic_addr == ((hpa) | 0xffffffff00000000ULL))
176#endif
177
178#define IOSAPIC_REG_SELECT 0x00
179#define IOSAPIC_REG_WINDOW 0x10
180#define IOSAPIC_REG_EOI 0x40
181
182#define IOSAPIC_REG_VERSION 0x1
183
184#define IOSAPIC_IRDT_ENTRY(idx) (0x10+(idx)*2)
185#define IOSAPIC_IRDT_ENTRY_HI(idx) (0x11+(idx)*2)
186
187static inline unsigned int iosapic_read(void __iomem *iosapic, unsigned int reg)
188{
189 writel(reg, iosapic + IOSAPIC_REG_SELECT);
190 return readl(iosapic + IOSAPIC_REG_WINDOW);
191}
192
193static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 val)
194{
195 writel(reg, iosapic + IOSAPIC_REG_SELECT);
196 writel(val, iosapic + IOSAPIC_REG_WINDOW);
197}
198
199#define IOSAPIC_VERSION_MASK 0x000000ff
200#define IOSAPIC_VERSION(ver) ((int) (ver & IOSAPIC_VERSION_MASK))
201
202#define IOSAPIC_MAX_ENTRY_MASK 0x00ff0000
203#define IOSAPIC_MAX_ENTRY_SHIFT 0x10
204#define IOSAPIC_IRDT_MAX_ENTRY(ver) \
205 (int) (((ver) & IOSAPIC_MAX_ENTRY_MASK) >> IOSAPIC_MAX_ENTRY_SHIFT)
206
207
208#define IOSAPIC_IRDT_ENABLE 0x10000
209#define IOSAPIC_IRDT_PO_LOW 0x02000
210#define IOSAPIC_IRDT_LEVEL_TRIG 0x08000
211#define IOSAPIC_IRDT_MODE_LPRI 0x00100
212
213
214#define IOSAPIC_IRDT_ID_EID_SHIFT 0x10
215
216
217static DEFINE_SPINLOCK(iosapic_lock);
218
219static inline void iosapic_eoi(void __iomem *addr, unsigned int data)
220{
221 __raw_writel(data, addr);
222}
223
224
225
226
227
228
229
230
231
232
233static struct irt_entry *irt_cell;
234static size_t irt_num_entry;
235
236static struct irt_entry *iosapic_alloc_irt(int num_entries)
237{
238 unsigned long a;
239
240
241
242
243
244
245 a = (unsigned long)kmalloc(sizeof(struct irt_entry) * num_entries + 8, GFP_KERNEL);
246 a = (a + 7UL) & ~7UL;
247 return (struct irt_entry *)a;
248}
249
250
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275
276
277static int __init
278iosapic_load_irt(unsigned long cell_num, struct irt_entry **irt)
279{
280 long status;
281 struct irt_entry *table;
282 unsigned long num_entries = 0UL;
283
284 BUG_ON(!irt);
285
286 if (is_pdc_pat()) {
287
288 DBG("calling get_irt_size (cell %ld)\n", cell_num);
289 status = pdc_pat_get_irt_size(&num_entries, cell_num);
290 DBG("get_irt_size: %ld\n", status);
291
292 BUG_ON(status != PDC_OK);
293 BUG_ON(num_entries == 0);
294
295
296
297
298
299
300
301 table = iosapic_alloc_irt(num_entries);
302 if (table == NULL) {
303 printk(KERN_WARNING MODULE_NAME ": read_irt : can "
304 "not alloc mem for IRT\n");
305 return 0;
306 }
307
308
309 status = pdc_pat_get_irt(table, cell_num);
310 DBG("pdc_pat_get_irt: %ld\n", status);
311 WARN_ON(status != PDC_OK);
312 } else {
313
314
315
316
317
318 if (irt_cell)
319 return 0;
320
321
322 status = pdc_pci_irt_size(&num_entries, 0);
323 DBG("pdc_pci_irt_size: %ld\n", status);
324
325 if (status != PDC_OK) {
326
327 return 0;
328 }
329
330 BUG_ON(num_entries == 0);
331
332 table = iosapic_alloc_irt(num_entries);
333 if (!table) {
334 printk(KERN_WARNING MODULE_NAME ": read_irt : can "
335 "not alloc mem for IRT\n");
336 return 0;
337 }
338
339
340 status = pdc_pci_irt(num_entries, 0, table);
341 BUG_ON(status != PDC_OK);
342 }
343
344
345 *irt = table;
346
347#ifdef DEBUG_IOSAPIC_IRT
348{
349 struct irt_entry *p = table;
350 int i;
351
352 printk(MODULE_NAME " Interrupt Routing Table (cell %ld)\n", cell_num);
353 printk(MODULE_NAME " start = 0x%p num_entries %ld entry_size %d\n",
354 table,
355 num_entries,
356 (int) sizeof(struct irt_entry));
357
358 for (i = 0 ; i < num_entries ; i++, p++) {
359 printk(MODULE_NAME " %02x %02x %02x %02x %02x %02x %02x %02x %08x%08x\n",
360 p->entry_type, p->entry_length, p->interrupt_type,
361 p->polarity_trigger, p->src_bus_irq_devno, p->src_bus_id,
362 p->src_seg_id, p->dest_iosapic_intin,
363 ((u32 *) p)[2],
364 ((u32 *) p)[3]
365 );
366 }
367}
368#endif
369
370 return num_entries;
371}
372
373
374
375void __init iosapic_init(void)
376{
377 unsigned long cell = 0;
378
379 DBG("iosapic_init()\n");
380
381#ifdef __LP64__
382 if (is_pdc_pat()) {
383 int status;
384 struct pdc_pat_cell_num cell_info;
385
386 status = pdc_pat_cell_get_number(&cell_info);
387 if (status == PDC_OK) {
388 cell = cell_info.cell_num;
389 }
390 }
391#endif
392
393
394 irt_num_entry = iosapic_load_irt(cell, &irt_cell);
395 if (irt_num_entry == 0)
396 irt_cell = NULL;
397}
398
399
400
401
402
403static struct irt_entry *
404irt_find_irqline(struct iosapic_info *isi, u8 slot, u8 intr_pin)
405{
406 struct irt_entry *i = irt_cell;
407 int cnt;
408 u8 irq_devno = (slot << IRT_DEV_SHIFT) | (intr_pin-1);
409
410 DBG_IRT("irt_find_irqline() SLOT %d pin %d\n", slot, intr_pin);
411
412 for (cnt=0; cnt < irt_num_entry; cnt++, i++) {
413
414
415
416
417
418
419
420
421 if (i->entry_type != IRT_IOSAPIC_TYPE) {
422 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d type %d\n", i, cnt, i->entry_type);
423 continue;
424 }
425
426 if (i->entry_length != IRT_IOSAPIC_LENGTH) {
427 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d length %d\n", i, cnt, i->entry_length);
428 continue;
429 }
430
431 if (i->interrupt_type != IRT_VECTORED_INTR) {
432 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d interrupt_type %d\n", i, cnt, i->interrupt_type);
433 continue;
434 }
435
436 if (!COMPARE_IRTE_ADDR(i, isi->isi_hpa))
437 continue;
438
439 if ((i->src_bus_irq_devno & IRT_IRQ_DEVNO_MASK) != irq_devno)
440 continue;
441
442
443
444
445
446
447
448
449
450 return i;
451 }
452
453 printk(KERN_WARNING MODULE_NAME ": 0x%lx : no IRT entry for slot %d, pin %d\n",
454 isi->isi_hpa, slot, intr_pin);
455 return NULL;
456}
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473static struct irt_entry *
474iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev)
475{
476 u8 intr_pin, intr_slot;
477
478 pci_read_config_byte(pcidev, PCI_INTERRUPT_PIN, &intr_pin);
479
480 DBG_IRT("iosapic_xlate_pin(%s) SLOT %d pin %d\n",
481 pcidev->slot_name, PCI_SLOT(pcidev->devfn), intr_pin);
482
483 if (intr_pin == 0) {
484
485 return NULL;
486 }
487
488
489 if (pcidev->bus->parent) {
490
491
492
493#ifdef PCI_BRIDGE_FUNCS
494
495
496
497
498
499
500
501
502
503 if (pci_bridge_funcs->xlate_intr_line) {
504 intr_pin = pci_bridge_funcs->xlate_intr_line(pcidev);
505 }
506#else
507 struct pci_bus *p = pcidev->bus;
508
509
510
511
512
513
514
515
516
517
518
519
520
521 intr_pin = pci_swizzle_interrupt_pin(pcidev, intr_pin);
522#endif
523
524
525
526
527 while (p->parent->parent)
528 p = p->parent;
529
530 intr_slot = PCI_SLOT(p->self->devfn);
531 } else {
532 intr_slot = PCI_SLOT(pcidev->devfn);
533 }
534 DBG_IRT("iosapic_xlate_pin: bus %d slot %d pin %d\n",
535 pcidev->bus->busn_res.start, intr_slot, intr_pin);
536
537 return irt_find_irqline(isi, intr_slot, intr_pin);
538}
539
540static void iosapic_rd_irt_entry(struct vector_info *vi , u32 *dp0, u32 *dp1)
541{
542 struct iosapic_info *isp = vi->iosapic;
543 u8 idx = vi->irqline;
544
545 *dp0 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY(idx));
546 *dp1 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY_HI(idx));
547}
548
549
550static void iosapic_wr_irt_entry(struct vector_info *vi, u32 dp0, u32 dp1)
551{
552 struct iosapic_info *isp = vi->iosapic;
553
554 DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %lx 0x%x 0x%x\n",
555 vi->irqline, isp->isi_hpa, dp0, dp1);
556
557 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY(vi->irqline), dp0);
558
559
560 dp0 = readl(isp->addr+IOSAPIC_REG_WINDOW);
561
562 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY_HI(vi->irqline), dp1);
563
564
565 dp1 = readl(isp->addr+IOSAPIC_REG_WINDOW);
566}
567
568
569
570
571
572
573static void
574iosapic_set_irt_data( struct vector_info *vi, u32 *dp0, u32 *dp1)
575{
576 u32 mode = 0;
577 struct irt_entry *p = vi->irte;
578
579 if ((p->polarity_trigger & IRT_PO_MASK) == IRT_ACTIVE_LO)
580 mode |= IOSAPIC_IRDT_PO_LOW;
581
582 if (((p->polarity_trigger >> IRT_EL_SHIFT) & IRT_EL_MASK) == IRT_LEVEL_TRIG)
583 mode |= IOSAPIC_IRDT_LEVEL_TRIG;
584
585
586
587
588
589
590 *dp0 = mode | (u32) vi->txn_data;
591
592
593
594
595
596 if (is_pdc_pat()) {
597
598
599
600
601 *dp1 = (u32) (vi->txn_addr);
602 } else {
603
604
605
606
607
608
609
610 *dp1 = (((u32)vi->txn_addr & 0x0ff00000) >> 4) |
611 (((u32)vi->txn_addr & 0x000ff000) << 12);
612 }
613 DBG_IRT("iosapic_set_irt_data(): 0x%x 0x%x\n", *dp0, *dp1);
614}
615
616
617static void iosapic_mask_irq(struct irq_data *d)
618{
619 unsigned long flags;
620 struct vector_info *vi = irq_data_get_irq_chip_data(d);
621 u32 d0, d1;
622
623 spin_lock_irqsave(&iosapic_lock, flags);
624 iosapic_rd_irt_entry(vi, &d0, &d1);
625 d0 |= IOSAPIC_IRDT_ENABLE;
626 iosapic_wr_irt_entry(vi, d0, d1);
627 spin_unlock_irqrestore(&iosapic_lock, flags);
628}
629
630static void iosapic_unmask_irq(struct irq_data *d)
631{
632 struct vector_info *vi = irq_data_get_irq_chip_data(d);
633 u32 d0, d1;
634
635
636 WARN_ON(vi->txn_irq == 0);
637
638 iosapic_set_irt_data(vi, &d0, &d1);
639 iosapic_wr_irt_entry(vi, d0, d1);
640
641#ifdef DEBUG_IOSAPIC_IRT
642{
643 u32 *t = (u32 *) ((ulong) vi->eoi_addr & ~0xffUL);
644 printk("iosapic_enable_irq(): regs %p", vi->eoi_addr);
645 for ( ; t < vi->eoi_addr; t++)
646 printk(" %x", readl(t));
647 printk("\n");
648}
649
650printk("iosapic_enable_irq(): sel ");
651{
652 struct iosapic_info *isp = vi->iosapic;
653
654 for (d0=0x10; d0<0x1e; d0++) {
655 d1 = iosapic_read(isp->addr, d0);
656 printk(" %x", d1);
657 }
658}
659printk("\n");
660#endif
661
662
663
664
665
666
667
668 DBG(KERN_DEBUG "enable_irq(%d): eoi(%p, 0x%x)\n", d->irq,
669 vi->eoi_addr, vi->eoi_data);
670 iosapic_eoi(vi->eoi_addr, vi->eoi_data);
671}
672
673static void iosapic_eoi_irq(struct irq_data *d)
674{
675 struct vector_info *vi = irq_data_get_irq_chip_data(d);
676
677 iosapic_eoi(vi->eoi_addr, vi->eoi_data);
678 cpu_eoi_irq(d);
679}
680
681#ifdef CONFIG_SMP
682static int iosapic_set_affinity_irq(struct irq_data *d,
683 const struct cpumask *dest, bool force)
684{
685 struct vector_info *vi = irq_data_get_irq_chip_data(d);
686 u32 d0, d1, dummy_d0;
687 unsigned long flags;
688 int dest_cpu;
689
690 dest_cpu = cpu_check_affinity(d, dest);
691 if (dest_cpu < 0)
692 return -1;
693
694 cpumask_copy(irq_data_get_affinity_mask(d), cpumask_of(dest_cpu));
695 vi->txn_addr = txn_affinity_addr(d->irq, dest_cpu);
696
697 spin_lock_irqsave(&iosapic_lock, flags);
698
699
700 iosapic_rd_irt_entry(vi, &d0, &d1);
701 iosapic_set_irt_data(vi, &dummy_d0, &d1);
702 iosapic_wr_irt_entry(vi, d0, d1);
703 spin_unlock_irqrestore(&iosapic_lock, flags);
704
705 return 0;
706}
707#endif
708
709static struct irq_chip iosapic_interrupt_type = {
710 .name = "IO-SAPIC-level",
711 .irq_unmask = iosapic_unmask_irq,
712 .irq_mask = iosapic_mask_irq,
713 .irq_ack = cpu_ack_irq,
714 .irq_eoi = iosapic_eoi_irq,
715#ifdef CONFIG_SMP
716 .irq_set_affinity = iosapic_set_affinity_irq,
717#endif
718};
719
720int iosapic_fixup_irq(void *isi_obj, struct pci_dev *pcidev)
721{
722 struct iosapic_info *isi = isi_obj;
723 struct irt_entry *irte = NULL;
724 struct vector_info *vi;
725 int isi_line;
726
727 if (!isi) {
728 printk(KERN_WARNING MODULE_NAME ": hpa not registered for %s\n",
729 pci_name(pcidev));
730 return -1;
731 }
732
733#ifdef CONFIG_SUPERIO
734
735
736
737
738
739
740
741
742 if (is_superio_device(pcidev)) {
743
744 pcidev->irq = superio_fixup_irq(pcidev);
745
746
747 if (PCI_FUNC(pcidev->devfn) != SUPERIO_USB_FN)
748 return pcidev->irq;
749 }
750#endif
751
752
753 irte = iosapic_xlate_pin(isi, pcidev);
754 if (!irte) {
755 printk("iosapic: no IRTE for %s (IRQ not connected?)\n",
756 pci_name(pcidev));
757 return -1;
758 }
759 DBG_IRT("iosapic_fixup_irq(): irte %p %x %x %x %x %x %x %x %x\n",
760 irte,
761 irte->entry_type,
762 irte->entry_length,
763 irte->polarity_trigger,
764 irte->src_bus_irq_devno,
765 irte->src_bus_id,
766 irte->src_seg_id,
767 irte->dest_iosapic_intin,
768 (u32) irte->dest_iosapic_addr);
769 isi_line = irte->dest_iosapic_intin;
770
771
772 vi = isi->isi_vector + isi_line;
773 DBG_IRT("iosapic_fixup_irq: line %d vi 0x%p\n", isi_line, vi);
774
775
776 if (vi->irte)
777 goto out;
778
779 vi->irte = irte;
780
781
782
783
784
785
786
787
788
789
790 vi->txn_irq = txn_alloc_irq(8);
791
792 if (vi->txn_irq < 0)
793 panic("I/O sapic: couldn't get TXN IRQ\n");
794
795
796 vi->txn_addr = txn_alloc_addr(vi->txn_irq);
797 vi->txn_data = txn_alloc_data(vi->txn_irq);
798
799 vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
800 vi->eoi_data = cpu_to_le32(vi->txn_data);
801
802 cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
803
804 out:
805 pcidev->irq = vi->txn_irq;
806
807 DBG_IRT("iosapic_fixup_irq() %d:%d %x %x line %d irq %d\n",
808 PCI_SLOT(pcidev->devfn), PCI_FUNC(pcidev->devfn),
809 pcidev->vendor, pcidev->device, isi_line, pcidev->irq);
810
811 return pcidev->irq;
812}
813
814static struct iosapic_info *iosapic_list;
815
816#ifdef CONFIG_64BIT
817int iosapic_serial_irq(struct parisc_device *dev)
818{
819 struct iosapic_info *isi;
820 struct irt_entry *irte;
821 struct vector_info *vi;
822 int cnt;
823 int intin;
824
825 intin = (dev->mod_info >> 24) & 15;
826
827
828 for (cnt = 0; cnt < irt_num_entry; cnt++) {
829 irte = &irt_cell[cnt];
830 if (COMPARE_IRTE_ADDR(irte, dev->mod0) &&
831 irte->dest_iosapic_intin == intin)
832 break;
833 }
834 if (cnt >= irt_num_entry)
835 return 0;
836
837 DBG_IRT("iosapic_serial_irq(): irte %p %x %x %x %x %x %x %x %x\n",
838 irte,
839 irte->entry_type,
840 irte->entry_length,
841 irte->polarity_trigger,
842 irte->src_bus_irq_devno,
843 irte->src_bus_id,
844 irte->src_seg_id,
845 irte->dest_iosapic_intin,
846 (u32) irte->dest_iosapic_addr);
847
848
849 for (isi = iosapic_list; isi; isi = isi->isi_next)
850 if (isi->isi_hpa == dev->mod0)
851 break;
852 if (!isi)
853 return 0;
854
855
856 vi = isi->isi_vector + intin;
857 DBG_IRT("iosapic_serial_irq: line %d vi 0x%p\n", iosapic_intin, vi);
858
859
860 if (vi->irte)
861 goto out;
862
863 vi->irte = irte;
864
865
866
867
868
869
870
871
872
873
874 vi->txn_irq = txn_alloc_irq(8);
875
876 if (vi->txn_irq < 0)
877 panic("I/O sapic: couldn't get TXN IRQ\n");
878
879
880 vi->txn_addr = txn_alloc_addr(vi->txn_irq);
881 vi->txn_data = txn_alloc_data(vi->txn_irq);
882
883 vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
884 vi->eoi_data = cpu_to_le32(vi->txn_data);
885
886 cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
887
888 out:
889
890 return vi->txn_irq;
891}
892#endif
893
894
895
896
897
898static unsigned int
899iosapic_rd_version(struct iosapic_info *isi)
900{
901 return iosapic_read(isi->addr, IOSAPIC_REG_VERSION);
902}
903
904
905
906
907
908
909
910
911
912
913
914
915void *iosapic_register(unsigned long hpa)
916{
917 struct iosapic_info *isi = NULL;
918 struct irt_entry *irte = irt_cell;
919 struct vector_info *vip;
920 int cnt;
921
922
923
924
925
926
927 for (cnt=0; cnt < irt_num_entry; cnt++, irte++) {
928 WARN_ON(IRT_IOSAPIC_TYPE != irte->entry_type);
929 if (COMPARE_IRTE_ADDR(irte, hpa))
930 break;
931 }
932
933 if (cnt >= irt_num_entry) {
934 DBG("iosapic_register() ignoring 0x%lx (NOT FOUND)\n", hpa);
935 return NULL;
936 }
937
938 isi = kzalloc(sizeof(struct iosapic_info), GFP_KERNEL);
939 if (!isi) {
940 BUG();
941 return NULL;
942 }
943
944 isi->addr = ioremap_nocache(hpa, 4096);
945 isi->isi_hpa = hpa;
946 isi->isi_version = iosapic_rd_version(isi);
947 isi->isi_num_vectors = IOSAPIC_IRDT_MAX_ENTRY(isi->isi_version) + 1;
948
949 vip = isi->isi_vector = kcalloc(isi->isi_num_vectors,
950 sizeof(struct vector_info), GFP_KERNEL);
951 if (vip == NULL) {
952 kfree(isi);
953 return NULL;
954 }
955
956 for (cnt=0; cnt < isi->isi_num_vectors; cnt++, vip++) {
957 vip->irqline = (unsigned char) cnt;
958 vip->iosapic = isi;
959 }
960 isi->isi_next = iosapic_list;
961 iosapic_list = isi;
962 return isi;
963}
964
965
966#ifdef DEBUG_IOSAPIC
967
968static void
969iosapic_prt_irt(void *irt, long num_entry)
970{
971 unsigned int i, *irp = (unsigned int *) irt;
972
973
974 printk(KERN_DEBUG MODULE_NAME ": Interrupt Routing Table (%lx entries)\n", num_entry);
975
976 for (i=0; i<num_entry; i++, irp += 4) {
977 printk(KERN_DEBUG "%p : %2d %.8x %.8x %.8x %.8x\n",
978 irp, i, irp[0], irp[1], irp[2], irp[3]);
979 }
980}
981
982
983static void
984iosapic_prt_vi(struct vector_info *vi)
985{
986 printk(KERN_DEBUG MODULE_NAME ": vector_info[%d] is at %p\n", vi->irqline, vi);
987 printk(KERN_DEBUG "\t\tstatus: %.4x\n", vi->status);
988 printk(KERN_DEBUG "\t\ttxn_irq: %d\n", vi->txn_irq);
989 printk(KERN_DEBUG "\t\ttxn_addr: %lx\n", vi->txn_addr);
990 printk(KERN_DEBUG "\t\ttxn_data: %lx\n", vi->txn_data);
991 printk(KERN_DEBUG "\t\teoi_addr: %p\n", vi->eoi_addr);
992 printk(KERN_DEBUG "\t\teoi_data: %x\n", vi->eoi_data);
993}
994
995
996static void
997iosapic_prt_isi(struct iosapic_info *isi)
998{
999 printk(KERN_DEBUG MODULE_NAME ": io_sapic_info at %p\n", isi);
1000 printk(KERN_DEBUG "\t\tisi_hpa: %lx\n", isi->isi_hpa);
1001 printk(KERN_DEBUG "\t\tisi_status: %x\n", isi->isi_status);
1002 printk(KERN_DEBUG "\t\tisi_version: %x\n", isi->isi_version);
1003 printk(KERN_DEBUG "\t\tisi_vector: %p\n", isi->isi_vector);
1004}
1005#endif
1006