1
2
3
4
5
6
7
8
9
10
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/pinctrl/machine.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include "../core.h"
24#include "pinctrl-mxs.h"
25
26#define SUFFIX_LEN 4
27
28struct mxs_pinctrl_data {
29 struct device *dev;
30 struct pinctrl_dev *pctl;
31 void __iomem *base;
32 struct mxs_pinctrl_soc_data *soc;
33};
34
35static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
36{
37 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
38
39 return d->soc->ngroups;
40}
41
42static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
43 unsigned group)
44{
45 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
46
47 return d->soc->groups[group].name;
48}
49
50static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
51 const unsigned **pins, unsigned *num_pins)
52{
53 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
54
55 *pins = d->soc->groups[group].pins;
56 *num_pins = d->soc->groups[group].npins;
57
58 return 0;
59}
60
61static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
62 unsigned offset)
63{
64 seq_printf(s, " %s", dev_name(pctldev->dev));
65}
66
67static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
68 struct device_node *np,
69 struct pinctrl_map **map, unsigned *num_maps)
70{
71 struct pinctrl_map *new_map;
72 char *group = NULL;
73 unsigned new_num = 1;
74 unsigned long config = 0;
75 unsigned long *pconfig;
76 int length = strlen(np->name) + SUFFIX_LEN;
77 bool purecfg = false;
78 u32 val, reg;
79 int ret, i = 0;
80
81
82 if (of_property_read_u32(np, "reg", ®))
83 purecfg = true;
84
85 ret = of_property_read_u32(np, "fsl,drive-strength", &val);
86 if (!ret)
87 config = val | MA_PRESENT;
88 ret = of_property_read_u32(np, "fsl,voltage", &val);
89 if (!ret)
90 config |= val << VOL_SHIFT | VOL_PRESENT;
91 ret = of_property_read_u32(np, "fsl,pull-up", &val);
92 if (!ret)
93 config |= val << PULL_SHIFT | PULL_PRESENT;
94
95
96 if (!purecfg && config)
97 new_num = 2;
98
99 new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
100 if (!new_map)
101 return -ENOMEM;
102
103 if (!purecfg) {
104 new_map[i].type = PIN_MAP_TYPE_MUX_GROUP;
105 new_map[i].data.mux.function = np->name;
106
107
108 group = kzalloc(length, GFP_KERNEL);
109 if (!group) {
110 ret = -ENOMEM;
111 goto free;
112 }
113 snprintf(group, length, "%s.%d", np->name, reg);
114 new_map[i].data.mux.group = group;
115 i++;
116 }
117
118 if (config) {
119 pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
120 if (!pconfig) {
121 ret = -ENOMEM;
122 goto free_group;
123 }
124
125 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
126 new_map[i].data.configs.group_or_pin = purecfg ? np->name :
127 group;
128 new_map[i].data.configs.configs = pconfig;
129 new_map[i].data.configs.num_configs = 1;
130 }
131
132 *map = new_map;
133 *num_maps = new_num;
134
135 return 0;
136
137free_group:
138 if (!purecfg)
139 kfree(group);
140free:
141 kfree(new_map);
142 return ret;
143}
144
145static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
146 struct pinctrl_map *map, unsigned num_maps)
147{
148 u32 i;
149
150 for (i = 0; i < num_maps; i++) {
151 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
152 kfree(map[i].data.mux.group);
153 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
154 kfree(map[i].data.configs.configs);
155 }
156
157 kfree(map);
158}
159
160static const struct pinctrl_ops mxs_pinctrl_ops = {
161 .get_groups_count = mxs_get_groups_count,
162 .get_group_name = mxs_get_group_name,
163 .get_group_pins = mxs_get_group_pins,
164 .pin_dbg_show = mxs_pin_dbg_show,
165 .dt_node_to_map = mxs_dt_node_to_map,
166 .dt_free_map = mxs_dt_free_map,
167};
168
169static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
170{
171 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
172
173 return d->soc->nfunctions;
174}
175
176static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
177 unsigned function)
178{
179 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
180
181 return d->soc->functions[function].name;
182}
183
184static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
185 unsigned group,
186 const char * const **groups,
187 unsigned * const num_groups)
188{
189 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
190
191 *groups = d->soc->functions[group].groups;
192 *num_groups = d->soc->functions[group].ngroups;
193
194 return 0;
195}
196
197static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
198 unsigned group)
199{
200 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
201 struct mxs_group *g = &d->soc->groups[group];
202 void __iomem *reg;
203 u8 bank, shift;
204 u16 pin;
205 u32 i;
206
207 for (i = 0; i < g->npins; i++) {
208 bank = PINID_TO_BANK(g->pins[i]);
209 pin = PINID_TO_PIN(g->pins[i]);
210 reg = d->base + d->soc->regs->muxsel;
211 reg += bank * 0x20 + pin / 16 * 0x10;
212 shift = pin % 16 * 2;
213
214 writel(0x3 << shift, reg + CLR);
215 writel(g->muxsel[i] << shift, reg + SET);
216 }
217
218 return 0;
219}
220
221static const struct pinmux_ops mxs_pinmux_ops = {
222 .get_functions_count = mxs_pinctrl_get_funcs_count,
223 .get_function_name = mxs_pinctrl_get_func_name,
224 .get_function_groups = mxs_pinctrl_get_func_groups,
225 .set_mux = mxs_pinctrl_set_mux,
226};
227
228static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
229 unsigned pin, unsigned long *config)
230{
231 return -ENOTSUPP;
232}
233
234static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
235 unsigned pin, unsigned long *configs,
236 unsigned num_configs)
237{
238 return -ENOTSUPP;
239}
240
241static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
242 unsigned group, unsigned long *config)
243{
244 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
245
246 *config = d->soc->groups[group].config;
247
248 return 0;
249}
250
251static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
252 unsigned group, unsigned long *configs,
253 unsigned num_configs)
254{
255 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
256 struct mxs_group *g = &d->soc->groups[group];
257 void __iomem *reg;
258 u8 ma, vol, pull, bank, shift;
259 u16 pin;
260 u32 i;
261 int n;
262 unsigned long config;
263
264 for (n = 0; n < num_configs; n++) {
265 config = configs[n];
266
267 ma = CONFIG_TO_MA(config);
268 vol = CONFIG_TO_VOL(config);
269 pull = CONFIG_TO_PULL(config);
270
271 for (i = 0; i < g->npins; i++) {
272 bank = PINID_TO_BANK(g->pins[i]);
273 pin = PINID_TO_PIN(g->pins[i]);
274
275
276 reg = d->base + d->soc->regs->drive;
277 reg += bank * 0x40 + pin / 8 * 0x10;
278
279
280 if (config & MA_PRESENT) {
281 shift = pin % 8 * 4;
282 writel(0x3 << shift, reg + CLR);
283 writel(ma << shift, reg + SET);
284 }
285
286
287 if (config & VOL_PRESENT) {
288 shift = pin % 8 * 4 + 2;
289 if (vol)
290 writel(1 << shift, reg + SET);
291 else
292 writel(1 << shift, reg + CLR);
293 }
294
295
296 if (config & PULL_PRESENT) {
297 reg = d->base + d->soc->regs->pull;
298 reg += bank * 0x10;
299 shift = pin;
300 if (pull)
301 writel(1 << shift, reg + SET);
302 else
303 writel(1 << shift, reg + CLR);
304 }
305 }
306
307
308 g->config = config;
309
310 }
311
312 return 0;
313}
314
315static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
316 struct seq_file *s, unsigned pin)
317{
318
319}
320
321static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
322 struct seq_file *s, unsigned group)
323{
324 unsigned long config;
325
326 if (!mxs_pinconf_group_get(pctldev, group, &config))
327 seq_printf(s, "0x%lx", config);
328}
329
330static const struct pinconf_ops mxs_pinconf_ops = {
331 .pin_config_get = mxs_pinconf_get,
332 .pin_config_set = mxs_pinconf_set,
333 .pin_config_group_get = mxs_pinconf_group_get,
334 .pin_config_group_set = mxs_pinconf_group_set,
335 .pin_config_dbg_show = mxs_pinconf_dbg_show,
336 .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
337};
338
339static struct pinctrl_desc mxs_pinctrl_desc = {
340 .pctlops = &mxs_pinctrl_ops,
341 .pmxops = &mxs_pinmux_ops,
342 .confops = &mxs_pinconf_ops,
343 .owner = THIS_MODULE,
344};
345
346static int mxs_pinctrl_parse_group(struct platform_device *pdev,
347 struct device_node *np, int idx,
348 const char **out_name)
349{
350 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
351 struct mxs_group *g = &d->soc->groups[idx];
352 struct property *prop;
353 const char *propname = "fsl,pinmux-ids";
354 char *group;
355 int length = strlen(np->name) + SUFFIX_LEN;
356 u32 val, i;
357
358 group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
359 if (!group)
360 return -ENOMEM;
361 if (of_property_read_u32(np, "reg", &val))
362 snprintf(group, length, "%s", np->name);
363 else
364 snprintf(group, length, "%s.%d", np->name, val);
365 g->name = group;
366
367 prop = of_find_property(np, propname, &length);
368 if (!prop)
369 return -EINVAL;
370 g->npins = length / sizeof(u32);
371
372 g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
373 GFP_KERNEL);
374 if (!g->pins)
375 return -ENOMEM;
376
377 g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
378 GFP_KERNEL);
379 if (!g->muxsel)
380 return -ENOMEM;
381
382 of_property_read_u32_array(np, propname, g->pins, g->npins);
383 for (i = 0; i < g->npins; i++) {
384 g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
385 g->pins[i] = MUXID_TO_PINID(g->pins[i]);
386 }
387
388 if (out_name)
389 *out_name = g->name;
390
391 return 0;
392}
393
394static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
395 struct mxs_pinctrl_data *d)
396{
397 struct mxs_pinctrl_soc_data *soc = d->soc;
398 struct device_node *np = pdev->dev.of_node;
399 struct device_node *child;
400 struct mxs_function *f;
401 const char *gpio_compat = "fsl,mxs-gpio";
402 const char *fn, *fnull = "";
403 int i = 0, idxf = 0, idxg = 0;
404 int ret;
405 u32 val;
406
407 child = of_get_next_child(np, NULL);
408 if (!child) {
409 dev_err(&pdev->dev, "no group is defined\n");
410 return -ENOENT;
411 }
412
413
414 fn = fnull;
415 for_each_child_of_node(np, child) {
416 if (of_device_is_compatible(child, gpio_compat))
417 continue;
418 soc->ngroups++;
419
420 if (of_property_read_u32(child, "reg", &val))
421 continue;
422 if (strcmp(fn, child->name)) {
423 fn = child->name;
424 soc->nfunctions++;
425 }
426 }
427
428 soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
429 sizeof(*soc->functions), GFP_KERNEL);
430 if (!soc->functions)
431 return -ENOMEM;
432
433 soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
434 sizeof(*soc->groups), GFP_KERNEL);
435 if (!soc->groups)
436 return -ENOMEM;
437
438
439 fn = fnull;
440 f = &soc->functions[idxf];
441 for_each_child_of_node(np, child) {
442 if (of_device_is_compatible(child, gpio_compat))
443 continue;
444 if (of_property_read_u32(child, "reg", &val))
445 continue;
446 if (strcmp(fn, child->name)) {
447 struct device_node *child2;
448
449
450
451
452
453 of_node_get(child);
454
455
456
457
458
459
460
461
462
463 for (child2 = of_get_next_child(np, child);
464 child2 != NULL;
465 child2 = of_get_next_child(np, child2)) {
466 if (!strcmp(child2->name, fn))
467 dev_warn(&pdev->dev,
468 "function nodes must be grouped by name (failed for: %s)",
469 fn);
470 }
471
472 f = &soc->functions[idxf++];
473 f->name = fn = child->name;
474 }
475 f->ngroups++;
476 }
477
478
479 idxf = 0;
480 fn = fnull;
481 for_each_child_of_node(np, child) {
482 if (of_device_is_compatible(child, gpio_compat))
483 continue;
484 if (of_property_read_u32(child, "reg", &val)) {
485 ret = mxs_pinctrl_parse_group(pdev, child,
486 idxg++, NULL);
487 if (ret)
488 return ret;
489 continue;
490 }
491
492 if (strcmp(fn, child->name)) {
493 f = &soc->functions[idxf++];
494 f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
495 sizeof(*f->groups),
496 GFP_KERNEL);
497 if (!f->groups)
498 return -ENOMEM;
499 fn = child->name;
500 i = 0;
501 }
502 ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
503 &f->groups[i++]);
504 if (ret)
505 return ret;
506 }
507
508 return 0;
509}
510
511int mxs_pinctrl_probe(struct platform_device *pdev,
512 struct mxs_pinctrl_soc_data *soc)
513{
514 struct device_node *np = pdev->dev.of_node;
515 struct mxs_pinctrl_data *d;
516 int ret;
517
518 d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
519 if (!d)
520 return -ENOMEM;
521
522 d->dev = &pdev->dev;
523 d->soc = soc;
524
525 d->base = of_iomap(np, 0);
526 if (!d->base)
527 return -EADDRNOTAVAIL;
528
529 mxs_pinctrl_desc.pins = d->soc->pins;
530 mxs_pinctrl_desc.npins = d->soc->npins;
531 mxs_pinctrl_desc.name = dev_name(&pdev->dev);
532
533 platform_set_drvdata(pdev, d);
534
535 ret = mxs_pinctrl_probe_dt(pdev, d);
536 if (ret) {
537 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
538 goto err;
539 }
540
541 d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
542 if (IS_ERR(d->pctl)) {
543 dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
544 ret = PTR_ERR(d->pctl);
545 goto err;
546 }
547
548 return 0;
549
550err:
551 iounmap(d->base);
552 return ret;
553}
554EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
555