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34#ifndef __CSIO_HW_CHIP_H__
35#define __CSIO_HW_CHIP_H__
36
37#include "csio_defs.h"
38
39
40#define CSIO_HW_T5 0x5000
41#define CSIO_T5_FCOE_ASIC 0x5600
42#define CSIO_HW_CHIP_MASK 0xF000
43
44#define T5_REGMAP_SIZE (332 * 1024)
45#define FW_FNAME_T5 "cxgb4/t5fw.bin"
46#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
47
48#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
49#define CHELSIO_CHIP_FPGA 0x100
50#define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
51#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
52
53#define CHELSIO_T5 0x5
54
55enum chip_type {
56 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
57 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
58 T5_FIRST_REV = T5_A0,
59 T5_LAST_REV = T5_A1,
60};
61
62static inline int csio_is_t5(uint16_t chip)
63{
64 return (chip == CSIO_HW_T5);
65}
66
67
68#define CSIO_DEVICE(devid, idx) \
69 { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
70
71#include "t4fw_api.h"
72#include "t4fw_version.h"
73
74#define FW_VERSION(chip) ( \
75 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
76 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
77 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
78 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
79#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
80
81struct fw_info {
82 u8 chip;
83 char *fs_name;
84 char *fw_mod_name;
85 struct fw_hdr fw_hdr;
86};
87
88
89enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
90
91enum {
92 MEMWIN_APERTURE = 2048,
93 MEMWIN_BASE = 0x1b800,
94};
95
96
97struct intr_info {
98 unsigned int mask;
99 const char *msg;
100 short stat_idx;
101 unsigned short fatal;
102};
103
104
105struct csio_hw;
106struct csio_hw_chip_ops {
107 int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
108 void (*chip_pcie_intr_handler)(struct csio_hw *);
109 uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
110 int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
111 __be32 *, uint64_t *);
112 int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
113 __be32 *, uint64_t *);
114 int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
115 u32, uint32_t *, int);
116 void (*chip_dfs_create_ext_mem)(struct csio_hw *);
117};
118
119extern struct csio_hw_chip_ops t5_ops;
120
121#endif
122