linux/drivers/usb/gadget/udc/bdc/bdc.h
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   1/*
   2 * bdc.h - header for the BRCM BDC USB3.0 device controller
   3 *
   4 * Copyright (C) 2014 Broadcom Corporation
   5 *
   6 * Author: Ashwini Pahuja
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms of the GNU General Public License as published by the
  10 * Free Software Foundation; either version 2 of the License, or (at your
  11 * option) any later version.
  12 *
  13 */
  14
  15#ifndef __LINUX_BDC_H__
  16#define __LINUX_BDC_H__
  17
  18#include <linux/kernel.h>
  19#include <linux/usb.h>
  20#include <linux/device.h>
  21#include <linux/spinlock.h>
  22#include <linux/list.h>
  23#include <linux/dma-mapping.h>
  24#include <linux/mm.h>
  25#include <linux/debugfs.h>
  26#include <linux/usb/ch9.h>
  27#include <linux/usb/gadget.h>
  28#include <asm/unaligned.h>
  29
  30#define BRCM_BDC_NAME "bdc_usb3"
  31#define BRCM_BDC_DESC "BDC device controller driver"
  32
  33#define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  34
  35/* BDC command operation timeout in usec*/
  36#define BDC_CMD_TIMEOUT 1000
  37/* BDC controller operation timeout in usec*/
  38#define BDC_COP_TIMEOUT 500
  39
  40/*
  41 * Maximum size of ep0 response buffer for ch9 requests,
  42 * the set_sel request uses 6 so far, the max.
  43*/
  44#define EP0_RESPONSE_BUFF  6
  45/* Start with SS as default */
  46#define EP0_MAX_PKT_SIZE 512
  47
  48/* 64 entries in a SRR */
  49#define NUM_SR_ENTRIES  64
  50
  51/* Num of bds per table */
  52#define NUM_BDS_PER_TABLE       32
  53
  54/* Num of tables in bd list for control,bulk and Int ep */
  55#define NUM_TABLES      2
  56
  57/* Num of tables in bd list for Isoch ep */
  58#define NUM_TABLES_ISOCH        6
  59
  60/* U1 Timeout default: 248usec */
  61#define U1_TIMEOUT      0xf8
  62
  63/* Interrupt coalescence in usec */
  64#define INT_CLS 500
  65
  66/* Register offsets */
  67/* Configuration and Capability registers */
  68#define BDC_BDCCFG0     0x00
  69#define BDC_BDCCFG1     0x04
  70#define BDC_BDCCAP0     0x08
  71#define BDC_BDCCAP1     0x0c
  72#define BDC_CMDPAR0     0x10
  73#define BDC_CMDPAR1     0x14
  74#define BDC_CMDPAR2     0x18
  75#define BDC_CMDSC       0x1c
  76#define BDC_USPC        0x20
  77#define BDC_USPPMS      0x28
  78#define BDC_USPPM2      0x2c
  79#define BDC_SPBBAL      0x38
  80#define BDC_SPBBAH      0x3c
  81#define BDC_BDCSC       0x40
  82#define BDC_XSFNTF      0x4c
  83
  84#define BDC_DVCSA       0x50
  85#define BDC_DVCSB       0x54
  86#define BDC_EPSTS0(n)   (0x60 + (n * 0x10))
  87#define BDC_EPSTS1(n)   (0x64 + (n * 0x10))
  88#define BDC_EPSTS2(n)   (0x68 + (n * 0x10))
  89#define BDC_EPSTS3(n)   (0x6c + (n * 0x10))
  90#define BDC_EPSTS4(n)   (0x70 + (n * 0x10))
  91#define BDC_EPSTS5(n)   (0x74 + (n * 0x10))
  92#define BDC_EPSTS6(n)   (0x78 + (n * 0x10))
  93#define BDC_EPSTS7(n)   (0x7c + (n * 0x10))
  94#define BDC_SRRBAL(n)   (0x200 + (n * 0x10))
  95#define BDC_SRRBAH(n)   (0x204 + (n * 0x10))
  96#define BDC_SRRINT(n)   (0x208 + (n * 0x10))
  97#define BDC_INTCTLS(n)  (0x20c + (n * 0x10))
  98
  99/* Extended capability regs */
 100#define BDC_FSCNOC      0xcd4
 101#define BDC_FSCNIC      0xce4
 102#define NUM_NCS(p)      (p >> 28)
 103
 104/* Register bit fields and Masks */
 105/* BDC Configuration 0 */
 106#define BDC_PGS(p)      (((p) & (0x7 << 8)) >> 8)
 107#define BDC_SPB(p)      (p & 0x7)
 108
 109/* BDC Capability1 */
 110#define BDC_P64         (1 << 0)
 111
 112/* BDC Command register */
 113#define BDC_CMD_FH      0xe
 114#define BDC_CMD_DNC     0x6
 115#define BDC_CMD_EPO     0x4
 116#define BDC_CMD_BLA     0x3
 117#define BDC_CMD_EPC     0x2
 118#define BDC_CMD_DVC     0x1
 119#define BDC_CMD_CWS             (0x1 << 5)
 120#define BDC_CMD_CST(p)          (((p) & (0xf << 6))>>6)
 121#define BDC_CMD_EPN(p)          ((p & 0x1f) << 10)
 122#define BDC_SUB_CMD_ADD         (0x1 << 17)
 123#define BDC_SUB_CMD_FWK         (0x4 << 17)
 124/* Reset sequence number */
 125#define BDC_CMD_EPO_RST_SN      (0x1 << 16)
 126#define BDC_CMD_EP0_XSD         (0x1 << 16)
 127#define BDC_SUB_CMD_ADD_EP      (0x1 << 17)
 128#define BDC_SUB_CMD_DRP_EP      (0x2 << 17)
 129#define BDC_SUB_CMD_EP_STP      (0x2 << 17)
 130#define BDC_SUB_CMD_EP_STL      (0x4 << 17)
 131#define BDC_SUB_CMD_EP_RST      (0x1 << 17)
 132#define BDC_CMD_SRD             (1 << 27)
 133
 134/* CMD completion status */
 135#define BDC_CMDS_SUCC   0x1
 136#define BDC_CMDS_PARA   0x3
 137#define BDC_CMDS_STAT   0x4
 138#define BDC_CMDS_FAIL   0x5
 139#define BDC_CMDS_INTL   0x6
 140#define BDC_CMDS_BUSY   0xf
 141
 142/* CMDSC Param 2 shifts */
 143#define EPT_SHIFT       22
 144#define MP_SHIFT        10
 145#define MB_SHIFT        6
 146#define EPM_SHIFT       4
 147
 148/* BDC USPSC */
 149#define BDC_VBC         (1 << 31)
 150#define BDC_PRC         (1 << 30)
 151#define BDC_PCE         (1 << 29)
 152#define BDC_CFC         (1 << 28)
 153#define BDC_PCC         (1 << 27)
 154#define BDC_PSC         (1 << 26)
 155#define BDC_VBS         (1 << 25)
 156#define BDC_PRS         (1 << 24)
 157#define BDC_PCS         (1 << 23)
 158#define BDC_PSP(p)      (((p) & (0x7 << 20))>>20)
 159#define BDC_SCN         (1 << 8)
 160#define BDC_SDC         (1 << 7)
 161#define BDC_SWS         (1 << 4)
 162
 163#define BDC_USPSC_RW    (BDC_SCN|BDC_SDC|BDC_SWS|0xf)
 164#define BDC_PSP(p)      (((p) & (0x7 << 20))>>20)
 165
 166#define BDC_SPEED_FS    0x1
 167#define BDC_SPEED_LS    0x2
 168#define BDC_SPEED_HS    0x3
 169#define BDC_SPEED_SS    0x4
 170
 171#define BDC_PST(p)      (p & 0xf)
 172#define BDC_PST_MASK    0xf
 173
 174/* USPPMS */
 175#define BDC_U2E         (0x1 << 31)
 176#define BDC_U1E         (0x1 << 30)
 177#define BDC_U2A         (0x1 << 29)
 178#define BDC_PORT_W1S    (0x1 << 17)
 179#define BDC_U1T(p)      ((p) & 0xff)
 180#define BDC_U2T(p)      (((p) & 0xff) << 8)
 181#define BDC_U1T_MASK    0xff
 182
 183/* USBPM2 */
 184/* Hardware LPM Enable */
 185#define BDC_HLE         (1 << 16)
 186
 187/* BDC Status and Control */
 188#define BDC_COP_RST     (1 << 29)
 189#define BDC_COP_RUN     (2 << 29)
 190#define BDC_COP_STP     (4 << 29)
 191
 192#define BDC_COP_MASK (BDC_COP_RST|BDC_COP_RUN|BDC_COP_STP)
 193
 194#define BDC_COS         (1 << 28)
 195#define BDC_CSTS(p)     (((p) & (0x7 << 20)) >> 20)
 196#define BDC_MASK_MCW    (1 << 7)
 197#define BDC_GIE         (1 << 1)
 198#define BDC_GIP         (1 << 0)
 199
 200#define BDC_HLT 1
 201#define BDC_NOR 2
 202#define BDC_OIP 7
 203
 204/* Buffer descriptor and Status report bit fields and masks */
 205#define BD_TYPE_BITMASK (0xf)
 206#define BD_CHAIN        0xf
 207
 208#define BD_TFS_SHIFT    4
 209#define BD_SOT          (1 << 26)
 210#define BD_EOT          (1 << 27)
 211#define BD_ISP          (1 << 29)
 212#define BD_IOC          (1 << 30)
 213#define BD_SBF          (1 << 31)
 214
 215#define BD_INTR_TARGET(p)       (((p) & 0x1f) << 27)
 216
 217#define BDC_SRR_RWS             (1 << 4)
 218#define BDC_SRR_RST             (1 << 3)
 219#define BDC_SRR_ISR             (1 << 2)
 220#define BDC_SRR_IE              (1 << 1)
 221#define BDC_SRR_IP              (1 << 0)
 222#define BDC_SRR_EPI(p)  (((p) & (0xff << 24)) >> 24)
 223#define BDC_SRR_DPI(p) (((p) & (0xff << 16)) >> 16)
 224#define BDC_SRR_DPI_MASK        0x00ff0000
 225
 226#define MARK_CHAIN_BD   (BD_CHAIN|BD_EOT|BD_SOT)
 227
 228/* Control transfer BD specific fields */
 229#define BD_DIR_IN               (1 << 25)
 230
 231#define BDC_PTC_MASK    0xf0000000
 232
 233/* status report defines */
 234#define SR_XSF          0
 235#define SR_USPC         4
 236#define SR_BD_LEN(p)    (p & 0xffffff)
 237
 238#define XSF_SUCC        0x1
 239#define XSF_SHORT       0x3
 240#define XSF_BABB        0x4
 241#define XSF_SETUP_RECV  0x6
 242#define XSF_DATA_START  0x7
 243#define XSF_STATUS_START 0x8
 244
 245#define XSF_STS(p) (((p) >> 28) & 0xf)
 246
 247/* Transfer BD fields */
 248#define BD_LEN(p) ((p) & 0x1ffff)
 249#define BD_LTF          (1 << 25)
 250#define BD_TYPE_DS      0x1
 251#define BD_TYPE_SS      0x2
 252
 253#define BDC_EP_ENABLED     (1 << 0)
 254#define BDC_EP_STALL       (1 << 1)
 255#define BDC_EP_STOP        (1 << 2)
 256
 257/* One BD can transfer max 65536 bytes */
 258#define BD_MAX_BUFF_SIZE        (1 << 16)
 259/* Maximum bytes in one XFR, Refer to BDC spec */
 260#define MAX_XFR_LEN             16777215
 261
 262/* defines for Force Header command */
 263#define DEV_NOTF_TYPE 6
 264#define FWK_SUBTYPE  1
 265#define TRA_PACKET   4
 266
 267#define to_bdc_ep(e)            container_of(e, struct bdc_ep, usb_ep)
 268#define to_bdc_req(r)           container_of(r, struct bdc_req, usb_req)
 269#define gadget_to_bdc(g)        container_of(g, struct bdc, gadget)
 270
 271/* FUNCTION WAKE DEV NOTIFICATION interval, USB3 spec table 8.13 */
 272#define BDC_TNOTIFY 2500 /*in ms*/
 273/* Devstatus bitfields */
 274#define REMOTE_WAKEUP_ISSUED    (1 << 16)
 275#define DEVICE_SUSPENDED        (1 << 17)
 276#define FUNC_WAKE_ISSUED        (1 << 18)
 277#define REMOTE_WAKE_ENABLE      (1 << USB_DEVICE_REMOTE_WAKEUP)
 278
 279/* On disconnect, preserve these bits and clear rest */
 280#define DEVSTATUS_CLEAR         (1 << USB_DEVICE_SELF_POWERED)
 281/* Hardware and software Data structures */
 282
 283/* Endpoint bd: buffer descriptor */
 284struct bdc_bd {
 285        __le32 offset[4];
 286};
 287
 288/* Status report in Status report ring(srr) */
 289struct bdc_sr {
 290        __le32 offset[4];
 291};
 292
 293/* bd_table: contiguous bd's in a table */
 294struct bd_table {
 295        struct bdc_bd *start_bd;
 296        /* dma address of start bd of table*/
 297        dma_addr_t dma;
 298};
 299
 300/*
 301 * Each endpoint has a bdl(buffer descriptor list), bdl consists of 1 or more bd
 302 * table's chained to each other through a chain bd, every table has equal
 303 * number of bds. the software uses bdi(bd index) to refer to particular bd in
 304 * the list.
 305 */
 306struct bd_list {
 307        /* Array of bd table pointers*/
 308        struct bd_table **bd_table_array;
 309        /* How many tables chained to each other */
 310        int num_tabs;
 311        /* Max_bdi = num_tabs * num_bds_table - 1 */
 312        int max_bdi;
 313        /* current enq bdi from sw point of view */
 314        int eqp_bdi;
 315        /* current deq bdi from sw point of view */
 316        int hwd_bdi;
 317        /* numbers of bds per table */
 318        int num_bds_table;
 319};
 320
 321struct bdc_req;
 322
 323/* Representation of a transfer, one transfer can have multiple bd's */
 324struct bd_transfer {
 325        struct bdc_req *req;
 326        /* start bd index */
 327        int start_bdi;
 328        /* this will be the next hw dqp when this transfer completes */
 329        int next_hwd_bdi;
 330        /* number of bds in this transfer */
 331        int num_bds;
 332};
 333
 334/*
 335 * Representation of a gadget request, every gadget request is contained
 336 * by 1 bd_transfer.
 337 */
 338struct bdc_req {
 339        struct usb_request      usb_req;
 340        struct list_head        queue;
 341        struct bdc_ep           *ep;
 342        /* only one Transfer per request */
 343        struct bd_transfer bd_xfr;
 344        int     epnum;
 345};
 346
 347/* scratchpad buffer needed by bdc hardware */
 348struct bdc_scratchpad {
 349        dma_addr_t sp_dma;
 350        void *buff;
 351        u32 size;
 352};
 353
 354/* endpoint representation */
 355struct bdc_ep {
 356        struct usb_ep   usb_ep;
 357        struct list_head queue;
 358        struct bdc *bdc;
 359        u8  ep_type;
 360        u8  dir;
 361        u8  ep_num;
 362        const struct usb_ss_ep_comp_descriptor  *comp_desc;
 363        const struct usb_endpoint_descriptor    *desc;
 364        unsigned int flags;
 365        char name[20];
 366        /* endpoint bd list*/
 367        struct bd_list bd_list;
 368        /*
 369         * HW generates extra event for multi bd tranfers, this flag helps in
 370         * ignoring the extra event
 371         */
 372        bool ignore_next_sr;
 373};
 374
 375/* bdc cmmand parameter structure */
 376struct bdc_cmd_params {
 377        u32     param2;
 378        u32     param1;
 379        u32     param0;
 380};
 381
 382/* status report ring(srr), currently one srr is supported for entire system */
 383struct srr {
 384        struct bdc_sr *sr_bds;
 385        u16     eqp_index;
 386        u16     dqp_index;
 387        dma_addr_t      dma_addr;
 388};
 389
 390/* EP0 states */
 391enum bdc_ep0_state {
 392        WAIT_FOR_SETUP = 0,
 393        WAIT_FOR_DATA_START,
 394        WAIT_FOR_DATA_XMIT,
 395        WAIT_FOR_STATUS_START,
 396        WAIT_FOR_STATUS_XMIT,
 397        STATUS_PENDING
 398};
 399
 400/* Link states */
 401enum bdc_link_state {
 402        BDC_LINK_STATE_U0       = 0x00,
 403        BDC_LINK_STATE_U3       = 0x03,
 404        BDC_LINK_STATE_RX_DET   = 0x05,
 405        BDC_LINK_STATE_RESUME   = 0x0f
 406};
 407
 408/* representation of bdc */
 409struct bdc {
 410        struct usb_gadget       gadget;
 411        struct usb_gadget_driver        *gadget_driver;
 412        struct device   *dev;
 413        /* device lock */
 414        spinlock_t      lock;
 415
 416        /* num of endpoints for a particular instantiation of IP */
 417        unsigned int num_eps;
 418        /*
 419         * Array of ep's, it uses the same index covention as bdc hw i.e.
 420         * 1 for ep0, 2 for 1out,3 for 1in ....
 421         */
 422        struct bdc_ep           **bdc_ep_array;
 423        void __iomem            *regs;
 424        struct bdc_scratchpad   scratchpad;
 425        u32     sp_buff_size;
 426        /* current driver supports 1 status ring */
 427        struct srr      srr;
 428        /* Last received setup packet */
 429        struct  usb_ctrlrequest setup_pkt;
 430        struct  bdc_req ep0_req;
 431        struct  bdc_req status_req;
 432        enum    bdc_ep0_state ep0_state;
 433        bool    delayed_status;
 434        bool    zlp_needed;
 435        bool    reinit;
 436        bool    pullup;
 437        /* Bits 0-15 are standard and 16-31 for proprietary information */
 438        u32     devstatus;
 439        int     irq;
 440        void    *mem;
 441        u32     dev_addr;
 442        /* DMA pools */
 443        struct dma_pool *bd_table_pool;
 444        u8              test_mode;
 445        /* array of callbacks for various status report handlers */
 446        void (*sr_handler[2])(struct bdc *, struct bdc_sr *);
 447        /* ep0 callback handlers */
 448        void (*sr_xsf_ep0[3])(struct bdc *, struct bdc_sr *);
 449        /* ep0 response buffer for ch9 requests like GET_STATUS and SET_SEL */
 450        unsigned char           ep0_response_buff[EP0_RESPONSE_BUFF];
 451        /*
 452         * Timer to check if host resumed transfer after bdc sent Func wake
 453         * notification  packet after a remote wakeup. if not, then resend the
 454         * Func Wake packet every 2.5 secs. Refer to USB3 spec section 8.5.6.4
 455         */
 456        struct delayed_work     func_wake_notify;
 457};
 458
 459static inline u32 bdc_readl(void __iomem *base, u32 offset)
 460{
 461        return readl(base + offset);
 462}
 463
 464static inline void bdc_writel(void __iomem *base, u32 offset, u32 value)
 465{
 466        writel(value, base + offset);
 467}
 468
 469/* Buffer descriptor list operations */
 470void bdc_notify_xfr(struct bdc *, u32);
 471void bdc_softconn(struct bdc *);
 472void bdc_softdisconn(struct bdc *);
 473int bdc_run(struct bdc *);
 474int bdc_stop(struct bdc *);
 475int bdc_reset(struct bdc *);
 476int bdc_udc_init(struct bdc *);
 477void bdc_udc_exit(struct bdc *);
 478int bdc_reinit(struct bdc *);
 479
 480/* Status report handlers */
 481/* Upstream port status change sr */
 482void bdc_sr_uspc(struct bdc *, struct bdc_sr *);
 483/* transfer sr */
 484void bdc_sr_xsf(struct bdc *, struct bdc_sr *);
 485/* EP0 XSF handlers */
 486void bdc_xsf_ep0_setup_recv(struct bdc *, struct bdc_sr *);
 487void bdc_xsf_ep0_data_start(struct bdc *, struct bdc_sr *);
 488void bdc_xsf_ep0_status_start(struct bdc *, struct bdc_sr *);
 489
 490#endif /* __LINUX_BDC_H__ */
 491