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13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/gpio.h>
20#include <linux/syscore_ops.h>
21#include <linux/serial_core.h>
22#include <linux/serial_s3c.h>
23#include <linux/platform_device.h>
24#include <linux/dm9000.h>
25#include <linux/ata_platform.h>
26#include <linux/i2c.h>
27#include <linux/io.h>
28#include <linux/serial_8250.h>
29
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/nand_ecc.h>
33#include <linux/mtd/partitions.h>
34
35#include <linux/platform_data/asoc-s3c24xx_simtec.h>
36#include <linux/platform_data/hwmon-s3c.h>
37#include <linux/platform_data/i2c-s3c2410.h>
38#include <linux/platform_data/mtd-nand-s3c2410.h>
39
40#include <net/ax88796.h>
41
42#include <asm/irq.h>
43#include <asm/mach/arch.h>
44#include <asm/mach/map.h>
45#include <asm/mach/irq.h>
46#include <asm/mach-types.h>
47
48#include <mach/fb.h>
49#include <mach/hardware.h>
50#include <mach/regs-gpio.h>
51#include <mach/regs-lcd.h>
52#include <mach/gpio-samsung.h>
53
54#include <plat/cpu.h>
55#include <plat/cpu-freq.h>
56#include <plat/devs.h>
57#include <plat/gpio-cfg.h>
58#include <plat/samsung-time.h>
59
60#include "bast.h"
61#include "common.h"
62#include "simtec.h"
63
64#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
65
66
67#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
68#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
69#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
70#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
71
72
73
74#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
75#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
76#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
77#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
78
79static struct map_desc bast_iodesc[] __initdata = {
80
81 {
82 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
83 .pfn = PA_CS2(BAST_PA_ISAIO),
84 .length = SZ_16M,
85 .type = MT_DEVICE,
86 }, {
87 .virtual = (u32)S3C24XX_VA_ISA_WORD,
88 .pfn = PA_CS3(BAST_PA_ISAIO),
89 .length = SZ_16M,
90 .type = MT_DEVICE,
91 },
92
93 {
94 .virtual = (u32)BAST_VA_CTRL1,
95 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
96 .length = SZ_1M,
97 .type = MT_DEVICE,
98 }, {
99 .virtual = (u32)BAST_VA_CTRL2,
100 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
101 .length = SZ_1M,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = (u32)BAST_VA_CTRL3,
105 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
106 .length = SZ_1M,
107 .type = MT_DEVICE,
108 }, {
109 .virtual = (u32)BAST_VA_CTRL4,
110 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
111 .length = SZ_1M,
112 .type = MT_DEVICE,
113 },
114
115 {
116 .virtual = (u32)BAST_VA_PC104_IRQREQ,
117 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
118 .length = SZ_1M,
119 .type = MT_DEVICE,
120 }, {
121 .virtual = (u32)BAST_VA_PC104_IRQRAW,
122 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
123 .length = SZ_1M,
124 .type = MT_DEVICE,
125 }, {
126 .virtual = (u32)BAST_VA_PC104_IRQMASK,
127 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
128 .length = SZ_1M,
129 .type = MT_DEVICE,
130 },
131
132
133
134
135
136
137 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
138 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
139 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
140
141
142 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
143 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
144 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
145
146
147 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
148 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
149 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
150
151
152 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
153 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
154 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
155};
156
157#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
158#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
159#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
160
161static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
162 [0] = {
163 .hwport = 0,
164 .flags = 0,
165 .ucon = UCON,
166 .ulcon = ULCON,
167 .ufcon = UFCON,
168 },
169 [1] = {
170 .hwport = 1,
171 .flags = 0,
172 .ucon = UCON,
173 .ulcon = ULCON,
174 .ufcon = UFCON,
175 },
176
177 [2] = {
178 .hwport = 2,
179 .flags = 0,
180 .ucon = UCON,
181 .ulcon = ULCON,
182 .ufcon = UFCON,
183 }
184};
185
186
187
188#ifdef CONFIG_PM
189static int bast_pm_suspend(void)
190{
191
192 gpio_direction_output(S3C2410_GPA(21), 1);
193 return 0;
194}
195
196static void bast_pm_resume(void)
197{
198 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
199}
200
201#else
202#define bast_pm_suspend NULL
203#define bast_pm_resume NULL
204#endif
205
206static struct syscore_ops bast_pm_syscore_ops = {
207 .suspend = bast_pm_suspend,
208 .resume = bast_pm_resume,
209};
210
211static int smartmedia_map[] = { 0 };
212static int chip0_map[] = { 1 };
213static int chip1_map[] = { 2 };
214static int chip2_map[] = { 3 };
215
216static struct mtd_partition __initdata bast_default_nand_part[] = {
217 [0] = {
218 .name = "Boot Agent",
219 .size = SZ_16K,
220 .offset = 0,
221 },
222 [1] = {
223 .name = "/boot",
224 .size = SZ_4M - SZ_16K,
225 .offset = SZ_16K,
226 },
227 [2] = {
228 .name = "user",
229 .offset = SZ_4M,
230 .size = MTDPART_SIZ_FULL,
231 }
232};
233
234
235
236
237
238
239
240
241
242static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
243 [0] = {
244 .name = "SmartMedia",
245 .nr_chips = 1,
246 .nr_map = smartmedia_map,
247 .options = NAND_SCAN_SILENT_NODEV,
248 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
249 .partitions = bast_default_nand_part,
250 },
251 [1] = {
252 .name = "chip0",
253 .nr_chips = 1,
254 .nr_map = chip0_map,
255 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
256 .partitions = bast_default_nand_part,
257 },
258 [2] = {
259 .name = "chip1",
260 .nr_chips = 1,
261 .nr_map = chip1_map,
262 .options = NAND_SCAN_SILENT_NODEV,
263 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
264 .partitions = bast_default_nand_part,
265 },
266 [3] = {
267 .name = "chip2",
268 .nr_chips = 1,
269 .nr_map = chip2_map,
270 .options = NAND_SCAN_SILENT_NODEV,
271 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
272 .partitions = bast_default_nand_part,
273 }
274};
275
276static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
277{
278 unsigned int tmp;
279
280 slot = set->nr_map[slot] & 3;
281
282 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
283 slot, set, set->nr_map);
284
285 tmp = __raw_readb(BAST_VA_CTRL2);
286 tmp &= BAST_CPLD_CTLR2_IDERST;
287 tmp |= slot;
288 tmp |= BAST_CPLD_CTRL2_WNAND;
289
290 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
291
292 __raw_writeb(tmp, BAST_VA_CTRL2);
293}
294
295static struct s3c2410_platform_nand __initdata bast_nand_info = {
296 .tacls = 30,
297 .twrph0 = 60,
298 .twrph1 = 60,
299 .nr_sets = ARRAY_SIZE(bast_nand_sets),
300 .sets = bast_nand_sets,
301 .select_chip = bast_nand_select,
302 .ecc_mode = NAND_ECC_SOFT,
303};
304
305
306
307static struct resource bast_dm9k_resource[] = {
308 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
309 [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
310 [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
311 | IORESOURCE_IRQ_HIGHLEVEL),
312};
313
314
315
316
317
318static struct dm9000_plat_data bast_dm9k_platdata = {
319 .flags = DM9000_PLATF_16BITONLY,
320};
321
322static struct platform_device bast_device_dm9k = {
323 .name = "dm9000",
324 .id = 0,
325 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
326 .resource = bast_dm9k_resource,
327 .dev = {
328 .platform_data = &bast_dm9k_platdata,
329 }
330};
331
332
333
334#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
335#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
336#define SERIAL_CLK (1843200)
337
338static struct plat_serial8250_port bast_sio_data[] = {
339 [0] = {
340 .mapbase = SERIAL_BASE + 0x2f8,
341 .irq = BAST_IRQ_PCSERIAL1,
342 .flags = SERIAL_FLAGS,
343 .iotype = UPIO_MEM,
344 .regshift = 0,
345 .uartclk = SERIAL_CLK,
346 },
347 [1] = {
348 .mapbase = SERIAL_BASE + 0x3f8,
349 .irq = BAST_IRQ_PCSERIAL2,
350 .flags = SERIAL_FLAGS,
351 .iotype = UPIO_MEM,
352 .regshift = 0,
353 .uartclk = SERIAL_CLK,
354 },
355 { }
356};
357
358static struct platform_device bast_sio = {
359 .name = "serial8250",
360 .id = PLAT8250_DEV_PLATFORM,
361 .dev = {
362 .platform_data = &bast_sio_data,
363 },
364};
365
366
367
368
369
370static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
371 .flags = 0,
372 .slave_addr = 0x10,
373 .frequency = 100*1000,
374};
375
376
377
378static struct ax_plat_data bast_asix_platdata = {
379 .flags = AXFLG_MAC_FROMDEV,
380 .wordlength = 2,
381 .dcr_val = 0x48,
382 .rcr_val = 0x40,
383};
384
385static struct resource bast_asix_resource[] = {
386 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
387 [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
388 [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
389};
390
391static struct platform_device bast_device_asix = {
392 .name = "ax88796",
393 .id = 0,
394 .num_resources = ARRAY_SIZE(bast_asix_resource),
395 .resource = bast_asix_resource,
396 .dev = {
397 .platform_data = &bast_asix_platdata
398 }
399};
400
401
402
403static struct resource bast_asixpp_resource[] = {
404 [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
405 0x30 * 0x20),
406};
407
408static struct platform_device bast_device_axpp = {
409 .name = "ax88796-pp",
410 .id = 0,
411 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
412 .resource = bast_asixpp_resource,
413};
414
415
416
417static struct s3c2410fb_display __initdata bast_lcd_info[] = {
418 {
419 .type = S3C2410_LCDCON1_TFT,
420 .width = 640,
421 .height = 480,
422
423 .pixclock = 33333,
424 .xres = 640,
425 .yres = 480,
426 .bpp = 4,
427 .left_margin = 40,
428 .right_margin = 20,
429 .hsync_len = 88,
430 .upper_margin = 30,
431 .lower_margin = 32,
432 .vsync_len = 3,
433
434 .lcdcon5 = 0x00014b02,
435 },
436 {
437 .type = S3C2410_LCDCON1_TFT,
438 .width = 640,
439 .height = 480,
440
441 .pixclock = 33333,
442 .xres = 640,
443 .yres = 480,
444 .bpp = 8,
445 .left_margin = 40,
446 .right_margin = 20,
447 .hsync_len = 88,
448 .upper_margin = 30,
449 .lower_margin = 32,
450 .vsync_len = 3,
451
452 .lcdcon5 = 0x00014b02,
453 },
454 {
455 .type = S3C2410_LCDCON1_TFT,
456 .width = 640,
457 .height = 480,
458
459 .pixclock = 33333,
460 .xres = 640,
461 .yres = 480,
462 .bpp = 16,
463 .left_margin = 40,
464 .right_margin = 20,
465 .hsync_len = 88,
466 .upper_margin = 30,
467 .lower_margin = 32,
468 .vsync_len = 3,
469
470 .lcdcon5 = 0x00014b02,
471 },
472};
473
474
475
476static struct s3c2410fb_mach_info __initdata bast_fb_info = {
477
478 .displays = bast_lcd_info,
479 .num_displays = ARRAY_SIZE(bast_lcd_info),
480 .default_display = 1,
481};
482
483
484
485static struct i2c_board_info bast_i2c_devs[] __initdata = {
486 {
487 I2C_BOARD_INFO("tlv320aic23", 0x1a),
488 }, {
489 I2C_BOARD_INFO("simtec-pmu", 0x6b),
490 }, {
491 I2C_BOARD_INFO("ch7013", 0x75),
492 },
493};
494
495static struct s3c_hwmon_pdata bast_hwmon_info = {
496
497 .in[0] = &(struct s3c_hwmon_chcfg) {
498 .name = "lcd-contrast",
499 .mult = 3300,
500 .div = 512,
501 },
502
503 .in[1] = &(struct s3c_hwmon_chcfg) {
504 .name = "led-feedback",
505 .mult = 3300,
506 .div = 1024,
507 },
508
509 .in[2] = &(struct s3c_hwmon_chcfg) {
510 .name = "lcd-feedback",
511 .mult = 3300,
512 .div = 512,
513 },
514
515 .in[3] = &(struct s3c_hwmon_chcfg) {
516 .name = "vcore",
517 .mult = 3300,
518 .div = 1024,
519 },
520};
521
522
523
524
525static struct platform_device *bast_devices[] __initdata = {
526 &s3c2410_device_dclk,
527 &s3c_device_ohci,
528 &s3c_device_lcd,
529 &s3c_device_wdt,
530 &s3c_device_i2c0,
531 &s3c_device_rtc,
532 &s3c_device_nand,
533 &s3c_device_adc,
534 &s3c_device_hwmon,
535 &bast_device_dm9k,
536 &bast_device_asix,
537 &bast_device_axpp,
538 &bast_sio,
539};
540
541static struct s3c_cpufreq_board __initdata bast_cpufreq = {
542 .refresh = 7800,
543 .auto_io = 1,
544 .need_io = 1,
545};
546
547static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
548 .have_mic = 1,
549 .have_lout = 1,
550};
551
552static void __init bast_map_io(void)
553{
554 s3c_hwmon_set_platdata(&bast_hwmon_info);
555
556 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
557 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
558 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
559}
560
561static void __init bast_init_time(void)
562{
563 s3c2410_init_clocks(12000000);
564 samsung_timer_init();
565}
566
567static void __init bast_init(void)
568{
569 register_syscore_ops(&bast_pm_syscore_ops);
570
571 s3c_i2c0_set_platdata(&bast_i2c_info);
572 s3c_nand_set_platdata(&bast_nand_info);
573 s3c24xx_fb_set_platdata(&bast_fb_info);
574 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
575
576 i2c_register_board_info(0, bast_i2c_devs,
577 ARRAY_SIZE(bast_i2c_devs));
578
579 usb_simtec_init();
580 nor_simtec_init();
581 simtec_audio_add(NULL, true, &bast_audio);
582
583 WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
584
585 s3c_cpufreq_setboard(&bast_cpufreq);
586}
587
588MACHINE_START(BAST, "Simtec-BAST")
589
590 .atag_offset = 0x100,
591 .map_io = bast_map_io,
592 .init_irq = s3c2410_init_irq,
593 .init_machine = bast_init,
594 .init_time = bast_init_time,
595MACHINE_END
596
