1#ifndef __iop_sap_in_defs_asm_h
2#define __iop_sap_in_defs_asm_h
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17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56
57#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0
58#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2
59#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2
60#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3
61#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5
62#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2
63#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7
64#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1
65#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7
66#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8
67#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2
68#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10
69#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3
70#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13
71#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2
72#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15
73#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1
74#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15
75#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16
76#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2
77#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18
78#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3
79#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21
80#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2
81#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23
82#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1
83#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23
84#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24
85#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2
86#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26
87#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3
88#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29
89#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2
90#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31
91#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1
92#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31
93#define reg_iop_sap_in_rw_bus0_sync_offset 0
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95
96#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0
97#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2
98#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2
99#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3
100#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5
101#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2
102#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7
103#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1
104#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7
105#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8
106#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2
107#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10
108#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3
109#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13
110#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2
111#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15
112#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1
113#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15
114#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16
115#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2
116#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18
117#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3
118#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21
119#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2
120#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23
121#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1
122#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23
123#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24
124#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2
125#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26
126#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3
127#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29
128#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2
129#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31
130#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1
131#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31
132#define reg_iop_sap_in_rw_bus1_sync_offset 4
133
134#define STRIDE_iop_sap_in_rw_gio 4
135
136#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
137#define reg_iop_sap_in_rw_gio___sync_sel___width 2
138#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
139#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
140#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
141#define reg_iop_sap_in_rw_gio___sync_edge___width 2
142#define reg_iop_sap_in_rw_gio___delay___lsb 7
143#define reg_iop_sap_in_rw_gio___delay___width 1
144#define reg_iop_sap_in_rw_gio___delay___bit 7
145#define reg_iop_sap_in_rw_gio___logic___lsb 8
146#define reg_iop_sap_in_rw_gio___logic___width 2
147#define reg_iop_sap_in_rw_gio_offset 8
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150
151#define regk_iop_sap_in_and 0x00000002
152#define regk_iop_sap_in_ext_clk200 0x00000003
153#define regk_iop_sap_in_gio1 0x00000000
154#define regk_iop_sap_in_gio13 0x00000005
155#define regk_iop_sap_in_gio18 0x00000003
156#define regk_iop_sap_in_gio19 0x00000004
157#define regk_iop_sap_in_gio21 0x00000006
158#define regk_iop_sap_in_gio23 0x00000005
159#define regk_iop_sap_in_gio29 0x00000007
160#define regk_iop_sap_in_gio5 0x00000004
161#define regk_iop_sap_in_gio6 0x00000001
162#define regk_iop_sap_in_gio7 0x00000002
163#define regk_iop_sap_in_inv 0x00000001
164#define regk_iop_sap_in_neg 0x00000002
165#define regk_iop_sap_in_no 0x00000000
166#define regk_iop_sap_in_no_del_ext_clk200 0x00000001
167#define regk_iop_sap_in_none 0x00000000
168#define regk_iop_sap_in_or 0x00000003
169#define regk_iop_sap_in_pos 0x00000001
170#define regk_iop_sap_in_pos_neg 0x00000003
171#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202
172#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202
173#define regk_iop_sap_in_rw_gio_default 0x00000002
174#define regk_iop_sap_in_rw_gio_size 0x00000020
175#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006
176#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004
177#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005
178#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007
179#define regk_iop_sap_in_tmr_clk200 0x00000000
180#define regk_iop_sap_in_two_clk200 0x00000002
181#define regk_iop_sap_in_yes 0x00000001
182#endif
183
