1
2
3
4
5
6
7
8
9
10
11#include <linux/compat.h>
12#include <linux/types.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <linux/kbuild.h>
16#include <linux/suspend.h>
17#include <asm/cpu-info.h>
18#include <asm/pm.h>
19#include <asm/ptrace.h>
20#include <asm/processor.h>
21#include <asm/smp-cps.h>
22
23#include <linux/kvm_host.h>
24
25void output_ptreg_defines(void)
26{
27 COMMENT("MIPS pt_regs offsets.");
28 OFFSET(PT_R0, pt_regs, regs[0]);
29 OFFSET(PT_R1, pt_regs, regs[1]);
30 OFFSET(PT_R2, pt_regs, regs[2]);
31 OFFSET(PT_R3, pt_regs, regs[3]);
32 OFFSET(PT_R4, pt_regs, regs[4]);
33 OFFSET(PT_R5, pt_regs, regs[5]);
34 OFFSET(PT_R6, pt_regs, regs[6]);
35 OFFSET(PT_R7, pt_regs, regs[7]);
36 OFFSET(PT_R8, pt_regs, regs[8]);
37 OFFSET(PT_R9, pt_regs, regs[9]);
38 OFFSET(PT_R10, pt_regs, regs[10]);
39 OFFSET(PT_R11, pt_regs, regs[11]);
40 OFFSET(PT_R12, pt_regs, regs[12]);
41 OFFSET(PT_R13, pt_regs, regs[13]);
42 OFFSET(PT_R14, pt_regs, regs[14]);
43 OFFSET(PT_R15, pt_regs, regs[15]);
44 OFFSET(PT_R16, pt_regs, regs[16]);
45 OFFSET(PT_R17, pt_regs, regs[17]);
46 OFFSET(PT_R18, pt_regs, regs[18]);
47 OFFSET(PT_R19, pt_regs, regs[19]);
48 OFFSET(PT_R20, pt_regs, regs[20]);
49 OFFSET(PT_R21, pt_regs, regs[21]);
50 OFFSET(PT_R22, pt_regs, regs[22]);
51 OFFSET(PT_R23, pt_regs, regs[23]);
52 OFFSET(PT_R24, pt_regs, regs[24]);
53 OFFSET(PT_R25, pt_regs, regs[25]);
54 OFFSET(PT_R26, pt_regs, regs[26]);
55 OFFSET(PT_R27, pt_regs, regs[27]);
56 OFFSET(PT_R28, pt_regs, regs[28]);
57 OFFSET(PT_R29, pt_regs, regs[29]);
58 OFFSET(PT_R30, pt_regs, regs[30]);
59 OFFSET(PT_R31, pt_regs, regs[31]);
60 OFFSET(PT_LO, pt_regs, lo);
61 OFFSET(PT_HI, pt_regs, hi);
62#ifdef CONFIG_CPU_HAS_SMARTMIPS
63 OFFSET(PT_ACX, pt_regs, acx);
64#endif
65 OFFSET(PT_EPC, pt_regs, cp0_epc);
66 OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
67 OFFSET(PT_STATUS, pt_regs, cp0_status);
68 OFFSET(PT_CAUSE, pt_regs, cp0_cause);
69#ifdef CONFIG_CPU_CAVIUM_OCTEON
70 OFFSET(PT_MPL, pt_regs, mpl);
71 OFFSET(PT_MTP, pt_regs, mtp);
72#endif
73 DEFINE(PT_SIZE, sizeof(struct pt_regs));
74 BLANK();
75}
76
77void output_task_defines(void)
78{
79 COMMENT("MIPS task_struct offsets.");
80 OFFSET(TASK_STATE, task_struct, state);
81 OFFSET(TASK_THREAD_INFO, task_struct, stack);
82 OFFSET(TASK_FLAGS, task_struct, flags);
83 OFFSET(TASK_MM, task_struct, mm);
84 OFFSET(TASK_PID, task_struct, pid);
85#if defined(CONFIG_CC_STACKPROTECTOR)
86 OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
87#endif
88 DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
89 BLANK();
90}
91
92void output_thread_info_defines(void)
93{
94 COMMENT("MIPS thread_info offsets.");
95 OFFSET(TI_TASK, thread_info, task);
96 OFFSET(TI_FLAGS, thread_info, flags);
97 OFFSET(TI_TP_VALUE, thread_info, tp_value);
98 OFFSET(TI_CPU, thread_info, cpu);
99 OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
100 OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
101 OFFSET(TI_REGS, thread_info, regs);
102 DEFINE(_THREAD_SIZE, THREAD_SIZE);
103 DEFINE(_THREAD_MASK, THREAD_MASK);
104 DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
105 DEFINE(_IRQ_STACK_START, IRQ_STACK_START);
106 BLANK();
107}
108
109void output_thread_defines(void)
110{
111 COMMENT("MIPS specific thread_struct offsets.");
112 OFFSET(THREAD_REG16, task_struct, thread.reg16);
113 OFFSET(THREAD_REG17, task_struct, thread.reg17);
114 OFFSET(THREAD_REG18, task_struct, thread.reg18);
115 OFFSET(THREAD_REG19, task_struct, thread.reg19);
116 OFFSET(THREAD_REG20, task_struct, thread.reg20);
117 OFFSET(THREAD_REG21, task_struct, thread.reg21);
118 OFFSET(THREAD_REG22, task_struct, thread.reg22);
119 OFFSET(THREAD_REG23, task_struct, thread.reg23);
120 OFFSET(THREAD_REG29, task_struct, thread.reg29);
121 OFFSET(THREAD_REG30, task_struct, thread.reg30);
122 OFFSET(THREAD_REG31, task_struct, thread.reg31);
123 OFFSET(THREAD_STATUS, task_struct,
124 thread.cp0_status);
125 OFFSET(THREAD_FPU, task_struct, thread.fpu);
126
127 OFFSET(THREAD_BVADDR, task_struct, \
128 thread.cp0_badvaddr);
129 OFFSET(THREAD_BUADDR, task_struct, \
130 thread.cp0_baduaddr);
131 OFFSET(THREAD_ECODE, task_struct, \
132 thread.error_code);
133 OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
134 BLANK();
135}
136
137void output_thread_fpu_defines(void)
138{
139 OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
140 OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
141 OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
142 OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
143 OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
144 OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
145 OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
146 OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
147 OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
148 OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
149 OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
150 OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
151 OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
152 OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
153 OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
154 OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
155 OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
156 OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
157 OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
158 OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
159 OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
160 OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
161 OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
162 OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
163 OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
164 OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
165 OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
166 OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
167 OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
168 OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
169 OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
170 OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
171
172 OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
173 OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
174 BLANK();
175}
176
177void output_mm_defines(void)
178{
179 COMMENT("Size of struct page");
180 DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
181 BLANK();
182 COMMENT("Linux mm_struct offsets.");
183 OFFSET(MM_USERS, mm_struct, mm_users);
184 OFFSET(MM_PGD, mm_struct, pgd);
185 OFFSET(MM_CONTEXT, mm_struct, context);
186 BLANK();
187 DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
188 DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
189 DEFINE(_PTE_T_SIZE, sizeof(pte_t));
190 BLANK();
191 DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
192#ifndef __PAGETABLE_PMD_FOLDED
193 DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
194#endif
195 DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
196 BLANK();
197 DEFINE(_PGD_ORDER, PGD_ORDER);
198#ifndef __PAGETABLE_PMD_FOLDED
199 DEFINE(_PMD_ORDER, PMD_ORDER);
200#endif
201 DEFINE(_PTE_ORDER, PTE_ORDER);
202 BLANK();
203 DEFINE(_PMD_SHIFT, PMD_SHIFT);
204 DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
205 BLANK();
206 DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
207 DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
208 DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
209 BLANK();
210 DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
211 DEFINE(_PAGE_SIZE, PAGE_SIZE);
212 BLANK();
213}
214
215#ifdef CONFIG_32BIT
216void output_sc_defines(void)
217{
218 COMMENT("Linux sigcontext offsets.");
219 OFFSET(SC_REGS, sigcontext, sc_regs);
220 OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
221 OFFSET(SC_ACX, sigcontext, sc_acx);
222 OFFSET(SC_MDHI, sigcontext, sc_mdhi);
223 OFFSET(SC_MDLO, sigcontext, sc_mdlo);
224 OFFSET(SC_PC, sigcontext, sc_pc);
225 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
226 OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
227 OFFSET(SC_HI1, sigcontext, sc_hi1);
228 OFFSET(SC_LO1, sigcontext, sc_lo1);
229 OFFSET(SC_HI2, sigcontext, sc_hi2);
230 OFFSET(SC_LO2, sigcontext, sc_lo2);
231 OFFSET(SC_HI3, sigcontext, sc_hi3);
232 OFFSET(SC_LO3, sigcontext, sc_lo3);
233 BLANK();
234}
235#endif
236
237#ifdef CONFIG_64BIT
238void output_sc_defines(void)
239{
240 COMMENT("Linux sigcontext offsets.");
241 OFFSET(SC_REGS, sigcontext, sc_regs);
242 OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
243 OFFSET(SC_MDHI, sigcontext, sc_mdhi);
244 OFFSET(SC_MDLO, sigcontext, sc_mdlo);
245 OFFSET(SC_PC, sigcontext, sc_pc);
246 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
247 BLANK();
248}
249#endif
250
251void output_signal_defined(void)
252{
253 COMMENT("Linux signal numbers.");
254 DEFINE(_SIGHUP, SIGHUP);
255 DEFINE(_SIGINT, SIGINT);
256 DEFINE(_SIGQUIT, SIGQUIT);
257 DEFINE(_SIGILL, SIGILL);
258 DEFINE(_SIGTRAP, SIGTRAP);
259 DEFINE(_SIGIOT, SIGIOT);
260 DEFINE(_SIGABRT, SIGABRT);
261 DEFINE(_SIGEMT, SIGEMT);
262 DEFINE(_SIGFPE, SIGFPE);
263 DEFINE(_SIGKILL, SIGKILL);
264 DEFINE(_SIGBUS, SIGBUS);
265 DEFINE(_SIGSEGV, SIGSEGV);
266 DEFINE(_SIGSYS, SIGSYS);
267 DEFINE(_SIGPIPE, SIGPIPE);
268 DEFINE(_SIGALRM, SIGALRM);
269 DEFINE(_SIGTERM, SIGTERM);
270 DEFINE(_SIGUSR1, SIGUSR1);
271 DEFINE(_SIGUSR2, SIGUSR2);
272 DEFINE(_SIGCHLD, SIGCHLD);
273 DEFINE(_SIGPWR, SIGPWR);
274 DEFINE(_SIGWINCH, SIGWINCH);
275 DEFINE(_SIGURG, SIGURG);
276 DEFINE(_SIGIO, SIGIO);
277 DEFINE(_SIGSTOP, SIGSTOP);
278 DEFINE(_SIGTSTP, SIGTSTP);
279 DEFINE(_SIGCONT, SIGCONT);
280 DEFINE(_SIGTTIN, SIGTTIN);
281 DEFINE(_SIGTTOU, SIGTTOU);
282 DEFINE(_SIGVTALRM, SIGVTALRM);
283 DEFINE(_SIGPROF, SIGPROF);
284 DEFINE(_SIGXCPU, SIGXCPU);
285 DEFINE(_SIGXFSZ, SIGXFSZ);
286 BLANK();
287}
288
289#ifdef CONFIG_CPU_CAVIUM_OCTEON
290void output_octeon_cop2_state_defines(void)
291{
292 COMMENT("Octeon specific octeon_cop2_state offsets.");
293 OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
294 OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
295 OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
296 OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
297 OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
298 OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
299 OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
300 OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
301 OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
302 OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
303 OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
304 OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
305 OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
306 OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
307 OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
308 OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
309 OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
310 OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3);
311 OFFSET(THREAD_CP2, task_struct, thread.cp2);
312 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
313 BLANK();
314}
315#endif
316
317#ifdef CONFIG_HIBERNATION
318void output_pbe_defines(void)
319{
320 COMMENT(" Linux struct pbe offsets. ");
321 OFFSET(PBE_ADDRESS, pbe, address);
322 OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
323 OFFSET(PBE_NEXT, pbe, next);
324 DEFINE(PBE_SIZE, sizeof(struct pbe));
325 BLANK();
326}
327#endif
328
329#ifdef CONFIG_CPU_PM
330void output_pm_defines(void)
331{
332 COMMENT(" PM offsets. ");
333#ifdef CONFIG_EVA
334 OFFSET(SSS_SEGCTL0, mips_static_suspend_state, segctl[0]);
335 OFFSET(SSS_SEGCTL1, mips_static_suspend_state, segctl[1]);
336 OFFSET(SSS_SEGCTL2, mips_static_suspend_state, segctl[2]);
337#endif
338 OFFSET(SSS_SP, mips_static_suspend_state, sp);
339 BLANK();
340}
341#endif
342
343void output_kvm_defines(void)
344{
345 COMMENT(" KVM/MIPS Specific offsets. ");
346
347 OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
348 OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
349 OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]);
350 OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]);
351 OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]);
352 OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]);
353 OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]);
354 OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]);
355 OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]);
356 OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]);
357 OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]);
358 OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]);
359 OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]);
360 OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]);
361 OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]);
362 OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]);
363 OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]);
364 OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]);
365 OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]);
366 OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]);
367 OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]);
368 OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]);
369 OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]);
370 OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]);
371 OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]);
372 OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]);
373 OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]);
374 OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]);
375 OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]);
376 OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]);
377 OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]);
378 OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]);
379
380 OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
381 OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
382 BLANK();
383}
384
385#ifdef CONFIG_MIPS_CPS
386void output_cps_defines(void)
387{
388 COMMENT(" MIPS CPS offsets. ");
389
390 OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
391 OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
392 DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
393
394 OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
395 OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
396 OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
397 DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
398}
399#endif
400
