LXR linux/arch/powerpc/perf/power9-pmu.c

   1/*
   2 * Performance counter support for POWER9 processors.
   3 *
   4 * Copyright 2009 Paul Mackerras, IBM Corporation.
   5 * Copyright 2013 Michael Ellerman, IBM Corporation.
   6 * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License
  10 * as published by the Free Software Foundation; either version
  11 * 2 of the License, or later version.
  12 */
  13
  14#define pr_fmt(fmt)     "power9-pmu: " fmt
  15
  16#include "isa207-common.h"
  17
  18/*
  19 * Raw event encoding for Power9:
  20 *
  21 *        60        56        52        48        44        40        36        32
  22 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
  23 *   | | [ ]                       [ ] [      thresh_cmp     ]   [  thresh_ctl   ]
  24 *   | |  |                         |                                     |
  25 *   | |  *- IFM (Linux)            |                  thresh start/stop -*
  26 *   | *- BHRB (Linux)              *sm
  27 *   *- EBB (Linux)
  28 *
  29 *        28        24        20        16        12         8         4         0
  30 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
  31 *   [   ] [  sample ]   [cache]   [ pmc ]   [unit ]   []    m   [    pmcxsel    ]
  32 *     |        |           |                          |     |
  33 *     |        |           |                          |     *- mark
  34 *     |        |           *- L1/L2/L3 cache_sel      |
  35 *     |        |                                      |
  36 *     |        *- sampling mode for marked events     *- combine
  37 *     |
  38 *     *- thresh_sel
  39 *
  40 * Below uses IBM bit numbering.
  41 *
  42 * MMCR1[x:y] = unit    (PMCxUNIT)
  43 * MMCR1[24]   = pmc1combine[0]
  44 * MMCR1[25]   = pmc1combine[1]
  45 * MMCR1[26]   = pmc2combine[0]
  46 * MMCR1[27]   = pmc2combine[1]
  47 * MMCR1[28]   = pmc3combine[0]
  48 * MMCR1[29]   = pmc3combine[1]
  49 * MMCR1[30]   = pmc4combine[0]
  50 * MMCR1[31]   = pmc4combine[1]
  51 *
  52 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
  53 *      MMCR1[20:27] = thresh_ctl
  54 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
  55 *      MMCR1[20:27] = thresh_ctl
  56 * else
  57 *      MMCRA[48:55] = thresh_ctl   (THRESH START/END)
  58 *
  59 * if thresh_sel:
  60 *      MMCRA[45:47] = thresh_sel
  61 *
  62 * if thresh_cmp:
  63 *      MMCRA[9:11] = thresh_cmp[0:2]
  64 *      MMCRA[12:18] = thresh_cmp[3:9]
  65 *
  66 * if unit == 6 or unit == 7
  67 *      MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)
  68 * else if unit == 8 or unit == 9:
  69 *      if cache_sel[0] == 0: # L3 bank
  70 *              MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)
  71 *      else if cache_sel[0] == 1:
  72 *              MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)
  73 * else if cache_sel[1]: # L1 event
  74 *      MMCR1[16] = cache_sel[2]
  75 *      MMCR1[17] = cache_sel[3]
  76 *
  77 * if mark:
  78 *      MMCRA[63]    = 1                (SAMPLE_ENABLE)
  79 *      MMCRA[57:59] = sample[0:2]      (RAND_SAMP_ELIG)
  80 *      MMCRA[61:62] = sample[3:4]      (RAND_SAMP_MODE)
  81 *
  82 * if EBB and BHRB:
  83 *      MMCRA[32:33] = IFM
  84 *
  85 * MMCRA[SDAR_MODE]  = sm
  86 */
  87
  88/*
  89 * Some power9 event codes.
  90 */
  91#define EVENT(_name, _code)     _name = _code,
  92
  93enum {
  94#include "power9-events-list.h"
  95};
  96
  97#undef EVENT
  98
  99/* MMCRA IFM bits - POWER9 */
 100#define POWER9_MMCRA_IFM1               0x0000000040000000UL
 101#define POWER9_MMCRA_IFM2               0x0000000080000000UL
 102#define POWER9_MMCRA_IFM3               0x00000000C0000000UL
 103
 104/* PowerISA v2.07 format attribute structure*/
 105extern struct attribute_group isa207_pmu_format_group;
 106
 107/* Table of alternatives, sorted by column 0 */
 108static const unsigned int power9_event_alternatives[][MAX_ALT] = {
 109        { PM_INST_DISP,                 PM_INST_DISP_ALT },
 110};
 111
 112static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 113{
 114        int num_alt = 0;
 115
 116        num_alt = isa207_get_alternatives(event, alt, power9_event_alternatives,
 117                                (int)ARRAY_SIZE(power9_event_alternatives));
 118
 119        return num_alt;
 120}
 121
 122GENERIC_EVENT_ATTR(cpu-cycles,                  PM_CYC);
 123GENERIC_EVENT_ATTR(stalled-cycles-frontend,     PM_ICT_NOSLOT_CYC);
 124GENERIC_EVENT_ATTR(stalled-cycles-backend,      PM_CMPLU_STALL);
 125GENERIC_EVENT_ATTR(instructions,                PM_INST_CMPL);
 126GENERIC_EVENT_ATTR(branch-instructions,         PM_BRU_CMPL);
 127GENERIC_EVENT_ATTR(branch-misses,               PM_BR_MPRED_CMPL);
 128GENERIC_EVENT_ATTR(cache-references,            PM_LD_REF_L1);
 129GENERIC_EVENT_ATTR(cache-misses,                PM_LD_MISS_L1_FIN);
 130
 131CACHE_EVENT_ATTR(L1-dcache-load-misses,         PM_LD_MISS_L1_FIN);
 132CACHE_EVENT_ATTR(L1-dcache-loads,               PM_LD_REF_L1);
 133CACHE_EVENT_ATTR(L1-dcache-prefetches,          PM_L1_PREF);
 134CACHE_EVENT_ATTR(L1-dcache-store-misses,        PM_ST_MISS_L1);
 135CACHE_EVENT_ATTR(L1-icache-load-misses,         PM_L1_ICACHE_MISS);
 136CACHE_EVENT_ATTR(L1-icache-loads,               PM_INST_FROM_L1);
 137CACHE_EVENT_ATTR(L1-icache-prefetches,          PM_IC_PREF_WRITE);
 138CACHE_EVENT_ATTR(LLC-load-misses,               PM_DATA_FROM_L3MISS);
 139CACHE_EVENT_ATTR(LLC-loads,                     PM_DATA_FROM_L3);
 140CACHE_EVENT_ATTR(LLC-prefetches,                PM_L3_PREF_ALL);
 141CACHE_EVENT_ATTR(LLC-store-misses,              PM_L2_ST_MISS);
 142CACHE_EVENT_ATTR(LLC-stores,                    PM_L2_ST);
 143CACHE_EVENT_ATTR(branch-load-misses,            PM_BR_MPRED_CMPL);
 144CACHE_EVENT_ATTR(branch-loads,                  PM_BRU_CMPL);
 145CACHE_EVENT_ATTR(dTLB-load-misses,              PM_DTLB_MISS);
 146CACHE_EVENT_ATTR(iTLB-load-misses,              PM_ITLB_MISS);
 147
 148static struct attribute *power9_events_attr[] = {
 149        GENERIC_EVENT_PTR(PM_CYC),
 150        GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
 151        GENERIC_EVENT_PTR(PM_CMPLU_STALL),
 152        GENERIC_EVENT_PTR(PM_INST_CMPL),
 153        GENERIC_EVENT_PTR(PM_BRU_CMPL),
 154        GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
 155        GENERIC_EVENT_PTR(PM_LD_REF_L1),
 156        GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
 157        CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
 158        CACHE_EVENT_PTR(PM_LD_REF_L1),
 159        CACHE_EVENT_PTR(PM_L1_PREF),
 160        CACHE_EVENT_PTR(PM_ST_MISS_L1),
 161        CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
 162        CACHE_EVENT_PTR(PM_INST_FROM_L1),
 163        CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
 164        CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
 165        CACHE_EVENT_PTR(PM_DATA_FROM_L3),
 166        CACHE_EVENT_PTR(PM_L3_PREF_ALL),
 167        CACHE_EVENT_PTR(PM_L2_ST_MISS),
 168        CACHE_EVENT_PTR(PM_L2_ST),
 169        CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
 170        CACHE_EVENT_PTR(PM_BRU_CMPL),
 171        CACHE_EVENT_PTR(PM_DTLB_MISS),
 172        CACHE_EVENT_PTR(PM_ITLB_MISS),
 173        NULL
 174};
 175
 176static struct attribute_group power9_pmu_events_group = {
 177        .name = "events",
 178        .attrs = power9_events_attr,
 179};
 180
 181static const struct attribute_group *power9_isa207_pmu_attr_groups[] = {
 182        &isa207_pmu_format_group,
 183        &power9_pmu_events_group,
 184        NULL,
 185};
 186
 187PMU_FORMAT_ATTR(event,          "config:0-51");
 188PMU_FORMAT_ATTR(pmcxsel,        "config:0-7");
 189PMU_FORMAT_ATTR(mark,           "config:8");
 190PMU_FORMAT_ATTR(combine,        "config:10-11");
 191PMU_FORMAT_ATTR(unit,           "config:12-15");
 192PMU_FORMAT_ATTR(pmc,            "config:16-19");
 193PMU_FORMAT_ATTR(cache_sel,      "config:20-23");
 194PMU_FORMAT_ATTR(sample_mode,    "config:24-28");
 195PMU_FORMAT_ATTR(thresh_sel,     "config:29-31");
 196PMU_FORMAT_ATTR(thresh_stop,    "config:32-35");
 197PMU_FORMAT_ATTR(thresh_start,   "config:36-39");
 198PMU_FORMAT_ATTR(thresh_cmp,     "config:40-49");
 199PMU_FORMAT_ATTR(sdar_mode,      "config:50-51");
 200
 201static struct attribute *power9_pmu_format_attr[] = {
 202        &format_attr_event.attr,
 203        &format_attr_pmcxsel.attr,
 204        &format_attr_mark.attr,
 205        &format_attr_combine.attr,
 206        &format_attr_unit.attr,
 207        &format_attr_pmc.attr,
 208        &format_attr_cache_sel.attr,
 209        &format_attr_sample_mode.attr,
 210        &format_attr_thresh_sel.attr,
 211        &format_attr_thresh_stop.attr,
 212        &format_attr_thresh_start.attr,
 213        &format_attr_thresh_cmp.attr,
 214        &format_attr_sdar_mode.attr,
 215        NULL,
 216};
 217
 218static struct attribute_group power9_pmu_format_group = {
 219        .name = "format",
 220        .attrs = power9_pmu_format_attr,
 221};
 222
 223static const struct attribute_group *power9_pmu_attr_groups[] = {
 224        &power9_pmu_format_group,
 225        &power9_pmu_events_group,
 226        NULL,
 227};
 228
 229static int power9_generic_events_dd1[] = {
 230        [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
 231        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_ICT_NOSLOT_CYC,
 232        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
 233        [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_DISP,
 234        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BRU_CMPL,
 235        [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
 236        [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
 237        [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1_FIN,
 238};
 239
 240static int power9_generic_events[] = {
 241        [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
 242        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_ICT_NOSLOT_CYC,
 243        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
 244        [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
 245        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BRU_CMPL,
 246        [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
 247        [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
 248        [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1_FIN,
 249};
 250
 251static u64 power9_bhrb_filter_map(u64 branch_sample_type)
 252{
 253        u64 pmu_bhrb_filter = 0;
 254
 255        /* BHRB and regular PMU events share the same privilege state
 256         * filter configuration. BHRB is always recorded along with a
 257         * regular PMU event. As the privilege state filter is handled
 258         * in the basic PMC configuration of the accompanying regular
 259         * PMU event, we ignore any separate BHRB specific request.
 260         */
 261
 262        /* No branch filter requested */
 263        if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
 264                return pmu_bhrb_filter;
 265
 266        /* Invalid branch filter options - HW does not support */
 267        if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
 268                return -1;
 269
 270        if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
 271                return -1;
 272
 273        if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
 274                return -1;
 275
 276        if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
 277                pmu_bhrb_filter |= POWER9_MMCRA_IFM1;
 278                return pmu_bhrb_filter;
 279        }
 280
 281        /* Every thing else is unsupported */
 282        return -1;
 283}
 284
 285static void power9_config_bhrb(u64 pmu_bhrb_filter)
 286{
 287        /* Enable BHRB filter in PMU */
 288        mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
 289}
 290
 291#define C(x)    PERF_COUNT_HW_CACHE_##x
 292
 293/*
 294 * Table of generalized cache-related events.
 295 * 0 means not supported, -1 means nonsensical, other values
 296 * are event codes.
 297 */
 298static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 299        [ C(L1D) ] = {
 300                [ C(OP_READ) ] = {
 301                        [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
 302                        [ C(RESULT_MISS)   ] = PM_LD_MISS_L1_FIN,
 303                },
 304                [ C(OP_WRITE) ] = {
 305                        [ C(RESULT_ACCESS) ] = 0,
 306                        [ C(RESULT_MISS)   ] = PM_ST_MISS_L1,
 307                },
 308                [ C(OP_PREFETCH) ] = {
 309                        [ C(RESULT_ACCESS) ] = PM_L1_PREF,
 310                        [ C(RESULT_MISS)   ] = 0,
 311                },
 312        },
 313        [ C(L1I) ] = {
 314                [ C(OP_READ) ] = {
 315                        [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
 316                        [ C(RESULT_MISS)   ] = PM_L1_ICACHE_MISS,
 317                },
 318                [ C(OP_WRITE) ] = {
 319                        [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
 320                        [ C(RESULT_MISS)   ] = -1,
 321                },
 322                [ C(OP_PREFETCH) ] = {
 323                        [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
 324                        [ C(RESULT_MISS)   ] = 0,
 325                },
 326        },
 327        [ C(LL) ] = {
 328                [ C(OP_READ) ] = {
 329                        [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
 330                        [ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
 331                },
 332                [ C(OP_WRITE) ] = {
 333                        [ C(RESULT_ACCESS) ] = PM_L2_ST,
 334                        [ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
 335                },
 336                [ C(OP_PREFETCH) ] = {
 337                        [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
 338                        [ C(RESULT_MISS)   ] = 0,
 339                },
 340        },
 341        [ C(DTLB) ] = {
 342                [ C(OP_READ) ] = {
 343                        [ C(RESULT_ACCESS) ] = 0,
 344                        [ C(RESULT_MISS)   ] = PM_DTLB_MISS,
 345                },
 346                [ C(OP_WRITE) ] = {
 347                        [ C(RESULT_ACCESS) ] = -1,
 348                        [ C(RESULT_MISS)   ] = -1,
 349                },
 350                [ C(OP_PREFETCH) ] = {
 351                        [ C(RESULT_ACCESS) ] = -1,
 352                        [ C(RESULT_MISS)   ] = -1,
 353                },
 354        },
 355        [ C(ITLB) ] = {
 356                [ C(OP_READ) ] = {
 357                        [ C(RESULT_ACCESS) ] = 0,
 358                        [ C(RESULT_MISS)   ] = PM_ITLB_MISS,
 359                },
 360                [ C(OP_WRITE) ] = {
 361                        [ C(RESULT_ACCESS) ] = -1,
 362                        [ C(RESULT_MISS)   ] = -1,
 363                },
 364                [ C(OP_PREFETCH) ] = {
 365                        [ C(RESULT_ACCESS) ] = -1,
 366                        [ C(RESULT_MISS)   ] = -1,
 367                },
 368        },
 369        [ C(BPU) ] = {
 370                [ C(OP_READ) ] = {
 371                        [ C(RESULT_ACCESS) ] = PM_BRU_CMPL,
 372                        [ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
 373                },
 374                [ C(OP_WRITE) ] = {
 375                        [ C(RESULT_ACCESS) ] = -1,
 376                        [ C(RESULT_MISS)   ] = -1,
 377                },
 378                [ C(OP_PREFETCH) ] = {
 379                        [ C(RESULT_ACCESS) ] = -1,
 380                        [ C(RESULT_MISS)   ] = -1,
 381                },
 382        },
 383        [ C(NODE) ] = {
 384                [ C(OP_READ) ] = {
 385                        [ C(RESULT_ACCESS) ] = -1,
 386                        [ C(RESULT_MISS)   ] = -1,
 387                },
 388                [ C(OP_WRITE) ] = {
 389                        [ C(RESULT_ACCESS) ] = -1,
 390                        [ C(RESULT_MISS)   ] = -1,
 391                },
 392                [ C(OP_PREFETCH) ] = {
 393                        [ C(RESULT_ACCESS) ] = -1,
 394                        [ C(RESULT_MISS)   ] = -1,
 395                },
 396        },
 397};
 398
 399#undef C
 400
 401static struct power_pmu power9_isa207_pmu = {
 402        .name                   = "POWER9",
 403        .n_counter              = MAX_PMU_COUNTERS,
 404        .add_fields             = ISA207_ADD_FIELDS,
 405        .test_adder             = ISA207_TEST_ADDER,
 406        .compute_mmcr           = isa207_compute_mmcr,
 407        .config_bhrb            = power9_config_bhrb,
 408        .bhrb_filter_map        = power9_bhrb_filter_map,
 409        .get_constraint         = isa207_get_constraint,
 410        .get_alternatives       = power9_get_alternatives,
 411        .disable_pmc            = isa207_disable_pmc,
 412        .flags                  = PPMU_NO_SIAR | PPMU_ARCH_207S,
 413        .n_generic              = ARRAY_SIZE(power9_generic_events_dd1),
 414        .generic_events         = power9_generic_events_dd1,
 415        .cache_events           = &power9_cache_events,
 416        .attr_groups            = power9_isa207_pmu_attr_groups,
 417        .bhrb_nr                = 32,
 418};
 419
 420static struct power_pmu power9_pmu = {
 421        .name                   = "POWER9",
 422        .n_counter              = MAX_PMU_COUNTERS,
 423        .add_fields             = ISA207_ADD_FIELDS,
 424        .test_adder             = P9_DD1_TEST_ADDER,
 425        .compute_mmcr           = isa207_compute_mmcr,
 426        .config_bhrb            = power9_config_bhrb,
 427        .bhrb_filter_map        = power9_bhrb_filter_map,
 428        .get_constraint         = isa207_get_constraint,
 429        .get_alternatives       = power9_get_alternatives,
 430        .disable_pmc            = isa207_disable_pmc,
 431        .flags                  = PPMU_HAS_SIER | PPMU_ARCH_207S,
 432        .n_generic              = ARRAY_SIZE(power9_generic_events),
 433        .generic_events         = power9_generic_events,
 434        .cache_events           = &power9_cache_events,
 435        .attr_groups            = power9_pmu_attr_groups,
 436        .bhrb_nr                = 32,
 437};
 438
 439static int __init init_power9_pmu(void)
 440{
 441        int rc = 0;
 442
 443        /* Comes from cpu_specs[] */
 444        if (!cur_cpu_spec->oprofile_cpu_type ||
 445            strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
 446                return -ENODEV;
 447
 448        if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
 449                /*
 450                 * Since PM_INST_CMPL may not provide right counts in all
 451                 * sampling scenarios in power9 DD1, instead use PM_INST_DISP.
 452                 */
 453                EVENT_VAR(PM_INST_CMPL, _g).id = PM_INST_DISP;
 454                rc = register_power_pmu(&power9_isa207_pmu);
 455        } else {
 456                rc = register_power_pmu(&power9_pmu);
 457        }
 458
 459        if (rc)
 460                return rc;
 461
 462        /* Tell userspace that EBB is supported */
 463        cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
 464
 465        return 0;
 466}
 467early_initcall(init_power9_pmu);
 468