LXR linux/arch/x86/include/asm/irq

   1#ifndef _ASM_X86_IRQ_VECTORS_H
   2#define _ASM_X86_IRQ_VECTORS_H
   3
   4#include <linux/threads.h>
   5/*
   6 * Linux IRQ vector layout.
   7 *
   8 * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can
   9 * be defined by Linux. They are used as a jump table by the CPU when a
  10 * given vector is triggered - by a CPU-external, CPU-internal or
  11 * software-triggered event.
  12 *
  13 * Linux sets the kernel code address each entry jumps to early during
  14 * bootup, and never changes them. This is the general layout of the
  15 * IDT entries:
  16 *
  17 *  Vectors   0 ...  31 : system traps and exceptions - hardcoded events
  18 *  Vectors  32 ... 127 : device interrupts
  19 *  Vector  128         : legacy int80 syscall interface
  20 *  Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 except 204 : device interrupts
  21 *  Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts
  22 *
  23 * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
  24 *
  25 * This file enumerates the exact layout of them:
  26 */
  27
  28#define NMI_VECTOR                      0x02
  29#define MCE_VECTOR                      0x12
  30
  31/*
  32 * IDT vectors usable for external interrupt sources start at 0x20.
  33 * (0x80 is the syscall vector, 0x30-0x3f are for ISA)
  34 */
  35#define FIRST_EXTERNAL_VECTOR           0x20
  36/*
  37 * We start allocating at 0x21 to spread out vectors evenly between
  38 * priority levels. (0x80 is the syscall vector)
  39 */
  40#define VECTOR_OFFSET_START             1
  41
  42/*
  43 * Reserve the lowest usable vector (and hence lowest priority)  0x20 for
  44 * triggering cleanup after irq migration. 0x21-0x2f will still be used
  45 * for device interrupts.
  46 */
  47#define IRQ_MOVE_CLEANUP_VECTOR         FIRST_EXTERNAL_VECTOR
  48
  49#define IA32_SYSCALL_VECTOR             0x80
  50
  51/*
  52 * Vectors 0x30-0x3f are used for ISA interrupts.
  53 *   round up to the next 16-vector boundary
  54 */
  55#define ISA_IRQ_VECTOR(irq)             (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq)
  56
  57/*
  58 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
  59 *
  60 *  some of the following vectors are 'rare', they are merged
  61 *  into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
  62 *  TLB, reschedule and local APIC vectors are performance-critical.
  63 */
  64
  65#define SPURIOUS_APIC_VECTOR            0xff
  66/*
  67 * Sanity check
  68 */
  69#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
  70# error SPURIOUS_APIC_VECTOR definition error
  71#endif
  72
  73#define ERROR_APIC_VECTOR               0xfe
  74#define RESCHEDULE_VECTOR               0xfd
  75#define CALL_FUNCTION_VECTOR            0xfc
  76#define CALL_FUNCTION_SINGLE_VECTOR     0xfb
  77#define THERMAL_APIC_VECTOR             0xfa
  78#define THRESHOLD_APIC_VECTOR           0xf9
  79#define REBOOT_VECTOR                   0xf8
  80
  81/*
  82 * Generic system vector for platform specific use
  83 */
  84#define X86_PLATFORM_IPI_VECTOR         0xf7
  85
  86#define POSTED_INTR_WAKEUP_VECTOR       0xf1
  87/*
  88 * IRQ work vector:
  89 */
  90#define IRQ_WORK_VECTOR                 0xf6
  91
  92#define UV_BAU_MESSAGE                  0xf5
  93#define DEFERRED_ERROR_VECTOR           0xf4
  94
  95/* Vector on which hypervisor callbacks will be delivered */
  96#define HYPERVISOR_CALLBACK_VECTOR      0xf3
  97
  98/* Vector for KVM to deliver posted interrupt IPI */
  99#ifdef CONFIG_HAVE_KVM
 100#define POSTED_INTR_VECTOR              0xf2
 101#endif
 102
 103/*
 104 * Local APIC timer IRQ vector is on a different priority level,
 105 * to work around the 'lost local interrupt if more than 2 IRQ
 106 * sources per level' errata.
 107 */
 108#define LOCAL_TIMER_VECTOR              0xef
 109
 110#define NR_VECTORS                       256
 111
 112#ifdef CONFIG_X86_LOCAL_APIC
 113#define FIRST_SYSTEM_VECTOR             LOCAL_TIMER_VECTOR
 114#else
 115#define FIRST_SYSTEM_VECTOR             NR_VECTORS
 116#endif
 117
 118#define FPU_IRQ                           13
 119
 120/*
 121 * Size the maximum number of interrupts.
 122 *
 123 * If the irq_desc[] array has a sparse layout, we can size things
 124 * generously - it scales up linearly with the maximum number of CPUs,
 125 * and the maximum number of IO-APICs, whichever is higher.
 126 *
 127 * In other cases we size more conservatively, to not create too large
 128 * static arrays.
 129 */
 130
 131#define NR_IRQS_LEGACY                  16
 132
 133#define CPU_VECTOR_LIMIT                (64 * NR_CPUS)
 134#define IO_APIC_VECTOR_LIMIT            (32 * MAX_IO_APICS)
 135
 136#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_PCI_MSI)
 137#define NR_IRQS                                         \
 138        (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ?      \
 139                (NR_VECTORS + CPU_VECTOR_LIMIT)  :      \
 140                (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
 141#elif defined(CONFIG_X86_IO_APIC)
 142#define NR_IRQS                         (NR_VECTORS + IO_APIC_VECTOR_LIMIT)
 143#elif defined(CONFIG_PCI_MSI)
 144#define NR_IRQS                         (NR_VECTORS + CPU_VECTOR_LIMIT)
 145#else
 146#define NR_IRQS                         NR_IRQS_LEGACY
 147#endif
 148
 149#endif /* _ASM_X86_IRQ_VECTORS_H */
 150