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15#include <linux/clk.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/slab.h>
19#include <linux/mfd/syscon.h>
20#include <dt-bindings/clock/mt8135-clk.h>
21
22#include "clk-mtk.h"
23#include "clk-gate.h"
24
25static DEFINE_SPINLOCK(mt8135_clk_lock);
26
27static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
28 FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
29 FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
30 FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
31 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
32};
33
34static const struct mtk_fixed_factor top_divs[] __initconst = {
35 FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
36 FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
37 FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
38 FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
39
40 FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
41 FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
42 FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
43 FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
44 FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
45
46 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
47 FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
48 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
49 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
50 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
51 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
52
53 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
54 FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
55 FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
56 FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
57 FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
58 FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
59 FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
60 FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
61
62 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
63
64 FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
65 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
66
67 FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
68
69 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
70 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
71 FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
72 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
73 FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
74
75 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
76 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
77 FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
78 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
79
80 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
81 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
82 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
83 FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
84 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
85
86 FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
87 FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
88 FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
89 FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
90 FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
91
92 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
93 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
94 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
95
96 FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
97 FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
98
99 FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
100
101 FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
102 FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
103
104 FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
105 FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
106
107 FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
108};
109
110static const char * const axi_parents[] __initconst = {
111 "clk26m",
112 "syspll_d3",
113 "syspll_d4",
114 "syspll_d6",
115 "univpll_d5",
116 "univpll2_d2",
117 "syspll_d3p5"
118};
119
120static const char * const smi_parents[] __initconst = {
121 "clk26m",
122 "clkph_mck",
123 "syspll_d2p5",
124 "syspll_d3",
125 "syspll_d8",
126 "univpll_d5",
127 "univpll1_d2",
128 "univpll1_d6",
129 "mmpll_d3",
130 "mmpll_d4",
131 "mmpll_d5",
132 "mmpll_d6",
133 "mmpll_d7",
134 "vdecpll",
135 "lvdspll"
136};
137
138static const char * const mfg_parents[] __initconst = {
139 "clk26m",
140 "univpll1_d4",
141 "syspll_d2",
142 "syspll_d2p5",
143 "syspll_d3",
144 "univpll_d5",
145 "univpll1_d2",
146 "mmpll_d2",
147 "mmpll_d3",
148 "mmpll_d4",
149 "mmpll_d5",
150 "mmpll_d6",
151 "mmpll_d7"
152};
153
154static const char * const irda_parents[] __initconst = {
155 "clk26m",
156 "univpll2_d8",
157 "univpll1_d6"
158};
159
160static const char * const cam_parents[] __initconst = {
161 "clk26m",
162 "syspll_d3",
163 "syspll_d3p5",
164 "syspll_d4",
165 "univpll_d5",
166 "univpll2_d2",
167 "univpll_d7",
168 "univpll1_d4"
169};
170
171static const char * const aud_intbus_parents[] __initconst = {
172 "clk26m",
173 "syspll_d6",
174 "univpll_d10"
175};
176
177static const char * const jpg_parents[] __initconst = {
178 "clk26m",
179 "syspll_d5",
180 "syspll_d4",
181 "syspll_d3",
182 "univpll_d7",
183 "univpll2_d2",
184 "univpll_d5"
185};
186
187static const char * const disp_parents[] __initconst = {
188 "clk26m",
189 "syspll_d3p5",
190 "syspll_d3",
191 "univpll2_d2",
192 "univpll_d5",
193 "univpll1_d2",
194 "lvdspll",
195 "vdecpll"
196};
197
198static const char * const msdc30_parents[] __initconst = {
199 "clk26m",
200 "syspll_d6",
201 "syspll_d5",
202 "univpll1_d4",
203 "univpll2_d4",
204 "msdcpll"
205};
206
207static const char * const usb20_parents[] __initconst = {
208 "clk26m",
209 "univpll2_d6",
210 "univpll1_d10"
211};
212
213static const char * const venc_parents[] __initconst = {
214 "clk26m",
215 "syspll_d3",
216 "syspll_d8",
217 "univpll_d5",
218 "univpll1_d6",
219 "mmpll_d4",
220 "mmpll_d5",
221 "mmpll_d6"
222};
223
224static const char * const spi_parents[] __initconst = {
225 "clk26m",
226 "syspll_d6",
227 "syspll_d8",
228 "syspll_d10",
229 "univpll1_d6",
230 "univpll1_d8"
231};
232
233static const char * const uart_parents[] __initconst = {
234 "clk26m",
235 "univpll2_d8"
236};
237
238static const char * const mem_parents[] __initconst = {
239 "clk26m",
240 "clkph_mck"
241};
242
243static const char * const camtg_parents[] __initconst = {
244 "clk26m",
245 "univpll_d26",
246 "univpll1_d6",
247 "syspll_d16",
248 "syspll_d8"
249};
250
251static const char * const audio_parents[] __initconst = {
252 "clk26m",
253 "syspll_d24"
254};
255
256static const char * const fix_parents[] __initconst = {
257 "rtc32k",
258 "clk26m",
259 "univpll_d5",
260 "univpll_d7",
261 "univpll1_d2",
262 "univpll1_d4",
263 "univpll1_d6",
264 "univpll1_d8"
265};
266
267static const char * const vdec_parents[] __initconst = {
268 "clk26m",
269 "vdecpll",
270 "clkph_mck",
271 "syspll_d2p5",
272 "syspll_d3",
273 "syspll_d3p5",
274 "syspll_d4",
275 "syspll_d5",
276 "syspll_d6",
277 "syspll_d8",
278 "univpll1_d2",
279 "univpll2_d2",
280 "univpll_d7",
281 "univpll_d10",
282 "univpll2_d4",
283 "lvdspll"
284};
285
286static const char * const ddrphycfg_parents[] __initconst = {
287 "clk26m",
288 "axi_sel",
289 "syspll_d12"
290};
291
292static const char * const dpilvds_parents[] __initconst = {
293 "clk26m",
294 "lvdspll",
295 "lvdspll_d2",
296 "lvdspll_d4",
297 "lvdspll_d8"
298};
299
300static const char * const pmicspi_parents[] __initconst = {
301 "clk26m",
302 "univpll2_d6",
303 "syspll_d8",
304 "syspll_d10",
305 "univpll1_d10",
306 "mempll_mck_d4",
307 "univpll_d26",
308 "syspll_d24"
309};
310
311static const char * const smi_mfg_as_parents[] __initconst = {
312 "clk26m",
313 "smi_sel",
314 "mfg_sel",
315 "mem_sel"
316};
317
318static const char * const gcpu_parents[] __initconst = {
319 "clk26m",
320 "syspll_d4",
321 "univpll_d7",
322 "syspll_d5",
323 "syspll_d6"
324};
325
326static const char * const dpi1_parents[] __initconst = {
327 "clk26m",
328 "tvhdmi_h_ck",
329 "tvhdmi_d2",
330 "tvhdmi_d4"
331};
332
333static const char * const cci_parents[] __initconst = {
334 "clk26m",
335 "mainpll_537p3m",
336 "univpll_d3",
337 "syspll_d2p5",
338 "syspll_d3",
339 "syspll_d5"
340};
341
342static const char * const apll_parents[] __initconst = {
343 "clk26m",
344 "apll_ck",
345 "apll_d4",
346 "apll_d8",
347 "apll_d16",
348 "apll_d24"
349};
350
351static const char * const hdmipll_parents[] __initconst = {
352 "clk26m",
353 "hdmitx_clkdig_cts",
354 "hdmitx_clkdig_d2",
355 "hdmitx_clkdig_d3"
356};
357
358static const struct mtk_composite top_muxes[] __initconst = {
359
360 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
361 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
362 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
363 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
364 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
365
366 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
367 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
368 0x0144, 8, 2, 15),
369 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
370 MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
371
372 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
373 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
374 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
375 MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
376
377 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
378
379 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
380 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
381 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
382
383 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
384 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
385 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
386
387 MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
388 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
389 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
390 0x015c, 16, 2, 23),
391 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
392
393 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
394 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
395 MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
396 0x0164, 16, 2, 23),
397 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
398
399 MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
400 MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15),
401 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
402 MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
403};
404
405static const struct mtk_gate_regs infra_cg_regs = {
406 .set_ofs = 0x0040,
407 .clr_ofs = 0x0044,
408 .sta_ofs = 0x0048,
409};
410
411#define GATE_ICG(_id, _name, _parent, _shift) { \
412 .id = _id, \
413 .name = _name, \
414 .parent_name = _parent, \
415 .regs = &infra_cg_regs, \
416 .shift = _shift, \
417 .ops = &mtk_clk_gate_ops_setclr, \
418 }
419
420static const struct mtk_gate infra_clks[] __initconst = {
421 GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
422 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
423 GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
424 GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
425 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
426 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
427 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
428 GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
429 GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
430 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
431 GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
432 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
433 GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
434};
435
436static const struct mtk_gate_regs peri0_cg_regs = {
437 .set_ofs = 0x0008,
438 .clr_ofs = 0x0010,
439 .sta_ofs = 0x0018,
440};
441
442static const struct mtk_gate_regs peri1_cg_regs = {
443 .set_ofs = 0x000c,
444 .clr_ofs = 0x0014,
445 .sta_ofs = 0x001c,
446};
447
448#define GATE_PERI0(_id, _name, _parent, _shift) { \
449 .id = _id, \
450 .name = _name, \
451 .parent_name = _parent, \
452 .regs = &peri0_cg_regs, \
453 .shift = _shift, \
454 .ops = &mtk_clk_gate_ops_setclr, \
455 }
456
457#define GATE_PERI1(_id, _name, _parent, _shift) { \
458 .id = _id, \
459 .name = _name, \
460 .parent_name = _parent, \
461 .regs = &peri1_cg_regs, \
462 .shift = _shift, \
463 .ops = &mtk_clk_gate_ops_setclr, \
464 }
465
466static const struct mtk_gate peri_gates[] __initconst = {
467
468 GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
469 GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
470 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
471 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
472 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
473 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
474 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
475 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
476 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
477 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
478 GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
479 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
480 GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
481 GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
482 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
483 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
484 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
485 GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
486 GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
487 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
488 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
489 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
490 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
491 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
492 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
493 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
494 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
495 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
496 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
497 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
498 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
499 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
500
501 GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
502 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
503 GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
504 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
505 GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
506 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
507 GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
508 GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
509 GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
510};
511
512static const char * const uart_ck_sel_parents[] __initconst = {
513 "clk26m",
514 "uart_sel",
515};
516
517static const struct mtk_composite peri_clks[] __initconst = {
518 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
519 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
520 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
521 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
522};
523
524static void __init mtk_topckgen_init(struct device_node *node)
525{
526 struct clk_onecell_data *clk_data;
527 void __iomem *base;
528 int r;
529
530 base = of_iomap(node, 0);
531 if (!base) {
532 pr_err("%s(): ioremap failed\n", __func__);
533 return;
534 }
535
536 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
537
538 mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
539 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
540 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
541 &mt8135_clk_lock, clk_data);
542
543 clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]);
544
545 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
546 if (r)
547 pr_err("%s(): could not register clock provider: %d\n",
548 __func__, r);
549}
550CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
551
552static void __init mtk_infrasys_init(struct device_node *node)
553{
554 struct clk_onecell_data *clk_data;
555 int r;
556
557 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
558
559 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
560 clk_data);
561
562 clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
563
564 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
565 if (r)
566 pr_err("%s(): could not register clock provider: %d\n",
567 __func__, r);
568
569 mtk_register_reset_controller(node, 2, 0x30);
570}
571CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
572
573static void __init mtk_pericfg_init(struct device_node *node)
574{
575 struct clk_onecell_data *clk_data;
576 int r;
577 void __iomem *base;
578
579 base = of_iomap(node, 0);
580 if (!base) {
581 pr_err("%s(): ioremap failed\n", __func__);
582 return;
583 }
584
585 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
586
587 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
588 clk_data);
589 mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
590 &mt8135_clk_lock, clk_data);
591
592 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
593 if (r)
594 pr_err("%s(): could not register clock provider: %d\n",
595 __func__, r);
596
597 mtk_register_reset_controller(node, 2, 0);
598}
599CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
600
601#define MT8135_PLL_FMAX (2000 * MHZ)
602#define CON0_MT8135_RST_BAR BIT(27)
603
604#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
605 .id = _id, \
606 .name = _name, \
607 .reg = _reg, \
608 .pwr_reg = _pwr_reg, \
609 .en_mask = _en_mask, \
610 .flags = _flags, \
611 .rst_bar_mask = CON0_MT8135_RST_BAR, \
612 .fmax = MT8135_PLL_FMAX, \
613 .pcwbits = _pcwbits, \
614 .pd_reg = _pd_reg, \
615 .pd_shift = _pd_shift, \
616 .tuner_reg = _tuner_reg, \
617 .pcw_reg = _pcw_reg, \
618 .pcw_shift = _pcw_shift, \
619 }
620
621static const struct mtk_pll_data plls[] = {
622 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
623 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
624 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
625 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
626 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
627 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
628 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
629 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
630 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
631 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
632};
633
634static void __init mtk_apmixedsys_init(struct device_node *node)
635{
636 struct clk_onecell_data *clk_data;
637
638 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
639 if (!clk_data)
640 return;
641
642 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
643}
644CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys",
645 mtk_apmixedsys_init);
646
