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12#include <linux/slab.h>
13#include <linux/io.h>
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/of_address.h>
17#include <linux/of_device.h>
18#include <linux/syscore_ops.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21
22#include <dt-bindings/clock/exynos-audss-clk.h>
23
24static DEFINE_SPINLOCK(lock);
25static struct clk **clk_table;
26static void __iomem *reg_base;
27static struct clk_onecell_data clk_data;
28
29
30
31
32
33
34static struct clk *epll;
35
36#define ASS_CLK_SRC 0x0
37#define ASS_CLK_DIV 0x4
38#define ASS_CLK_GATE 0x8
39
40#ifdef CONFIG_PM_SLEEP
41static unsigned long reg_save[][2] = {
42 { ASS_CLK_SRC, 0 },
43 { ASS_CLK_DIV, 0 },
44 { ASS_CLK_GATE, 0 },
45};
46
47static int exynos_audss_clk_suspend(struct device *dev)
48{
49 int i;
50
51 for (i = 0; i < ARRAY_SIZE(reg_save); i++)
52 reg_save[i][1] = readl(reg_base + reg_save[i][0]);
53
54 return 0;
55}
56
57static int exynos_audss_clk_resume(struct device *dev)
58{
59 int i;
60
61 for (i = 0; i < ARRAY_SIZE(reg_save); i++)
62 writel(reg_save[i][1], reg_base + reg_save[i][0]);
63
64 return 0;
65}
66#endif
67
68struct exynos_audss_clk_drvdata {
69 unsigned int has_adma_clk:1;
70 unsigned int has_mst_clk:1;
71 unsigned int enable_epll:1;
72 unsigned int num_clks;
73};
74
75static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
76 .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
77};
78
79static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
80 .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
81 .has_mst_clk = 1,
82};
83
84static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
85 .num_clks = EXYNOS_AUDSS_MAX_CLKS,
86 .has_adma_clk = 1,
87 .enable_epll = 1,
88};
89
90static const struct of_device_id exynos_audss_clk_of_match[] = {
91 {
92 .compatible = "samsung,exynos4210-audss-clock",
93 .data = &exynos4210_drvdata,
94 }, {
95 .compatible = "samsung,exynos5250-audss-clock",
96 .data = &exynos4210_drvdata,
97 }, {
98 .compatible = "samsung,exynos5410-audss-clock",
99 .data = &exynos5410_drvdata,
100 }, {
101 .compatible = "samsung,exynos5420-audss-clock",
102 .data = &exynos5420_drvdata,
103 },
104 { },
105};
106MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
107
108static void exynos_audss_clk_teardown(void)
109{
110 int i;
111
112 for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
113 if (!IS_ERR(clk_table[i]))
114 clk_unregister_mux(clk_table[i]);
115 }
116
117 for (; i < EXYNOS_SRP_CLK; i++) {
118 if (!IS_ERR(clk_table[i]))
119 clk_unregister_divider(clk_table[i]);
120 }
121
122 for (; i < clk_data.clk_num; i++) {
123 if (!IS_ERR(clk_table[i]))
124 clk_unregister_gate(clk_table[i]);
125 }
126}
127
128
129static int exynos_audss_clk_probe(struct platform_device *pdev)
130{
131 const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
132 const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
133 const char *sclk_pcm_p = "sclk_pcm0";
134 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
135 const struct exynos_audss_clk_drvdata *variant;
136 struct resource *res;
137 int i, ret = 0;
138
139 variant = of_device_get_match_data(&pdev->dev);
140 if (!variant)
141 return -EINVAL;
142
143 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
144 reg_base = devm_ioremap_resource(&pdev->dev, res);
145 if (IS_ERR(reg_base)) {
146 dev_err(&pdev->dev, "failed to map audss registers\n");
147 return PTR_ERR(reg_base);
148 }
149
150 epll = ERR_PTR(-ENODEV);
151
152 clk_table = devm_kzalloc(&pdev->dev,
153 sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
154 GFP_KERNEL);
155 if (!clk_table)
156 return -ENOMEM;
157
158 clk_data.clks = clk_table;
159 clk_data.clk_num = variant->num_clks;
160
161 pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
162 pll_in = devm_clk_get(&pdev->dev, "pll_in");
163 if (!IS_ERR(pll_ref))
164 mout_audss_p[0] = __clk_get_name(pll_ref);
165 if (!IS_ERR(pll_in)) {
166 mout_audss_p[1] = __clk_get_name(pll_in);
167
168 if (variant->enable_epll) {
169 epll = pll_in;
170
171 ret = clk_prepare_enable(epll);
172 if (ret) {
173 dev_err(&pdev->dev,
174 "failed to prepare the epll clock\n");
175 return ret;
176 }
177 }
178 }
179 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
180 mout_audss_p, ARRAY_SIZE(mout_audss_p),
181 CLK_SET_RATE_NO_REPARENT,
182 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
183
184 cdclk = devm_clk_get(&pdev->dev, "cdclk");
185 sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
186 if (!IS_ERR(cdclk))
187 mout_i2s_p[1] = __clk_get_name(cdclk);
188 if (!IS_ERR(sclk_audio))
189 mout_i2s_p[2] = __clk_get_name(sclk_audio);
190 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
191 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
192 CLK_SET_RATE_NO_REPARENT,
193 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
194
195 clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
196 "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
197 0, &lock);
198
199 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
200 "dout_aud_bus", "dout_srp", 0,
201 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
202
203 clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
204 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
205 &lock);
206
207 clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
208 "dout_srp", CLK_SET_RATE_PARENT,
209 reg_base + ASS_CLK_GATE, 0, 0, &lock);
210
211 clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
212 "dout_aud_bus", CLK_SET_RATE_PARENT,
213 reg_base + ASS_CLK_GATE, 2, 0, &lock);
214
215 clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
216 "dout_i2s", CLK_SET_RATE_PARENT,
217 reg_base + ASS_CLK_GATE, 3, 0, &lock);
218
219 clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
220 "sclk_pcm", CLK_SET_RATE_PARENT,
221 reg_base + ASS_CLK_GATE, 4, 0, &lock);
222
223 sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
224 if (!IS_ERR(sclk_pcm_in))
225 sclk_pcm_p = __clk_get_name(sclk_pcm_in);
226 clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
227 sclk_pcm_p, CLK_SET_RATE_PARENT,
228 reg_base + ASS_CLK_GATE, 5, 0, &lock);
229
230 if (variant->has_adma_clk) {
231 clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
232 "dout_srp", CLK_SET_RATE_PARENT,
233 reg_base + ASS_CLK_GATE, 9, 0, &lock);
234 }
235
236 for (i = 0; i < clk_data.clk_num; i++) {
237 if (IS_ERR(clk_table[i])) {
238 dev_err(&pdev->dev, "failed to register clock %d\n", i);
239 ret = PTR_ERR(clk_table[i]);
240 goto unregister;
241 }
242 }
243
244 ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
245 &clk_data);
246 if (ret) {
247 dev_err(&pdev->dev, "failed to add clock provider\n");
248 goto unregister;
249 }
250
251 return 0;
252
253unregister:
254 exynos_audss_clk_teardown();
255
256 if (!IS_ERR(epll))
257 clk_disable_unprepare(epll);
258
259 return ret;
260}
261
262static int exynos_audss_clk_remove(struct platform_device *pdev)
263{
264 of_clk_del_provider(pdev->dev.of_node);
265
266 exynos_audss_clk_teardown();
267
268 if (!IS_ERR(epll))
269 clk_disable_unprepare(epll);
270
271 return 0;
272}
273
274static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
275 SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_audss_clk_suspend,
276 exynos_audss_clk_resume)
277};
278
279static struct platform_driver exynos_audss_clk_driver = {
280 .driver = {
281 .name = "exynos-audss-clk",
282 .of_match_table = exynos_audss_clk_of_match,
283 .pm = &exynos_audss_clk_pm_ops,
284 },
285 .probe = exynos_audss_clk_probe,
286 .remove = exynos_audss_clk_remove,
287};
288
289module_platform_driver(exynos_audss_clk_driver);
290
291MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
292MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
293MODULE_LICENSE("GPL v2");
294MODULE_ALIAS("platform:exynos-audss-clk");
295
