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24#include <linux/kernel.h>
25#include <linux/component.h>
26#include <drm/i915_component.h>
27#include <drm/intel_lpe_audio.h>
28#include "intel_drv.h"
29
30#include <drm/drmP.h>
31#include <drm/drm_edid.h>
32#include "i915_drv.h"
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62#define LC_540M 540000
63#define LC_270M 270000
64#define LC_162M 162000
65
66struct dp_aud_n_m {
67 int sample_rate;
68 int clock;
69 u16 m;
70 u16 n;
71};
72
73
74static const struct dp_aud_n_m dp_aud_n_m[] = {
75 { 32000, LC_162M, 1024, 10125 },
76 { 44100, LC_162M, 784, 5625 },
77 { 48000, LC_162M, 512, 3375 },
78 { 64000, LC_162M, 2048, 10125 },
79 { 88200, LC_162M, 1568, 5625 },
80 { 96000, LC_162M, 1024, 3375 },
81 { 128000, LC_162M, 4096, 10125 },
82 { 176400, LC_162M, 3136, 5625 },
83 { 192000, LC_162M, 2048, 3375 },
84 { 32000, LC_270M, 1024, 16875 },
85 { 44100, LC_270M, 784, 9375 },
86 { 48000, LC_270M, 512, 5625 },
87 { 64000, LC_270M, 2048, 16875 },
88 { 88200, LC_270M, 1568, 9375 },
89 { 96000, LC_270M, 1024, 5625 },
90 { 128000, LC_270M, 4096, 16875 },
91 { 176400, LC_270M, 3136, 9375 },
92 { 192000, LC_270M, 2048, 5625 },
93 { 32000, LC_540M, 1024, 33750 },
94 { 44100, LC_540M, 784, 18750 },
95 { 48000, LC_540M, 512, 11250 },
96 { 64000, LC_540M, 2048, 33750 },
97 { 88200, LC_540M, 1568, 18750 },
98 { 96000, LC_540M, 1024, 11250 },
99 { 128000, LC_540M, 4096, 33750 },
100 { 176400, LC_540M, 3136, 18750 },
101 { 192000, LC_540M, 2048, 11250 },
102};
103
104static const struct dp_aud_n_m *
105audio_config_dp_get_n_m(struct intel_crtc *intel_crtc, int rate)
106{
107 int i;
108
109 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
110 if (rate == dp_aud_n_m[i].sample_rate &&
111 intel_crtc->config->port_clock == dp_aud_n_m[i].clock)
112 return &dp_aud_n_m[i];
113 }
114
115 return NULL;
116}
117
118static const struct {
119 int clock;
120 u32 config;
121} hdmi_audio_clock[] = {
122 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
123 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 },
124 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
125 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
126 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
127 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
128 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
129 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
130 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
131 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
132};
133
134
135#define TMDS_297M 297000
136#define TMDS_296M 296703
137static const struct {
138 int sample_rate;
139 int clock;
140 int n;
141 int cts;
142} hdmi_aud_ncts[] = {
143 { 44100, TMDS_296M, 4459, 234375 },
144 { 44100, TMDS_297M, 4704, 247500 },
145 { 48000, TMDS_296M, 5824, 281250 },
146 { 48000, TMDS_297M, 5120, 247500 },
147 { 32000, TMDS_296M, 5824, 421875 },
148 { 32000, TMDS_297M, 3072, 222750 },
149 { 88200, TMDS_296M, 8918, 234375 },
150 { 88200, TMDS_297M, 9408, 247500 },
151 { 96000, TMDS_296M, 11648, 281250 },
152 { 96000, TMDS_297M, 10240, 247500 },
153 { 176400, TMDS_296M, 17836, 234375 },
154 { 176400, TMDS_297M, 18816, 247500 },
155 { 192000, TMDS_296M, 23296, 281250 },
156 { 192000, TMDS_297M, 20480, 247500 },
157};
158
159
160static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
161{
162 int i;
163
164 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
165 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
166 break;
167 }
168
169 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
170 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
171 adjusted_mode->crtc_clock);
172 i = 1;
173 }
174
175 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
176 hdmi_audio_clock[i].clock,
177 hdmi_audio_clock[i].config);
178
179 return hdmi_audio_clock[i].config;
180}
181
182static int audio_config_hdmi_get_n(const struct drm_display_mode *adjusted_mode,
183 int rate)
184{
185 int i;
186
187 for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
188 if (rate == hdmi_aud_ncts[i].sample_rate &&
189 adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
190 return hdmi_aud_ncts[i].n;
191 }
192 }
193 return 0;
194}
195
196static bool intel_eld_uptodate(struct drm_connector *connector,
197 i915_reg_t reg_eldv, uint32_t bits_eldv,
198 i915_reg_t reg_elda, uint32_t bits_elda,
199 i915_reg_t reg_edid)
200{
201 struct drm_i915_private *dev_priv = to_i915(connector->dev);
202 uint8_t *eld = connector->eld;
203 uint32_t tmp;
204 int i;
205
206 tmp = I915_READ(reg_eldv);
207 tmp &= bits_eldv;
208
209 if (!tmp)
210 return false;
211
212 tmp = I915_READ(reg_elda);
213 tmp &= ~bits_elda;
214 I915_WRITE(reg_elda, tmp);
215
216 for (i = 0; i < drm_eld_size(eld) / 4; i++)
217 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
218 return false;
219
220 return true;
221}
222
223static void g4x_audio_codec_disable(struct intel_encoder *encoder)
224{
225 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
226 uint32_t eldv, tmp;
227
228 DRM_DEBUG_KMS("Disable audio codec\n");
229
230 tmp = I915_READ(G4X_AUD_VID_DID);
231 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
232 eldv = G4X_ELDV_DEVCL_DEVBLC;
233 else
234 eldv = G4X_ELDV_DEVCTG;
235
236
237 tmp = I915_READ(G4X_AUD_CNTL_ST);
238 tmp &= ~eldv;
239 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
240}
241
242static void g4x_audio_codec_enable(struct drm_connector *connector,
243 struct intel_encoder *encoder,
244 const struct drm_display_mode *adjusted_mode)
245{
246 struct drm_i915_private *dev_priv = to_i915(connector->dev);
247 uint8_t *eld = connector->eld;
248 uint32_t eldv;
249 uint32_t tmp;
250 int len, i;
251
252 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
253
254 tmp = I915_READ(G4X_AUD_VID_DID);
255 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
256 eldv = G4X_ELDV_DEVCL_DEVBLC;
257 else
258 eldv = G4X_ELDV_DEVCTG;
259
260 if (intel_eld_uptodate(connector,
261 G4X_AUD_CNTL_ST, eldv,
262 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
263 G4X_HDMIW_HDMIEDID))
264 return;
265
266 tmp = I915_READ(G4X_AUD_CNTL_ST);
267 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
268 len = (tmp >> 9) & 0x1f;
269 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
270
271 len = min(drm_eld_size(eld) / 4, len);
272 DRM_DEBUG_DRIVER("ELD size %d\n", len);
273 for (i = 0; i < len; i++)
274 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
275
276 tmp = I915_READ(G4X_AUD_CNTL_ST);
277 tmp |= eldv;
278 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
279}
280
281static void
282hsw_dp_audio_config_update(struct intel_crtc *intel_crtc, enum port port,
283 const struct drm_display_mode *adjusted_mode)
284{
285 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
286 struct i915_audio_component *acomp = dev_priv->audio_component;
287 int rate = acomp ? acomp->aud_sample_rate[port] : 0;
288 const struct dp_aud_n_m *nm = audio_config_dp_get_n_m(intel_crtc, rate);
289 enum pipe pipe = intel_crtc->pipe;
290 u32 tmp;
291
292 if (nm)
293 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
294 else
295 DRM_DEBUG_KMS("using automatic Maud, Naud\n");
296
297 tmp = I915_READ(HSW_AUD_CFG(pipe));
298 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
299 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
300 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
301 tmp |= AUD_CONFIG_N_VALUE_INDEX;
302
303 if (nm) {
304 tmp &= ~AUD_CONFIG_N_MASK;
305 tmp |= AUD_CONFIG_N(nm->n);
306 tmp |= AUD_CONFIG_N_PROG_ENABLE;
307 }
308
309 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
310
311 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
312 tmp &= ~AUD_CONFIG_M_MASK;
313 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
314 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
315
316 if (nm) {
317 tmp |= nm->m;
318 tmp |= AUD_M_CTS_M_VALUE_INDEX;
319 tmp |= AUD_M_CTS_M_PROG_ENABLE;
320 }
321
322 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
323}
324
325static void
326hsw_hdmi_audio_config_update(struct intel_crtc *intel_crtc, enum port port,
327 const struct drm_display_mode *adjusted_mode)
328{
329 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
330 struct i915_audio_component *acomp = dev_priv->audio_component;
331 int rate = acomp ? acomp->aud_sample_rate[port] : 0;
332 enum pipe pipe = intel_crtc->pipe;
333 int n;
334 u32 tmp;
335
336 tmp = I915_READ(HSW_AUD_CFG(pipe));
337 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
338 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
339 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
340 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
341
342 n = audio_config_hdmi_get_n(adjusted_mode, rate);
343 if (n != 0) {
344 DRM_DEBUG_KMS("using N %d\n", n);
345
346 tmp &= ~AUD_CONFIG_N_MASK;
347 tmp |= AUD_CONFIG_N(n);
348 tmp |= AUD_CONFIG_N_PROG_ENABLE;
349 } else {
350 DRM_DEBUG_KMS("using automatic N\n");
351 }
352
353 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
354
355
356
357
358
359 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
360 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
361 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
362 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
363}
364
365static void
366hsw_audio_config_update(struct intel_crtc *intel_crtc, enum port port,
367 const struct drm_display_mode *adjusted_mode)
368{
369 if (intel_crtc_has_dp_encoder(intel_crtc->config))
370 hsw_dp_audio_config_update(intel_crtc, port, adjusted_mode);
371 else
372 hsw_hdmi_audio_config_update(intel_crtc, port, adjusted_mode);
373}
374
375static void hsw_audio_codec_disable(struct intel_encoder *encoder)
376{
377 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
378 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
379 enum pipe pipe = intel_crtc->pipe;
380 uint32_t tmp;
381
382 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
383
384 mutex_lock(&dev_priv->av_mutex);
385
386
387 tmp = I915_READ(HSW_AUD_CFG(pipe));
388 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
389 tmp |= AUD_CONFIG_N_PROG_ENABLE;
390 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
391 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
392 if (intel_crtc_has_dp_encoder(intel_crtc->config))
393 tmp |= AUD_CONFIG_N_VALUE_INDEX;
394 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
395
396
397 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
398 tmp &= ~AUDIO_ELD_VALID(pipe);
399 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
400 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
401
402 mutex_unlock(&dev_priv->av_mutex);
403}
404
405static void hsw_audio_codec_enable(struct drm_connector *connector,
406 struct intel_encoder *intel_encoder,
407 const struct drm_display_mode *adjusted_mode)
408{
409 struct drm_i915_private *dev_priv = to_i915(connector->dev);
410 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
411 enum pipe pipe = intel_crtc->pipe;
412 enum port port = intel_encoder->port;
413 const uint8_t *eld = connector->eld;
414 uint32_t tmp;
415 int len, i;
416
417 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
418 pipe_name(pipe), drm_eld_size(eld));
419
420 mutex_lock(&dev_priv->av_mutex);
421
422
423 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
424 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
425 tmp &= ~AUDIO_ELD_VALID(pipe);
426 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
427
428
429
430
431
432
433
434
435
436 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
437 tmp &= ~IBX_ELD_ADDRESS_MASK;
438 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
439
440
441 len = min(drm_eld_size(eld), 84);
442 for (i = 0; i < len / 4; i++)
443 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
444
445
446 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
447 tmp |= AUDIO_ELD_VALID(pipe);
448 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
449
450
451 hsw_audio_config_update(intel_crtc, port, adjusted_mode);
452
453 mutex_unlock(&dev_priv->av_mutex);
454}
455
456static void ilk_audio_codec_disable(struct intel_encoder *intel_encoder)
457{
458 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
459 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
460 enum pipe pipe = intel_crtc->pipe;
461 enum port port = intel_encoder->port;
462 uint32_t tmp, eldv;
463 i915_reg_t aud_config, aud_cntrl_st2;
464
465 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
466 port_name(port), pipe_name(pipe));
467
468 if (WARN_ON(port == PORT_A))
469 return;
470
471 if (HAS_PCH_IBX(dev_priv)) {
472 aud_config = IBX_AUD_CFG(pipe);
473 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
474 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
475 aud_config = VLV_AUD_CFG(pipe);
476 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
477 } else {
478 aud_config = CPT_AUD_CFG(pipe);
479 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
480 }
481
482
483 tmp = I915_READ(aud_config);
484 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
485 tmp |= AUD_CONFIG_N_PROG_ENABLE;
486 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
487 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
488 if (intel_crtc_has_dp_encoder(intel_crtc->config))
489 tmp |= AUD_CONFIG_N_VALUE_INDEX;
490 I915_WRITE(aud_config, tmp);
491
492 eldv = IBX_ELD_VALID(port);
493
494
495 tmp = I915_READ(aud_cntrl_st2);
496 tmp &= ~eldv;
497 I915_WRITE(aud_cntrl_st2, tmp);
498}
499
500static void ilk_audio_codec_enable(struct drm_connector *connector,
501 struct intel_encoder *intel_encoder,
502 const struct drm_display_mode *adjusted_mode)
503{
504 struct drm_i915_private *dev_priv = to_i915(connector->dev);
505 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
506 enum pipe pipe = intel_crtc->pipe;
507 enum port port = intel_encoder->port;
508 uint8_t *eld = connector->eld;
509 uint32_t tmp, eldv;
510 int len, i;
511 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
512
513 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
514 port_name(port), pipe_name(pipe), drm_eld_size(eld));
515
516 if (WARN_ON(port == PORT_A))
517 return;
518
519
520
521
522
523
524
525
526 if (HAS_PCH_IBX(dev_priv)) {
527 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
528 aud_config = IBX_AUD_CFG(pipe);
529 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
530 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
531 } else if (IS_VALLEYVIEW(dev_priv) ||
532 IS_CHERRYVIEW(dev_priv)) {
533 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
534 aud_config = VLV_AUD_CFG(pipe);
535 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
536 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
537 } else {
538 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
539 aud_config = CPT_AUD_CFG(pipe);
540 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
541 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
542 }
543
544 eldv = IBX_ELD_VALID(port);
545
546
547 tmp = I915_READ(aud_cntrl_st2);
548 tmp &= ~eldv;
549 I915_WRITE(aud_cntrl_st2, tmp);
550
551
552 tmp = I915_READ(aud_cntl_st);
553 tmp &= ~IBX_ELD_ADDRESS_MASK;
554 I915_WRITE(aud_cntl_st, tmp);
555
556
557 len = min(drm_eld_size(eld), 84);
558 for (i = 0; i < len / 4; i++)
559 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
560
561
562 tmp = I915_READ(aud_cntrl_st2);
563 tmp |= eldv;
564 I915_WRITE(aud_cntrl_st2, tmp);
565
566
567 tmp = I915_READ(aud_config);
568 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
569 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
570 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
571 if (intel_crtc_has_dp_encoder(intel_crtc->config))
572 tmp |= AUD_CONFIG_N_VALUE_INDEX;
573 else
574 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
575 I915_WRITE(aud_config, tmp);
576}
577
578
579
580
581
582
583
584
585
586
587void intel_audio_codec_enable(struct intel_encoder *intel_encoder,
588 const struct intel_crtc_state *crtc_state,
589 const struct drm_connector_state *conn_state)
590{
591 struct drm_encoder *encoder = &intel_encoder->base;
592 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
593 struct drm_connector *connector;
594 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
595 struct i915_audio_component *acomp = dev_priv->audio_component;
596 enum port port = intel_encoder->port;
597 enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
598
599 connector = conn_state->connector;
600 if (!connector || !connector->eld[0])
601 return;
602
603 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
604 connector->base.id,
605 connector->name,
606 connector->encoder->base.id,
607 connector->encoder->name);
608
609
610 connector->eld[5] &= ~(3 << 2);
611 if (intel_crtc_has_dp_encoder(crtc_state))
612 connector->eld[5] |= (1 << 2);
613
614 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
615
616 if (dev_priv->display.audio_codec_enable)
617 dev_priv->display.audio_codec_enable(connector, intel_encoder,
618 adjusted_mode);
619
620 mutex_lock(&dev_priv->av_mutex);
621 intel_encoder->audio_connector = connector;
622
623
624 dev_priv->av_enc_map[pipe] = intel_encoder;
625 mutex_unlock(&dev_priv->av_mutex);
626
627 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
628
629 if (intel_encoder->type != INTEL_OUTPUT_DP_MST)
630 pipe = -1;
631 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
632 (int) port, (int) pipe);
633 }
634
635 switch (intel_encoder->type) {
636 case INTEL_OUTPUT_HDMI:
637 intel_lpe_audio_notify(dev_priv, connector->eld, port, pipe,
638 crtc_state->port_clock,
639 false, 0);
640 break;
641 case INTEL_OUTPUT_DP:
642 intel_lpe_audio_notify(dev_priv, connector->eld, port, pipe,
643 adjusted_mode->crtc_clock,
644 true, crtc_state->port_clock);
645 break;
646 default:
647 break;
648 }
649}
650
651
652
653
654
655
656
657
658void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
659{
660 struct drm_encoder *encoder = &intel_encoder->base;
661 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
662 struct i915_audio_component *acomp = dev_priv->audio_component;
663 enum port port = intel_encoder->port;
664 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
665 enum pipe pipe = crtc->pipe;
666
667 if (dev_priv->display.audio_codec_disable)
668 dev_priv->display.audio_codec_disable(intel_encoder);
669
670 mutex_lock(&dev_priv->av_mutex);
671 intel_encoder->audio_connector = NULL;
672 dev_priv->av_enc_map[pipe] = NULL;
673 mutex_unlock(&dev_priv->av_mutex);
674
675 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
676
677 if (intel_encoder->type != INTEL_OUTPUT_DP_MST)
678 pipe = -1;
679 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
680 (int) port, (int) pipe);
681 }
682
683 intel_lpe_audio_notify(dev_priv, NULL, port, pipe, 0, false, 0);
684}
685
686
687
688
689
690void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
691{
692 if (IS_G4X(dev_priv)) {
693 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
694 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
695 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
696 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
697 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
698 } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
699 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
700 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
701 } else if (HAS_PCH_SPLIT(dev_priv)) {
702 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
703 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
704 }
705}
706
707static void i915_audio_component_get_power(struct device *kdev)
708{
709 intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
710}
711
712static void i915_audio_component_put_power(struct device *kdev)
713{
714 intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
715}
716
717static void i915_audio_component_codec_wake_override(struct device *kdev,
718 bool enable)
719{
720 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
721 u32 tmp;
722
723 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
724 return;
725
726 i915_audio_component_get_power(kdev);
727
728
729
730
731
732 tmp = I915_READ(HSW_AUD_CHICKENBIT);
733 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
734 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
735 usleep_range(1000, 1500);
736
737 if (enable) {
738 tmp = I915_READ(HSW_AUD_CHICKENBIT);
739 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
740 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
741 usleep_range(1000, 1500);
742 }
743
744 i915_audio_component_put_power(kdev);
745}
746
747
748static int i915_audio_component_get_cdclk_freq(struct device *kdev)
749{
750 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
751
752 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
753 return -ENODEV;
754
755 return dev_priv->cdclk_freq;
756}
757
758
759
760
761
762
763
764
765
766
767
768static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
769 int port, int pipe)
770{
771 struct intel_encoder *encoder;
772
773 if (WARN_ON(pipe >= I915_MAX_PIPES))
774 return NULL;
775
776
777 if (pipe >= 0) {
778 encoder = dev_priv->av_enc_map[pipe];
779
780
781
782
783
784 if (encoder != NULL && encoder->port == port &&
785 encoder->type == INTEL_OUTPUT_DP_MST)
786 return encoder;
787 }
788
789
790 if (pipe > 0)
791 return NULL;
792
793 for_each_pipe(dev_priv, pipe) {
794 encoder = dev_priv->av_enc_map[pipe];
795 if (encoder == NULL)
796 continue;
797
798 if (encoder->type == INTEL_OUTPUT_DP_MST)
799 continue;
800
801 if (port == encoder->port)
802 return encoder;
803 }
804
805 return NULL;
806}
807
808static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
809 int pipe, int rate)
810{
811 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
812 struct intel_encoder *intel_encoder;
813 struct intel_crtc *crtc;
814 struct drm_display_mode *adjusted_mode;
815 struct i915_audio_component *acomp = dev_priv->audio_component;
816 int err = 0;
817
818 if (!HAS_DDI(dev_priv))
819 return 0;
820
821 i915_audio_component_get_power(kdev);
822 mutex_lock(&dev_priv->av_mutex);
823
824
825 intel_encoder = get_saved_enc(dev_priv, port, pipe);
826 if (!intel_encoder || !intel_encoder->base.crtc) {
827 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
828 err = -ENODEV;
829 goto unlock;
830 }
831
832
833 crtc = to_intel_crtc(intel_encoder->base.crtc);
834 pipe = crtc->pipe;
835
836 adjusted_mode = &crtc->config->base.adjusted_mode;
837
838
839 acomp->aud_sample_rate[port] = rate;
840
841 hsw_audio_config_update(crtc, port, adjusted_mode);
842
843 unlock:
844 mutex_unlock(&dev_priv->av_mutex);
845 i915_audio_component_put_power(kdev);
846 return err;
847}
848
849static int i915_audio_component_get_eld(struct device *kdev, int port,
850 int pipe, bool *enabled,
851 unsigned char *buf, int max_bytes)
852{
853 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
854 struct intel_encoder *intel_encoder;
855 const u8 *eld;
856 int ret = -EINVAL;
857
858 mutex_lock(&dev_priv->av_mutex);
859
860 intel_encoder = get_saved_enc(dev_priv, port, pipe);
861 if (!intel_encoder) {
862 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
863 mutex_unlock(&dev_priv->av_mutex);
864 return ret;
865 }
866
867 ret = 0;
868 *enabled = intel_encoder->audio_connector != NULL;
869 if (*enabled) {
870 eld = intel_encoder->audio_connector->eld;
871 ret = drm_eld_size(eld);
872 memcpy(buf, eld, min(max_bytes, ret));
873 }
874
875 mutex_unlock(&dev_priv->av_mutex);
876 return ret;
877}
878
879static const struct i915_audio_component_ops i915_audio_component_ops = {
880 .owner = THIS_MODULE,
881 .get_power = i915_audio_component_get_power,
882 .put_power = i915_audio_component_put_power,
883 .codec_wake_override = i915_audio_component_codec_wake_override,
884 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
885 .sync_audio_rate = i915_audio_component_sync_audio_rate,
886 .get_eld = i915_audio_component_get_eld,
887};
888
889static int i915_audio_component_bind(struct device *i915_kdev,
890 struct device *hda_kdev, void *data)
891{
892 struct i915_audio_component *acomp = data;
893 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
894 int i;
895
896 if (WARN_ON(acomp->ops || acomp->dev))
897 return -EEXIST;
898
899 drm_modeset_lock_all(&dev_priv->drm);
900 acomp->ops = &i915_audio_component_ops;
901 acomp->dev = i915_kdev;
902 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
903 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
904 acomp->aud_sample_rate[i] = 0;
905 dev_priv->audio_component = acomp;
906 drm_modeset_unlock_all(&dev_priv->drm);
907
908 return 0;
909}
910
911static void i915_audio_component_unbind(struct device *i915_kdev,
912 struct device *hda_kdev, void *data)
913{
914 struct i915_audio_component *acomp = data;
915 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
916
917 drm_modeset_lock_all(&dev_priv->drm);
918 acomp->ops = NULL;
919 acomp->dev = NULL;
920 dev_priv->audio_component = NULL;
921 drm_modeset_unlock_all(&dev_priv->drm);
922}
923
924static const struct component_ops i915_audio_component_bind_ops = {
925 .bind = i915_audio_component_bind,
926 .unbind = i915_audio_component_unbind,
927};
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945void i915_audio_component_init(struct drm_i915_private *dev_priv)
946{
947 int ret;
948
949 if (INTEL_INFO(dev_priv)->num_pipes == 0)
950 return;
951
952 ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
953 if (ret < 0) {
954 DRM_ERROR("failed to add audio component (%d)\n", ret);
955
956 return;
957 }
958
959 dev_priv->audio_component_registered = true;
960}
961
962
963
964
965
966
967
968
969void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
970{
971 if (!dev_priv->audio_component_registered)
972 return;
973
974 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
975 dev_priv->audio_component_registered = false;
976}
977
978
979
980
981
982
983
984void intel_audio_init(struct drm_i915_private *dev_priv)
985{
986 if (intel_lpe_audio_init(dev_priv) < 0)
987 i915_audio_component_init(dev_priv);
988}
989
990
991
992
993
994
995void intel_audio_deinit(struct drm_i915_private *dev_priv)
996{
997 if ((dev_priv)->lpe_audio.platdev != NULL)
998 intel_lpe_audio_teardown(dev_priv);
999 else
1000 i915_audio_component_cleanup(dev_priv);
1001}
1002