linux/drivers/iio/accel/mma8452.c
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   1/*
   2 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
   3 *
   4 * device name  digital output  7-bit I2C slave address (pin selectable)
   5 * ---------------------------------------------------------------------
   6 * MMA8451Q     14 bit          0x1c / 0x1d
   7 * MMA8452Q     12 bit          0x1c / 0x1d
   8 * MMA8453Q     10 bit          0x1c / 0x1d
   9 * MMA8652FC    12 bit          0x1d
  10 * MMA8653FC    10 bit          0x1d
  11 * FXLS8471Q    14 bit          0x1e / 0x1d / 0x1c / 0x1f
  12 *
  13 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
  14 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
  15 *
  16 * This file is subject to the terms and conditions of version 2 of
  17 * the GNU General Public License.  See the file COPYING in the main
  18 * directory of this archive for more details.
  19 *
  20 * TODO: orientation events
  21 */
  22
  23#include <linux/module.h>
  24#include <linux/i2c.h>
  25#include <linux/iio/iio.h>
  26#include <linux/iio/sysfs.h>
  27#include <linux/iio/buffer.h>
  28#include <linux/iio/trigger.h>
  29#include <linux/iio/trigger_consumer.h>
  30#include <linux/iio/triggered_buffer.h>
  31#include <linux/iio/events.h>
  32#include <linux/delay.h>
  33#include <linux/of_device.h>
  34#include <linux/of_irq.h>
  35#include <linux/pm_runtime.h>
  36
  37#define MMA8452_STATUS                          0x00
  38#define  MMA8452_STATUS_DRDY                    (BIT(2) | BIT(1) | BIT(0))
  39#define MMA8452_OUT_X                           0x01 /* MSB first */
  40#define MMA8452_OUT_Y                           0x03
  41#define MMA8452_OUT_Z                           0x05
  42#define MMA8452_INT_SRC                         0x0c
  43#define MMA8452_WHO_AM_I                        0x0d
  44#define MMA8452_DATA_CFG                        0x0e
  45#define  MMA8452_DATA_CFG_FS_MASK               GENMASK(1, 0)
  46#define  MMA8452_DATA_CFG_FS_2G                 0
  47#define  MMA8452_DATA_CFG_FS_4G                 1
  48#define  MMA8452_DATA_CFG_FS_8G                 2
  49#define  MMA8452_DATA_CFG_HPF_MASK              BIT(4)
  50#define MMA8452_HP_FILTER_CUTOFF                0x0f
  51#define  MMA8452_HP_FILTER_CUTOFF_SEL_MASK      GENMASK(1, 0)
  52#define MMA8452_FF_MT_CFG                       0x15
  53#define  MMA8452_FF_MT_CFG_OAE                  BIT(6)
  54#define  MMA8452_FF_MT_CFG_ELE                  BIT(7)
  55#define MMA8452_FF_MT_SRC                       0x16
  56#define  MMA8452_FF_MT_SRC_XHE                  BIT(1)
  57#define  MMA8452_FF_MT_SRC_YHE                  BIT(3)
  58#define  MMA8452_FF_MT_SRC_ZHE                  BIT(5)
  59#define MMA8452_FF_MT_THS                       0x17
  60#define  MMA8452_FF_MT_THS_MASK                 0x7f
  61#define MMA8452_FF_MT_COUNT                     0x18
  62#define MMA8452_TRANSIENT_CFG                   0x1d
  63#define  MMA8452_TRANSIENT_CFG_HPF_BYP          BIT(0)
  64#define  MMA8452_TRANSIENT_CFG_ELE              BIT(4)
  65#define MMA8452_TRANSIENT_SRC                   0x1e
  66#define  MMA8452_TRANSIENT_SRC_XTRANSE          BIT(1)
  67#define  MMA8452_TRANSIENT_SRC_YTRANSE          BIT(3)
  68#define  MMA8452_TRANSIENT_SRC_ZTRANSE          BIT(5)
  69#define MMA8452_TRANSIENT_THS                   0x1f
  70#define  MMA8452_TRANSIENT_THS_MASK             GENMASK(6, 0)
  71#define MMA8452_TRANSIENT_COUNT                 0x20
  72#define MMA8452_CTRL_REG1                       0x2a
  73#define  MMA8452_CTRL_ACTIVE                    BIT(0)
  74#define  MMA8452_CTRL_DR_MASK                   GENMASK(5, 3)
  75#define  MMA8452_CTRL_DR_SHIFT                  3
  76#define  MMA8452_CTRL_DR_DEFAULT                0x4 /* 50 Hz sample frequency */
  77#define MMA8452_CTRL_REG2                       0x2b
  78#define  MMA8452_CTRL_REG2_RST                  BIT(6)
  79#define  MMA8452_CTRL_REG2_MODS_SHIFT           3
  80#define  MMA8452_CTRL_REG2_MODS_MASK            0x1b
  81#define MMA8452_CTRL_REG4                       0x2d
  82#define MMA8452_CTRL_REG5                       0x2e
  83#define MMA8452_OFF_X                           0x2f
  84#define MMA8452_OFF_Y                           0x30
  85#define MMA8452_OFF_Z                           0x31
  86
  87#define MMA8452_MAX_REG                         0x31
  88
  89#define  MMA8452_INT_DRDY                       BIT(0)
  90#define  MMA8452_INT_FF_MT                      BIT(2)
  91#define  MMA8452_INT_TRANS                      BIT(5)
  92
  93#define MMA8451_DEVICE_ID                       0x1a
  94#define MMA8452_DEVICE_ID                       0x2a
  95#define MMA8453_DEVICE_ID                       0x3a
  96#define MMA8652_DEVICE_ID                       0x4a
  97#define MMA8653_DEVICE_ID                       0x5a
  98#define FXLS8471_DEVICE_ID                      0x6a
  99
 100#define MMA8452_AUTO_SUSPEND_DELAY_MS           2000
 101
 102struct mma8452_data {
 103        struct i2c_client *client;
 104        struct mutex lock;
 105        u8 ctrl_reg1;
 106        u8 data_cfg;
 107        const struct mma_chip_info *chip_info;
 108};
 109
 110/**
 111 * struct mma_chip_info - chip specific data
 112 * @chip_id:                    WHO_AM_I register's value
 113 * @channels:                   struct iio_chan_spec matching the device's
 114 *                              capabilities
 115 * @num_channels:               number of channels
 116 * @mma_scales:                 scale factors for converting register values
 117 *                              to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
 118 *                              per mode: m/s^2 and micro m/s^2
 119 * @ev_cfg:                     event config register address
 120 * @ev_cfg_ele:                 latch bit in event config register
 121 * @ev_cfg_chan_shift:          number of the bit to enable events in X
 122 *                              direction; in event config register
 123 * @ev_src:                     event source register address
 124 * @ev_src_xe:                  bit in event source register that indicates
 125 *                              an event in X direction
 126 * @ev_src_ye:                  bit in event source register that indicates
 127 *                              an event in Y direction
 128 * @ev_src_ze:                  bit in event source register that indicates
 129 *                              an event in Z direction
 130 * @ev_ths:                     event threshold register address
 131 * @ev_ths_mask:                mask for the threshold value
 132 * @ev_count:                   event count (period) register address
 133 *
 134 * Since not all chips supported by the driver support comparing high pass
 135 * filtered data for events (interrupts), different interrupt sources are
 136 * used for different chips and the relevant registers are included here.
 137 */
 138struct mma_chip_info {
 139        u8 chip_id;
 140        const struct iio_chan_spec *channels;
 141        int num_channels;
 142        const int mma_scales[3][2];
 143        u8 ev_cfg;
 144        u8 ev_cfg_ele;
 145        u8 ev_cfg_chan_shift;
 146        u8 ev_src;
 147        u8 ev_src_xe;
 148        u8 ev_src_ye;
 149        u8 ev_src_ze;
 150        u8 ev_ths;
 151        u8 ev_ths_mask;
 152        u8 ev_count;
 153};
 154
 155enum {
 156        idx_x,
 157        idx_y,
 158        idx_z,
 159        idx_ts,
 160};
 161
 162static int mma8452_drdy(struct mma8452_data *data)
 163{
 164        int tries = 150;
 165
 166        while (tries-- > 0) {
 167                int ret = i2c_smbus_read_byte_data(data->client,
 168                        MMA8452_STATUS);
 169                if (ret < 0)
 170                        return ret;
 171                if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
 172                        return 0;
 173
 174                msleep(20);
 175        }
 176
 177        dev_err(&data->client->dev, "data not ready\n");
 178
 179        return -EIO;
 180}
 181
 182static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
 183{
 184#ifdef CONFIG_PM
 185        int ret;
 186
 187        if (on) {
 188                ret = pm_runtime_get_sync(&client->dev);
 189        } else {
 190                pm_runtime_mark_last_busy(&client->dev);
 191                ret = pm_runtime_put_autosuspend(&client->dev);
 192        }
 193
 194        if (ret < 0) {
 195                dev_err(&client->dev,
 196                        "failed to change power state to %d\n", on);
 197                if (on)
 198                        pm_runtime_put_noidle(&client->dev);
 199
 200                return ret;
 201        }
 202#endif
 203
 204        return 0;
 205}
 206
 207static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
 208{
 209        int ret = mma8452_drdy(data);
 210
 211        if (ret < 0)
 212                return ret;
 213
 214        ret = mma8452_set_runtime_pm_state(data->client, true);
 215        if (ret)
 216                return ret;
 217
 218        ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
 219                                            3 * sizeof(__be16), (u8 *)buf);
 220
 221        ret = mma8452_set_runtime_pm_state(data->client, false);
 222
 223        return ret;
 224}
 225
 226static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
 227                                            int n)
 228{
 229        size_t len = 0;
 230
 231        while (n-- > 0)
 232                len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
 233                                 vals[n][0], vals[n][1]);
 234
 235        /* replace trailing space by newline */
 236        buf[len - 1] = '\n';
 237
 238        return len;
 239}
 240
 241static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
 242                                             int val, int val2)
 243{
 244        while (n-- > 0)
 245                if (val == vals[n][0] && val2 == vals[n][1])
 246                        return n;
 247
 248        return -EINVAL;
 249}
 250
 251static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
 252{
 253        return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
 254                        MMA8452_CTRL_DR_SHIFT;
 255}
 256
 257static const int mma8452_samp_freq[8][2] = {
 258        {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
 259        {6, 250000}, {1, 560000}
 260};
 261
 262/* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
 263static const unsigned int mma8452_transient_time_step_us[4][8] = {
 264        { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 },  /* normal */
 265        { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 },  /* l p l n */
 266        { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 },       /* high res*/
 267        { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
 268};
 269
 270/* Datasheet table "High-Pass Filter Cutoff Options" */
 271static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
 272        { /* normal */
 273        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },            /* 800 Hz sample */
 274        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },            /* 400 Hz sample */
 275        { {8, 0}, {4, 0}, {2, 0}, {1, 0} },             /* 200 Hz sample */
 276        { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },        /* 100 Hz sample */
 277        { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },   /* 50 Hz sample */
 278        { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },   /* 12.5 Hz sample */
 279        { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },   /* 6.25 Hz sample */
 280        { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }    /* 1.56 Hz sample */
 281        },
 282        { /* low noise low power */
 283        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
 284        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
 285        { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
 286        { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
 287        { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
 288        { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
 289        { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
 290        { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
 291        },
 292        { /* high resolution */
 293        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
 294        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
 295        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
 296        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
 297        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
 298        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
 299        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
 300        { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
 301        },
 302        { /* low power */
 303        { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
 304        { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
 305        { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
 306        { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
 307        { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
 308        { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
 309        { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
 310        { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
 311        }
 312};
 313
 314/* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
 315static const u16 mma8452_os_ratio[4][8] = {
 316        /* 800 Hz, 400 Hz, ... , 1.56 Hz */
 317        { 2, 4, 4, 4, 4, 16, 32, 128 },         /* normal */
 318        { 2, 4, 4, 4, 4, 4, 8, 32 },            /* low power low noise */
 319        { 2, 4, 8, 16, 32, 128, 256, 1024 },    /* high resolution */
 320        { 2, 2, 2, 2, 2, 2, 4, 16 }             /* low power */
 321};
 322
 323static int mma8452_get_power_mode(struct mma8452_data *data)
 324{
 325        int reg;
 326
 327        reg = i2c_smbus_read_byte_data(data->client,
 328                                       MMA8452_CTRL_REG2);
 329        if (reg < 0)
 330                return reg;
 331
 332        return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
 333                MMA8452_CTRL_REG2_MODS_SHIFT);
 334}
 335
 336static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
 337                                            struct device_attribute *attr,
 338                                            char *buf)
 339{
 340        return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
 341                                            ARRAY_SIZE(mma8452_samp_freq));
 342}
 343
 344static ssize_t mma8452_show_scale_avail(struct device *dev,
 345                                        struct device_attribute *attr,
 346                                        char *buf)
 347{
 348        struct mma8452_data *data = iio_priv(i2c_get_clientdata(
 349                                             to_i2c_client(dev)));
 350
 351        return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
 352                ARRAY_SIZE(data->chip_info->mma_scales));
 353}
 354
 355static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
 356                                            struct device_attribute *attr,
 357                                            char *buf)
 358{
 359        struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 360        struct mma8452_data *data = iio_priv(indio_dev);
 361        int i, j;
 362
 363        i = mma8452_get_odr_index(data);
 364        j = mma8452_get_power_mode(data);
 365        if (j < 0)
 366                return j;
 367
 368        return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
 369                ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
 370}
 371
 372static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
 373                                           struct device_attribute *attr,
 374                                           char *buf)
 375{
 376        struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 377        struct mma8452_data *data = iio_priv(indio_dev);
 378        int i = mma8452_get_odr_index(data);
 379        int j;
 380        u16 val = 0;
 381        size_t len = 0;
 382
 383        for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
 384                if (val == mma8452_os_ratio[j][i])
 385                        continue;
 386
 387                val = mma8452_os_ratio[j][i];
 388
 389                len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
 390        }
 391        buf[len - 1] = '\n';
 392
 393        return len;
 394}
 395
 396static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
 397static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
 398                       mma8452_show_scale_avail, NULL, 0);
 399static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
 400                       S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
 401static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, S_IRUGO,
 402                       mma8452_show_os_ratio_avail, NULL, 0);
 403
 404static int mma8452_get_samp_freq_index(struct mma8452_data *data,
 405                                       int val, int val2)
 406{
 407        return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
 408                                                 ARRAY_SIZE(mma8452_samp_freq),
 409                                                 val, val2);
 410}
 411
 412static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
 413{
 414        return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
 415                        ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
 416}
 417
 418static int mma8452_get_hp_filter_index(struct mma8452_data *data,
 419                                       int val, int val2)
 420{
 421        int i, j;
 422
 423        i = mma8452_get_odr_index(data);
 424        j = mma8452_get_power_mode(data);
 425        if (j < 0)
 426                return j;
 427
 428        return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
 429                ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
 430}
 431
 432static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
 433{
 434        int j, i, ret;
 435
 436        ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
 437        if (ret < 0)
 438                return ret;
 439
 440        i = mma8452_get_odr_index(data);
 441        j = mma8452_get_power_mode(data);
 442        if (j < 0)
 443                return j;
 444
 445        ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
 446        *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
 447        *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
 448
 449        return 0;
 450}
 451
 452static int mma8452_read_raw(struct iio_dev *indio_dev,
 453                            struct iio_chan_spec const *chan,
 454                            int *val, int *val2, long mask)
 455{
 456        struct mma8452_data *data = iio_priv(indio_dev);
 457        __be16 buffer[3];
 458        int i, ret;
 459
 460        switch (mask) {
 461        case IIO_CHAN_INFO_RAW:
 462                ret = iio_device_claim_direct_mode(indio_dev);
 463                if (ret)
 464                        return ret;
 465
 466                mutex_lock(&data->lock);
 467                ret = mma8452_read(data, buffer);
 468                mutex_unlock(&data->lock);
 469                iio_device_release_direct_mode(indio_dev);
 470                if (ret < 0)
 471                        return ret;
 472
 473                *val = sign_extend32(be16_to_cpu(
 474                        buffer[chan->scan_index]) >> chan->scan_type.shift,
 475                        chan->scan_type.realbits - 1);
 476
 477                return IIO_VAL_INT;
 478        case IIO_CHAN_INFO_SCALE:
 479                i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
 480                *val = data->chip_info->mma_scales[i][0];
 481                *val2 = data->chip_info->mma_scales[i][1];
 482
 483                return IIO_VAL_INT_PLUS_MICRO;
 484        case IIO_CHAN_INFO_SAMP_FREQ:
 485                i = mma8452_get_odr_index(data);
 486                *val = mma8452_samp_freq[i][0];
 487                *val2 = mma8452_samp_freq[i][1];
 488
 489                return IIO_VAL_INT_PLUS_MICRO;
 490        case IIO_CHAN_INFO_CALIBBIAS:
 491                ret = i2c_smbus_read_byte_data(data->client,
 492                                               MMA8452_OFF_X +
 493                                               chan->scan_index);
 494                if (ret < 0)
 495                        return ret;
 496
 497                *val = sign_extend32(ret, 7);
 498
 499                return IIO_VAL_INT;
 500        case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
 501                if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
 502                        ret = mma8452_read_hp_filter(data, val, val2);
 503                        if (ret < 0)
 504                                return ret;
 505                } else {
 506                        *val = 0;
 507                        *val2 = 0;
 508                }
 509
 510                return IIO_VAL_INT_PLUS_MICRO;
 511        case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
 512                ret = mma8452_get_power_mode(data);
 513                if (ret < 0)
 514                        return ret;
 515
 516                i = mma8452_get_odr_index(data);
 517
 518                *val = mma8452_os_ratio[ret][i];
 519                return IIO_VAL_INT;
 520        }
 521
 522        return -EINVAL;
 523}
 524
 525static int mma8452_standby(struct mma8452_data *data)
 526{
 527        return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
 528                                        data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
 529}
 530
 531static int mma8452_active(struct mma8452_data *data)
 532{
 533        return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
 534                                         data->ctrl_reg1);
 535}
 536
 537/* returns >0 if active, 0 if in standby and <0 on error */
 538static int mma8452_is_active(struct mma8452_data *data)
 539{
 540        int reg;
 541
 542        reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
 543        if (reg < 0)
 544                return reg;
 545
 546        return reg & MMA8452_CTRL_ACTIVE;
 547}
 548
 549static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
 550{
 551        int ret;
 552        int is_active;
 553
 554        mutex_lock(&data->lock);
 555
 556        is_active = mma8452_is_active(data);
 557        if (is_active < 0) {
 558                ret = is_active;
 559                goto fail;
 560        }
 561
 562        /* config can only be changed when in standby */
 563        if (is_active > 0) {
 564                ret = mma8452_standby(data);
 565                if (ret < 0)
 566                        goto fail;
 567        }
 568
 569        ret = i2c_smbus_write_byte_data(data->client, reg, val);
 570        if (ret < 0)
 571                goto fail;
 572
 573        if (is_active > 0) {
 574                ret = mma8452_active(data);
 575                if (ret < 0)
 576                        goto fail;
 577        }
 578
 579        ret = 0;
 580fail:
 581        mutex_unlock(&data->lock);
 582
 583        return ret;
 584}
 585
 586static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
 587{
 588        int reg;
 589
 590        reg = i2c_smbus_read_byte_data(data->client,
 591                                       MMA8452_CTRL_REG2);
 592        if (reg < 0)
 593                return reg;
 594
 595        reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
 596        reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
 597
 598        return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
 599}
 600
 601/* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
 602static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
 603{
 604        int val;
 605        const struct mma_chip_info *chip = data->chip_info;
 606
 607        val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
 608        if (val < 0)
 609                return val;
 610
 611        return !(val & MMA8452_FF_MT_CFG_OAE);
 612}
 613
 614static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
 615{
 616        int val;
 617        const struct mma_chip_info *chip = data->chip_info;
 618
 619        if ((state && mma8452_freefall_mode_enabled(data)) ||
 620            (!state && !(mma8452_freefall_mode_enabled(data))))
 621                return 0;
 622
 623        val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
 624        if (val < 0)
 625                return val;
 626
 627        if (state) {
 628                val |= BIT(idx_x + chip->ev_cfg_chan_shift);
 629                val |= BIT(idx_y + chip->ev_cfg_chan_shift);
 630                val |= BIT(idx_z + chip->ev_cfg_chan_shift);
 631                val &= ~MMA8452_FF_MT_CFG_OAE;
 632        } else {
 633                val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
 634                val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
 635                val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
 636                val |= MMA8452_FF_MT_CFG_OAE;
 637        }
 638
 639        return mma8452_change_config(data, chip->ev_cfg, val);
 640}
 641
 642static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
 643                                           int val, int val2)
 644{
 645        int i, reg;
 646
 647        i = mma8452_get_hp_filter_index(data, val, val2);
 648        if (i < 0)
 649                return i;
 650
 651        reg = i2c_smbus_read_byte_data(data->client,
 652                                       MMA8452_HP_FILTER_CUTOFF);
 653        if (reg < 0)
 654                return reg;
 655
 656        reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
 657        reg |= i;
 658
 659        return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
 660}
 661
 662static int mma8452_write_raw(struct iio_dev *indio_dev,
 663                             struct iio_chan_spec const *chan,
 664                             int val, int val2, long mask)
 665{
 666        struct mma8452_data *data = iio_priv(indio_dev);
 667        int i, ret;
 668
 669        ret = iio_device_claim_direct_mode(indio_dev);
 670        if (ret)
 671                return ret;
 672
 673        switch (mask) {
 674        case IIO_CHAN_INFO_SAMP_FREQ:
 675                i = mma8452_get_samp_freq_index(data, val, val2);
 676                if (i < 0) {
 677                        ret = i;
 678                        break;
 679                }
 680                data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
 681                data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
 682
 683                ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
 684                                            data->ctrl_reg1);
 685                break;
 686        case IIO_CHAN_INFO_SCALE:
 687                i = mma8452_get_scale_index(data, val, val2);
 688                if (i < 0) {
 689                        ret = i;
 690                        break;
 691                }
 692
 693                data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
 694                data->data_cfg |= i;
 695
 696                ret = mma8452_change_config(data, MMA8452_DATA_CFG,
 697                                            data->data_cfg);
 698                break;
 699        case IIO_CHAN_INFO_CALIBBIAS:
 700                if (val < -128 || val > 127) {
 701                        ret = -EINVAL;
 702                        break;
 703                }
 704
 705                ret = mma8452_change_config(data,
 706                                            MMA8452_OFF_X + chan->scan_index,
 707                                            val);
 708                break;
 709
 710        case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
 711                if (val == 0 && val2 == 0) {
 712                        data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
 713                } else {
 714                        data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
 715                        ret = mma8452_set_hp_filter_frequency(data, val, val2);
 716                        if (ret < 0)
 717                                break;
 718                }
 719
 720                ret = mma8452_change_config(data, MMA8452_DATA_CFG,
 721                                             data->data_cfg);
 722                break;
 723
 724        case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
 725                ret = mma8452_get_odr_index(data);
 726
 727                for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
 728                        if (mma8452_os_ratio[i][ret] == val) {
 729                                ret = mma8452_set_power_mode(data, i);
 730                                break;
 731                        }
 732                }
 733                break;
 734        default:
 735                ret = -EINVAL;
 736                break;
 737        }
 738
 739        iio_device_release_direct_mode(indio_dev);
 740        return ret;
 741}
 742
 743static int mma8452_read_thresh(struct iio_dev *indio_dev,
 744                               const struct iio_chan_spec *chan,
 745                               enum iio_event_type type,
 746                               enum iio_event_direction dir,
 747                               enum iio_event_info info,
 748                               int *val, int *val2)
 749{
 750        struct mma8452_data *data = iio_priv(indio_dev);
 751        int ret, us, power_mode;
 752
 753        switch (info) {
 754        case IIO_EV_INFO_VALUE:
 755                ret = i2c_smbus_read_byte_data(data->client,
 756                                               data->chip_info->ev_ths);
 757                if (ret < 0)
 758                        return ret;
 759
 760                *val = ret & data->chip_info->ev_ths_mask;
 761
 762                return IIO_VAL_INT;
 763
 764        case IIO_EV_INFO_PERIOD:
 765                ret = i2c_smbus_read_byte_data(data->client,
 766                                               data->chip_info->ev_count);
 767                if (ret < 0)
 768                        return ret;
 769
 770                power_mode = mma8452_get_power_mode(data);
 771                if (power_mode < 0)
 772                        return power_mode;
 773
 774                us = ret * mma8452_transient_time_step_us[power_mode][
 775                                mma8452_get_odr_index(data)];
 776                *val = us / USEC_PER_SEC;
 777                *val2 = us % USEC_PER_SEC;
 778
 779                return IIO_VAL_INT_PLUS_MICRO;
 780
 781        case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
 782                ret = i2c_smbus_read_byte_data(data->client,
 783                                               MMA8452_TRANSIENT_CFG);
 784                if (ret < 0)
 785                        return ret;
 786
 787                if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
 788                        *val = 0;
 789                        *val2 = 0;
 790                } else {
 791                        ret = mma8452_read_hp_filter(data, val, val2);
 792                        if (ret < 0)
 793                                return ret;
 794                }
 795
 796                return IIO_VAL_INT_PLUS_MICRO;
 797
 798        default:
 799                return -EINVAL;
 800        }
 801}
 802
 803static int mma8452_write_thresh(struct iio_dev *indio_dev,
 804                                const struct iio_chan_spec *chan,
 805                                enum iio_event_type type,
 806                                enum iio_event_direction dir,
 807                                enum iio_event_info info,
 808                                int val, int val2)
 809{
 810        struct mma8452_data *data = iio_priv(indio_dev);
 811        int ret, reg, steps;
 812
 813        switch (info) {
 814        case IIO_EV_INFO_VALUE:
 815                if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
 816                        return -EINVAL;
 817
 818                return mma8452_change_config(data, data->chip_info->ev_ths,
 819                                             val);
 820
 821        case IIO_EV_INFO_PERIOD:
 822                ret = mma8452_get_power_mode(data);
 823                if (ret < 0)
 824                        return ret;
 825
 826                steps = (val * USEC_PER_SEC + val2) /
 827                                mma8452_transient_time_step_us[ret][
 828                                        mma8452_get_odr_index(data)];
 829
 830                if (steps < 0 || steps > 0xff)
 831                        return -EINVAL;
 832
 833                return mma8452_change_config(data, data->chip_info->ev_count,
 834                                             steps);
 835
 836        case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
 837                reg = i2c_smbus_read_byte_data(data->client,
 838                                               MMA8452_TRANSIENT_CFG);
 839                if (reg < 0)
 840                        return reg;
 841
 842                if (val == 0 && val2 == 0) {
 843                        reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
 844                } else {
 845                        reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
 846                        ret = mma8452_set_hp_filter_frequency(data, val, val2);
 847                        if (ret < 0)
 848                                return ret;
 849                }
 850
 851                return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
 852
 853        default:
 854                return -EINVAL;
 855        }
 856}
 857
 858static int mma8452_read_event_config(struct iio_dev *indio_dev,
 859                                     const struct iio_chan_spec *chan,
 860                                     enum iio_event_type type,
 861                                     enum iio_event_direction dir)
 862{
 863        struct mma8452_data *data = iio_priv(indio_dev);
 864        const struct mma_chip_info *chip = data->chip_info;
 865        int ret;
 866
 867        switch (dir) {
 868        case IIO_EV_DIR_FALLING:
 869                return mma8452_freefall_mode_enabled(data);
 870        case IIO_EV_DIR_RISING:
 871                if (mma8452_freefall_mode_enabled(data))
 872                        return 0;
 873
 874                ret = i2c_smbus_read_byte_data(data->client,
 875                                               data->chip_info->ev_cfg);
 876                if (ret < 0)
 877                        return ret;
 878
 879                return !!(ret & BIT(chan->scan_index +
 880                                    chip->ev_cfg_chan_shift));
 881        default:
 882                return -EINVAL;
 883        }
 884}
 885
 886static int mma8452_write_event_config(struct iio_dev *indio_dev,
 887                                      const struct iio_chan_spec *chan,
 888                                      enum iio_event_type type,
 889                                      enum iio_event_direction dir,
 890                                      int state)
 891{
 892        struct mma8452_data *data = iio_priv(indio_dev);
 893        const struct mma_chip_info *chip = data->chip_info;
 894        int val, ret;
 895
 896        ret = mma8452_set_runtime_pm_state(data->client, state);
 897        if (ret)
 898                return ret;
 899
 900        switch (dir) {
 901        case IIO_EV_DIR_FALLING:
 902                return mma8452_set_freefall_mode(data, state);
 903        case IIO_EV_DIR_RISING:
 904                val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
 905                if (val < 0)
 906                        return val;
 907
 908                if (state) {
 909                        if (mma8452_freefall_mode_enabled(data)) {
 910                                val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
 911                                val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
 912                                val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
 913                                val |= MMA8452_FF_MT_CFG_OAE;
 914                        }
 915                        val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
 916                } else {
 917                        if (mma8452_freefall_mode_enabled(data))
 918                                return 0;
 919
 920                        val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
 921                }
 922
 923                val |= chip->ev_cfg_ele;
 924
 925                return mma8452_change_config(data, chip->ev_cfg, val);
 926        default:
 927                return -EINVAL;
 928        }
 929}
 930
 931static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
 932{
 933        struct mma8452_data *data = iio_priv(indio_dev);
 934        s64 ts = iio_get_time_ns(indio_dev);
 935        int src;
 936
 937        src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
 938        if (src < 0)
 939                return;
 940
 941        if (mma8452_freefall_mode_enabled(data)) {
 942                iio_push_event(indio_dev,
 943                               IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
 944                                                  IIO_MOD_X_AND_Y_AND_Z,
 945                                                  IIO_EV_TYPE_MAG,
 946                                                  IIO_EV_DIR_FALLING),
 947                               ts);
 948                return;
 949        }
 950
 951        if (src & data->chip_info->ev_src_xe)
 952                iio_push_event(indio_dev,
 953                               IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
 954                                                  IIO_EV_TYPE_MAG,
 955                                                  IIO_EV_DIR_RISING),
 956                               ts);
 957
 958        if (src & data->chip_info->ev_src_ye)
 959                iio_push_event(indio_dev,
 960                               IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
 961                                                  IIO_EV_TYPE_MAG,
 962                                                  IIO_EV_DIR_RISING),
 963                               ts);
 964
 965        if (src & data->chip_info->ev_src_ze)
 966                iio_push_event(indio_dev,
 967                               IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
 968                                                  IIO_EV_TYPE_MAG,
 969                                                  IIO_EV_DIR_RISING),
 970                               ts);
 971}
 972
 973static irqreturn_t mma8452_interrupt(int irq, void *p)
 974{
 975        struct iio_dev *indio_dev = p;
 976        struct mma8452_data *data = iio_priv(indio_dev);
 977        const struct mma_chip_info *chip = data->chip_info;
 978        int ret = IRQ_NONE;
 979        int src;
 980
 981        src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
 982        if (src < 0)
 983                return IRQ_NONE;
 984
 985        if (src & MMA8452_INT_DRDY) {
 986                iio_trigger_poll_chained(indio_dev->trig);
 987                ret = IRQ_HANDLED;
 988        }
 989
 990        if ((src & MMA8452_INT_TRANS &&
 991             chip->ev_src == MMA8452_TRANSIENT_SRC) ||
 992            (src & MMA8452_INT_FF_MT &&
 993             chip->ev_src == MMA8452_FF_MT_SRC)) {
 994                mma8452_transient_interrupt(indio_dev);
 995                ret = IRQ_HANDLED;
 996        }
 997
 998        return ret;
 999}
1000
1001static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1002{
1003        struct iio_poll_func *pf = p;
1004        struct iio_dev *indio_dev = pf->indio_dev;
1005        struct mma8452_data *data = iio_priv(indio_dev);
1006        u8 buffer[16]; /* 3 16-bit channels + padding + ts */
1007        int ret;
1008
1009        ret = mma8452_read(data, (__be16 *)buffer);
1010        if (ret < 0)
1011                goto done;
1012
1013        iio_push_to_buffers_with_timestamp(indio_dev, buffer,
1014                                           iio_get_time_ns(indio_dev));
1015
1016done:
1017        iio_trigger_notify_done(indio_dev->trig);
1018
1019        return IRQ_HANDLED;
1020}
1021
1022static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1023                                  unsigned reg, unsigned writeval,
1024                                  unsigned *readval)
1025{
1026        int ret;
1027        struct mma8452_data *data = iio_priv(indio_dev);
1028
1029        if (reg > MMA8452_MAX_REG)
1030                return -EINVAL;
1031
1032        if (!readval)
1033                return mma8452_change_config(data, reg, writeval);
1034
1035        ret = i2c_smbus_read_byte_data(data->client, reg);
1036        if (ret < 0)
1037                return ret;
1038
1039        *readval = ret;
1040
1041        return 0;
1042}
1043
1044static const struct iio_event_spec mma8452_freefall_event[] = {
1045        {
1046                .type = IIO_EV_TYPE_MAG,
1047                .dir = IIO_EV_DIR_FALLING,
1048                .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1049                .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1050                                        BIT(IIO_EV_INFO_PERIOD) |
1051                                        BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1052        },
1053};
1054
1055static const struct iio_event_spec mma8652_freefall_event[] = {
1056        {
1057                .type = IIO_EV_TYPE_MAG,
1058                .dir = IIO_EV_DIR_FALLING,
1059                .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1060                .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1061                                        BIT(IIO_EV_INFO_PERIOD)
1062        },
1063};
1064
1065static const struct iio_event_spec mma8452_transient_event[] = {
1066        {
1067                .type = IIO_EV_TYPE_MAG,
1068                .dir = IIO_EV_DIR_RISING,
1069                .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1070                .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1071                                        BIT(IIO_EV_INFO_PERIOD) |
1072                                        BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1073        },
1074};
1075
1076static const struct iio_event_spec mma8452_motion_event[] = {
1077        {
1078                .type = IIO_EV_TYPE_MAG,
1079                .dir = IIO_EV_DIR_RISING,
1080                .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1081                .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1082                                        BIT(IIO_EV_INFO_PERIOD)
1083        },
1084};
1085
1086/*
1087 * Threshold is configured in fixed 8G/127 steps regardless of
1088 * currently selected scale for measurement.
1089 */
1090static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1091
1092static struct attribute *mma8452_event_attributes[] = {
1093        &iio_const_attr_accel_transient_scale.dev_attr.attr,
1094        NULL,
1095};
1096
1097static struct attribute_group mma8452_event_attribute_group = {
1098        .attrs = mma8452_event_attributes,
1099};
1100
1101#define MMA8452_FREEFALL_CHANNEL(modifier) { \
1102        .type = IIO_ACCEL, \
1103        .modified = 1, \
1104        .channel2 = modifier, \
1105        .scan_index = -1, \
1106        .event_spec = mma8452_freefall_event, \
1107        .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1108}
1109
1110#define MMA8652_FREEFALL_CHANNEL(modifier) { \
1111        .type = IIO_ACCEL, \
1112        .modified = 1, \
1113        .channel2 = modifier, \
1114        .scan_index = -1, \
1115        .event_spec = mma8652_freefall_event, \
1116        .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1117}
1118
1119#define MMA8452_CHANNEL(axis, idx, bits) { \
1120        .type = IIO_ACCEL, \
1121        .modified = 1, \
1122        .channel2 = IIO_MOD_##axis, \
1123        .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1124                              BIT(IIO_CHAN_INFO_CALIBBIAS), \
1125        .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1126                        BIT(IIO_CHAN_INFO_SCALE) | \
1127                        BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1128                        BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1129        .scan_index = idx, \
1130        .scan_type = { \
1131                .sign = 's', \
1132                .realbits = (bits), \
1133                .storagebits = 16, \
1134                .shift = 16 - (bits), \
1135                .endianness = IIO_BE, \
1136        }, \
1137        .event_spec = mma8452_transient_event, \
1138        .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1139}
1140
1141#define MMA8652_CHANNEL(axis, idx, bits) { \
1142        .type = IIO_ACCEL, \
1143        .modified = 1, \
1144        .channel2 = IIO_MOD_##axis, \
1145        .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1146                BIT(IIO_CHAN_INFO_CALIBBIAS), \
1147        .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1148                BIT(IIO_CHAN_INFO_SCALE) | \
1149                BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1150        .scan_index = idx, \
1151        .scan_type = { \
1152                .sign = 's', \
1153                .realbits = (bits), \
1154                .storagebits = 16, \
1155                .shift = 16 - (bits), \
1156                .endianness = IIO_BE, \
1157        }, \
1158        .event_spec = mma8452_motion_event, \
1159        .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1160}
1161
1162static const struct iio_chan_spec mma8451_channels[] = {
1163        MMA8452_CHANNEL(X, idx_x, 14),
1164        MMA8452_CHANNEL(Y, idx_y, 14),
1165        MMA8452_CHANNEL(Z, idx_z, 14),
1166        IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1167        MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1168};
1169
1170static const struct iio_chan_spec mma8452_channels[] = {
1171        MMA8452_CHANNEL(X, idx_x, 12),
1172        MMA8452_CHANNEL(Y, idx_y, 12),
1173        MMA8452_CHANNEL(Z, idx_z, 12),
1174        IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1175        MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1176};
1177
1178static const struct iio_chan_spec mma8453_channels[] = {
1179        MMA8452_CHANNEL(X, idx_x, 10),
1180        MMA8452_CHANNEL(Y, idx_y, 10),
1181        MMA8452_CHANNEL(Z, idx_z, 10),
1182        IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1183        MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1184};
1185
1186static const struct iio_chan_spec mma8652_channels[] = {
1187        MMA8652_CHANNEL(X, idx_x, 12),
1188        MMA8652_CHANNEL(Y, idx_y, 12),
1189        MMA8652_CHANNEL(Z, idx_z, 12),
1190        IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1191        MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1192};
1193
1194static const struct iio_chan_spec mma8653_channels[] = {
1195        MMA8652_CHANNEL(X, idx_x, 10),
1196        MMA8652_CHANNEL(Y, idx_y, 10),
1197        MMA8652_CHANNEL(Z, idx_z, 10),
1198        IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1199        MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1200};
1201
1202enum {
1203        mma8451,
1204        mma8452,
1205        mma8453,
1206        mma8652,
1207        mma8653,
1208        fxls8471,
1209};
1210
1211static const struct mma_chip_info mma_chip_info_table[] = {
1212        [mma8451] = {
1213                .chip_id = MMA8451_DEVICE_ID,
1214                .channels = mma8451_channels,
1215                .num_channels = ARRAY_SIZE(mma8451_channels),
1216                /*
1217                 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1218                 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1219                 * bit.
1220                 * The userspace interface uses m/s^2 and we declare micro units
1221                 * So scale factor for 12 bit here is given by:
1222                 *      g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1223                 */
1224                .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1225                .ev_cfg = MMA8452_TRANSIENT_CFG,
1226                .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1227                .ev_cfg_chan_shift = 1,
1228                .ev_src = MMA8452_TRANSIENT_SRC,
1229                .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1230                .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1231                .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1232                .ev_ths = MMA8452_TRANSIENT_THS,
1233                .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1234                .ev_count = MMA8452_TRANSIENT_COUNT,
1235        },
1236        [mma8452] = {
1237                .chip_id = MMA8452_DEVICE_ID,
1238                .channels = mma8452_channels,
1239                .num_channels = ARRAY_SIZE(mma8452_channels),
1240                .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1241                .ev_cfg = MMA8452_TRANSIENT_CFG,
1242                .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1243                .ev_cfg_chan_shift = 1,
1244                .ev_src = MMA8452_TRANSIENT_SRC,
1245                .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1246                .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1247                .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1248                .ev_ths = MMA8452_TRANSIENT_THS,
1249                .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1250                .ev_count = MMA8452_TRANSIENT_COUNT,
1251        },
1252        [mma8453] = {
1253                .chip_id = MMA8453_DEVICE_ID,
1254                .channels = mma8453_channels,
1255                .num_channels = ARRAY_SIZE(mma8453_channels),
1256                .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1257                .ev_cfg = MMA8452_TRANSIENT_CFG,
1258                .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1259                .ev_cfg_chan_shift = 1,
1260                .ev_src = MMA8452_TRANSIENT_SRC,
1261                .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1262                .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1263                .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1264                .ev_ths = MMA8452_TRANSIENT_THS,
1265                .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1266                .ev_count = MMA8452_TRANSIENT_COUNT,
1267        },
1268        [mma8652] = {
1269                .chip_id = MMA8652_DEVICE_ID,
1270                .channels = mma8652_channels,
1271                .num_channels = ARRAY_SIZE(mma8652_channels),
1272                .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1273                .ev_cfg = MMA8452_FF_MT_CFG,
1274                .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1275                .ev_cfg_chan_shift = 3,
1276                .ev_src = MMA8452_FF_MT_SRC,
1277                .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1278                .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1279                .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1280                .ev_ths = MMA8452_FF_MT_THS,
1281                .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1282                .ev_count = MMA8452_FF_MT_COUNT,
1283        },
1284        [mma8653] = {
1285                .chip_id = MMA8653_DEVICE_ID,
1286                .channels = mma8653_channels,
1287                .num_channels = ARRAY_SIZE(mma8653_channels),
1288                .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1289                .ev_cfg = MMA8452_FF_MT_CFG,
1290                .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1291                .ev_cfg_chan_shift = 3,
1292                .ev_src = MMA8452_FF_MT_SRC,
1293                .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1294                .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1295                .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1296                .ev_ths = MMA8452_FF_MT_THS,
1297                .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1298                .ev_count = MMA8452_FF_MT_COUNT,
1299        },
1300        [fxls8471] = {
1301                .chip_id = FXLS8471_DEVICE_ID,
1302                .channels = mma8451_channels,
1303                .num_channels = ARRAY_SIZE(mma8451_channels),
1304                .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1305                .ev_cfg = MMA8452_TRANSIENT_CFG,
1306                .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1307                .ev_cfg_chan_shift = 1,
1308                .ev_src = MMA8452_TRANSIENT_SRC,
1309                .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1310                .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1311                .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1312                .ev_ths = MMA8452_TRANSIENT_THS,
1313                .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1314                .ev_count = MMA8452_TRANSIENT_COUNT,
1315        },
1316};
1317
1318static struct attribute *mma8452_attributes[] = {
1319        &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1320        &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1321        &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1322        &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1323        NULL
1324};
1325
1326static const struct attribute_group mma8452_group = {
1327        .attrs = mma8452_attributes,
1328};
1329
1330static const struct iio_info mma8452_info = {
1331        .attrs = &mma8452_group,
1332        .read_raw = &mma8452_read_raw,
1333        .write_raw = &mma8452_write_raw,
1334        .event_attrs = &mma8452_event_attribute_group,
1335        .read_event_value = &mma8452_read_thresh,
1336        .write_event_value = &mma8452_write_thresh,
1337        .read_event_config = &mma8452_read_event_config,
1338        .write_event_config = &mma8452_write_event_config,
1339        .debugfs_reg_access = &mma8452_reg_access_dbg,
1340        .driver_module = THIS_MODULE,
1341};
1342
1343static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1344
1345static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1346                                              bool state)
1347{
1348        struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1349        struct mma8452_data *data = iio_priv(indio_dev);
1350        int reg, ret;
1351
1352        ret = mma8452_set_runtime_pm_state(data->client, state);
1353        if (ret)
1354                return ret;
1355
1356        reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1357        if (reg < 0)
1358                return reg;
1359
1360        if (state)
1361                reg |= MMA8452_INT_DRDY;
1362        else
1363                reg &= ~MMA8452_INT_DRDY;
1364
1365        return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1366}
1367
1368static const struct iio_trigger_ops mma8452_trigger_ops = {
1369        .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1370        .validate_device = iio_trigger_validate_own_device,
1371        .owner = THIS_MODULE,
1372};
1373
1374static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1375{
1376        struct mma8452_data *data = iio_priv(indio_dev);
1377        struct iio_trigger *trig;
1378        int ret;
1379
1380        trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1381                                      indio_dev->name,
1382                                      indio_dev->id);
1383        if (!trig)
1384                return -ENOMEM;
1385
1386        trig->dev.parent = &data->client->dev;
1387        trig->ops = &mma8452_trigger_ops;
1388        iio_trigger_set_drvdata(trig, indio_dev);
1389
1390        ret = iio_trigger_register(trig);
1391        if (ret)
1392                return ret;
1393
1394        indio_dev->trig = trig;
1395
1396        return 0;
1397}
1398
1399static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1400{
1401        if (indio_dev->trig)
1402                iio_trigger_unregister(indio_dev->trig);
1403}
1404
1405static int mma8452_reset(struct i2c_client *client)
1406{
1407        int i;
1408        int ret;
1409
1410        ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1411                                        MMA8452_CTRL_REG2_RST);
1412        if (ret < 0)
1413                return ret;
1414
1415        for (i = 0; i < 10; i++) {
1416                usleep_range(100, 200);
1417                ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1418                if (ret == -EIO)
1419                        continue; /* I2C comm reset */
1420                if (ret < 0)
1421                        return ret;
1422                if (!(ret & MMA8452_CTRL_REG2_RST))
1423                        return 0;
1424        }
1425
1426        return -ETIMEDOUT;
1427}
1428
1429static const struct of_device_id mma8452_dt_ids[] = {
1430        { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1431        { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1432        { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1433        { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1434        { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1435        { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1436        { }
1437};
1438MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1439
1440static int mma8452_probe(struct i2c_client *client,
1441                         const struct i2c_device_id *id)
1442{
1443        struct mma8452_data *data;
1444        struct iio_dev *indio_dev;
1445        int ret;
1446        const struct of_device_id *match;
1447
1448        match = of_match_device(mma8452_dt_ids, &client->dev);
1449        if (!match) {
1450                dev_err(&client->dev, "unknown device model\n");
1451                return -ENODEV;
1452        }
1453
1454        indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1455        if (!indio_dev)
1456                return -ENOMEM;
1457
1458        data = iio_priv(indio_dev);
1459        data->client = client;
1460        mutex_init(&data->lock);
1461        data->chip_info = match->data;
1462
1463        ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1464        if (ret < 0)
1465                return ret;
1466
1467        switch (ret) {
1468        case MMA8451_DEVICE_ID:
1469        case MMA8452_DEVICE_ID:
1470        case MMA8453_DEVICE_ID:
1471        case MMA8652_DEVICE_ID:
1472        case MMA8653_DEVICE_ID:
1473        case FXLS8471_DEVICE_ID:
1474                if (ret == data->chip_info->chip_id)
1475                        break;
1476        default:
1477                return -ENODEV;
1478        }
1479
1480        dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1481                 match->compatible, data->chip_info->chip_id);
1482
1483        i2c_set_clientdata(client, indio_dev);
1484        indio_dev->info = &mma8452_info;
1485        indio_dev->name = id->name;
1486        indio_dev->dev.parent = &client->dev;
1487        indio_dev->modes = INDIO_DIRECT_MODE;
1488        indio_dev->channels = data->chip_info->channels;
1489        indio_dev->num_channels = data->chip_info->num_channels;
1490        indio_dev->available_scan_masks = mma8452_scan_masks;
1491
1492        ret = mma8452_reset(client);
1493        if (ret < 0)
1494                return ret;
1495
1496        data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1497        ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1498                                        data->data_cfg);
1499        if (ret < 0)
1500                return ret;
1501
1502        /*
1503         * By default set transient threshold to max to avoid events if
1504         * enabling without configuring threshold.
1505         */
1506        ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1507                                        MMA8452_TRANSIENT_THS_MASK);
1508        if (ret < 0)
1509                return ret;
1510
1511        if (client->irq) {
1512                /*
1513                 * Although we enable the interrupt sources once and for
1514                 * all here the event detection itself is not enabled until
1515                 * userspace asks for it by mma8452_write_event_config()
1516                 */
1517                int supported_interrupts = MMA8452_INT_DRDY |
1518                                           MMA8452_INT_TRANS |
1519                                           MMA8452_INT_FF_MT;
1520                int enabled_interrupts = MMA8452_INT_TRANS |
1521                                         MMA8452_INT_FF_MT;
1522                int irq2;
1523
1524                irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1525
1526                if (irq2 == client->irq) {
1527                        dev_dbg(&client->dev, "using interrupt line INT2\n");
1528                } else {
1529                        ret = i2c_smbus_write_byte_data(client,
1530                                                        MMA8452_CTRL_REG5,
1531                                                        supported_interrupts);
1532                        if (ret < 0)
1533                                return ret;
1534
1535                        dev_dbg(&client->dev, "using interrupt line INT1\n");
1536                }
1537
1538                ret = i2c_smbus_write_byte_data(client,
1539                                                MMA8452_CTRL_REG4,
1540                                                enabled_interrupts);
1541                if (ret < 0)
1542                        return ret;
1543
1544                ret = mma8452_trigger_setup(indio_dev);
1545                if (ret < 0)
1546                        return ret;
1547        }
1548
1549        data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1550                          (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1551        ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1552                                        data->ctrl_reg1);
1553        if (ret < 0)
1554                goto trigger_cleanup;
1555
1556        ret = iio_triggered_buffer_setup(indio_dev, NULL,
1557                                         mma8452_trigger_handler, NULL);
1558        if (ret < 0)
1559                goto trigger_cleanup;
1560
1561        if (client->irq) {
1562                ret = devm_request_threaded_irq(&client->dev,
1563                                                client->irq,
1564                                                NULL, mma8452_interrupt,
1565                                                IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1566                                                client->name, indio_dev);
1567                if (ret)
1568                        goto buffer_cleanup;
1569        }
1570
1571        ret = pm_runtime_set_active(&client->dev);
1572        if (ret < 0)
1573                goto buffer_cleanup;
1574
1575        pm_runtime_enable(&client->dev);
1576        pm_runtime_set_autosuspend_delay(&client->dev,
1577                                         MMA8452_AUTO_SUSPEND_DELAY_MS);
1578        pm_runtime_use_autosuspend(&client->dev);
1579
1580        ret = iio_device_register(indio_dev);
1581        if (ret < 0)
1582                goto buffer_cleanup;
1583
1584        ret = mma8452_set_freefall_mode(data, false);
1585        if (ret < 0)
1586                goto buffer_cleanup;
1587
1588        return 0;
1589
1590buffer_cleanup:
1591        iio_triggered_buffer_cleanup(indio_dev);
1592
1593trigger_cleanup:
1594        mma8452_trigger_cleanup(indio_dev);
1595
1596        return ret;
1597}
1598
1599static int mma8452_remove(struct i2c_client *client)
1600{
1601        struct iio_dev *indio_dev = i2c_get_clientdata(client);
1602
1603        iio_device_unregister(indio_dev);
1604
1605        pm_runtime_disable(&client->dev);
1606        pm_runtime_set_suspended(&client->dev);
1607        pm_runtime_put_noidle(&client->dev);
1608
1609        iio_triggered_buffer_cleanup(indio_dev);
1610        mma8452_trigger_cleanup(indio_dev);
1611        mma8452_standby(iio_priv(indio_dev));
1612
1613        return 0;
1614}
1615
1616#ifdef CONFIG_PM
1617static int mma8452_runtime_suspend(struct device *dev)
1618{
1619        struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1620        struct mma8452_data *data = iio_priv(indio_dev);
1621        int ret;
1622
1623        mutex_lock(&data->lock);
1624        ret = mma8452_standby(data);
1625        mutex_unlock(&data->lock);
1626        if (ret < 0) {
1627                dev_err(&data->client->dev, "powering off device failed\n");
1628                return -EAGAIN;
1629        }
1630
1631        return 0;
1632}
1633
1634static int mma8452_runtime_resume(struct device *dev)
1635{
1636        struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1637        struct mma8452_data *data = iio_priv(indio_dev);
1638        int ret, sleep_val;
1639
1640        ret = mma8452_active(data);
1641        if (ret < 0)
1642                return ret;
1643
1644        ret = mma8452_get_odr_index(data);
1645        sleep_val = 1000 / mma8452_samp_freq[ret][0];
1646        if (sleep_val < 20)
1647                usleep_range(sleep_val * 1000, 20000);
1648        else
1649                msleep_interruptible(sleep_val);
1650
1651        return 0;
1652}
1653#endif
1654
1655#ifdef CONFIG_PM_SLEEP
1656static int mma8452_suspend(struct device *dev)
1657{
1658        return mma8452_standby(iio_priv(i2c_get_clientdata(
1659                to_i2c_client(dev))));
1660}
1661
1662static int mma8452_resume(struct device *dev)
1663{
1664        return mma8452_active(iio_priv(i2c_get_clientdata(
1665                to_i2c_client(dev))));
1666}
1667#endif
1668
1669static const struct dev_pm_ops mma8452_pm_ops = {
1670        SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume)
1671        SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1672                           mma8452_runtime_resume, NULL)
1673};
1674
1675static const struct i2c_device_id mma8452_id[] = {
1676        { "mma8451", mma8451 },
1677        { "mma8452", mma8452 },
1678        { "mma8453", mma8453 },
1679        { "mma8652", mma8652 },
1680        { "mma8653", mma8653 },
1681        { "fxls8471", fxls8471 },
1682        { }
1683};
1684MODULE_DEVICE_TABLE(i2c, mma8452_id);
1685
1686static struct i2c_driver mma8452_driver = {
1687        .driver = {
1688                .name   = "mma8452",
1689                .of_match_table = of_match_ptr(mma8452_dt_ids),
1690                .pm     = &mma8452_pm_ops,
1691        },
1692        .probe = mma8452_probe,
1693        .remove = mma8452_remove,
1694        .id_table = mma8452_id,
1695};
1696module_i2c_driver(mma8452_driver);
1697
1698MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1699MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1700MODULE_LICENSE("GPL");
1701